Code Review / openocd.git / blob
? search:
summary | shortlog | log | commit | commitdiff | review | tree
history | raw | HEAD
Spen spotted a bug in warning for missing srst_pulls_trst
[openocd.git] / src / target / arm7_9_common.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
20 #ifdef HAVE_CONFIG_H
21 #include "config.h"
22 #endif
23
24 #include "replacements.h"
25
26 #include "embeddedice.h"
27 #include "target.h"
28 #include "target_request.h"
29 #include "armv4_5.h"
30 #include "arm_jtag.h"
31 #include "jtag.h"
32 #include "log.h"
33 #include "arm7_9_common.h"
34 #include "breakpoints.h"
35
36 #include <stdlib.h>
37 #include <string.h>
38 #include <unistd.h>
39
40 #include <sys/types.h>
41 #include <sys/stat.h>
42 #include <sys/time.h>
43 #include <errno.h>
44
45 int arm7_9_debug_entry(target_t *target);
46 int arm7_9_enable_sw_bkpts(struct target_s *target);
47
48 /* command handler forward declarations */
49 int handle_arm7_9_write_xpsr_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
50 int handle_arm7_9_write_xpsr_im8_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
51 int handle_arm7_9_read_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
52 int handle_arm7_9_write_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
53 int handle_arm7_9_sw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
54 int handle_arm7_9_force_hw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
55 int handle_arm7_9_dbgrq_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
56 int handle_arm7_9_fast_memory_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
57 int handle_arm7_9_dcc_downloads_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
58 int handle_arm7_9_etm_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
59
60 int arm7_9_reinit_embeddedice(target_t *target)
61 {
62 armv4_5_common_t *armv4_5 = target->arch_info;
63 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
64
65 breakpoint_t *breakpoint = target->breakpoints;
66
67 arm7_9->wp_available = 2;
68 arm7_9->wp0_used = 0;
69 arm7_9->wp1_used = 0;
70
71 /* mark all hardware breakpoints as unset */
72 while (breakpoint)
73 {
74 if (breakpoint->type == BKPT_HARD)
75 {
76 breakpoint->set = 0;
77 }
78 breakpoint = breakpoint->next;
79 }
80
81 if (arm7_9->sw_bkpts_enabled && arm7_9->sw_bkpts_use_wp)
82 {
83 arm7_9->sw_bkpts_enabled = 0;
84 arm7_9_enable_sw_bkpts(target);
85 }
86
87 return ERROR_OK;
88 }
89
90 /* set things up after a reset / on startup */
91 int arm7_9_setup(target_t *target)
92 {
93 /* a test-logic reset have occured
94 * the EmbeddedICE registers have been reset
95 * hardware breakpoints have been cleared
96 */
97 return arm7_9_reinit_embeddedice(target);
98 }
99
100 int arm7_9_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p)
101 {
102 armv4_5_common_t *armv4_5 = target->arch_info;
103 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
104
105 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
106 {
107 return -1;
108 }
109
110 if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
111 {
112 return -1;
113 }
114
115 *armv4_5_p = armv4_5;
116 *arm7_9_p = arm7_9;
117
118 return ERROR_OK;
119 }
120
121 int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
122 {
123 armv4_5_common_t *armv4_5 = target->arch_info;
124 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
125
126 if (target->state != TARGET_HALTED)
127 {
128 LOG_WARNING("target not halted");
129 return ERROR_TARGET_NOT_HALTED;
130 }
131
132 if (arm7_9->force_hw_bkpts)
133 breakpoint->type = BKPT_HARD;
134
135 if (breakpoint->set)
136 {
137 LOG_WARNING("breakpoint already set");
138 return ERROR_OK;
139 }
140
141 if (breakpoint->type == BKPT_HARD)
142 {
143 /* either an ARM (4 byte) or Thumb (2 byte) breakpoint */
144 u32 mask = (breakpoint->length == 4) ? 0x3u : 0x1u;
145 if (!arm7_9->wp0_used)
146 {
147 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], breakpoint->address);
148 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask);
149 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffffu);
150 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
151 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
152
153 jtag_execute_queue();
154 arm7_9->wp0_used = 1;
155 breakpoint->set = 1;
156 }
157 else if (!arm7_9->wp1_used)
158 {
159 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], breakpoint->address);
160 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask);
161 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffffu);
162 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
163 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
164
165 jtag_execute_queue();
166 arm7_9->wp1_used = 1;
167 breakpoint->set = 2;
168 }
169 else
170 {
171 LOG_ERROR("BUG: no hardware comparator available");
172 return ERROR_OK;
173 }
174 }
175 else if (breakpoint->type == BKPT_SOFT)
176 {
177 if (breakpoint->length == 4)
178 {
179 u32 verify = 0xffffffff;
180 /* keep the original instruction in target endianness */
181 target->type->read_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr);
182 /* write the breakpoint instruction in target endianness (arm7_9->arm_bkpt is host endian) */
183 target_write_u32(target, breakpoint->address, arm7_9->arm_bkpt);
184
185 target->type->read_memory(target, breakpoint->address, 4, 1, (u8 *)&verify);
186 if (verify != arm7_9->arm_bkpt)
187 {
188 LOG_ERROR("Unable to set 32 bit software breakpoint at address %08x", breakpoint->address);
189 return ERROR_OK;
190 }
191 }
192 else
193 {
194 u16 verify = 0xffff;
195 /* keep the original instruction in target endianness */
196 target->type->read_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr);
197 /* write the breakpoint instruction in target endianness (arm7_9->thumb_bkpt is host endian) */
198 target_write_u16(target, breakpoint->address, arm7_9->thumb_bkpt);
199
200 target->type->read_memory(target, breakpoint->address, 2, 1, (u8 *)&verify);
201 if (verify != arm7_9->thumb_bkpt)
202 {
203 LOG_ERROR("Unable to set thumb software breakpoint at address %08x", breakpoint->address);
204 return ERROR_OK;
205 }
206 }
207 breakpoint->set = 1;
208 }
209
210 return ERROR_OK;
211
212 }
213
214 int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
215 {
216 armv4_5_common_t *armv4_5 = target->arch_info;
217 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
218
219 if (target->state != TARGET_HALTED)
220 {
221 LOG_WARNING("target not halted");
222 return ERROR_TARGET_NOT_HALTED;
223 }
224
225 if (!breakpoint->set)
226 {
227 LOG_WARNING("breakpoint not set");
228 return ERROR_OK;
229 }
230
231 if (breakpoint->type == BKPT_HARD)
232 {
233 if (breakpoint->set == 1)
234 {
235 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
236 jtag_execute_queue();
237 arm7_9->wp0_used = 0;
238 }
239 else if (breakpoint->set == 2)
240 {
241 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
242 jtag_execute_queue();
243 arm7_9->wp1_used = 0;
244 }
245 breakpoint->set = 0;
246 }
247 else
248 {
249 /* restore original instruction (kept in target endianness) */
250 if (breakpoint->length == 4)
251 {
252 u32 current_instr;
253 /* check that user program as not modified breakpoint instruction */
254 target->type->read_memory(target, breakpoint->address, 4, 1, (u8*)&current_instr);
255 if (current_instr==arm7_9->arm_bkpt)
256 target->type->write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr);
257 }
258 else
259 {
260 u16 current_instr;
261 /* check that user program as not modified breakpoint instruction */
262 target->type->read_memory(target, breakpoint->address, 2, 1, (u8*)&current_instr);
263 if (current_instr==arm7_9->thumb_bkpt)
264 target->type->write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr);
265 }
266 breakpoint->set = 0;
267 }
268
269 return ERROR_OK;
270 }
271
272 int arm7_9_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
273 {
274 armv4_5_common_t *armv4_5 = target->arch_info;
275 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
276
277 if (target->state != TARGET_HALTED)
278 {
279 LOG_WARNING("target not halted");
280 return ERROR_TARGET_NOT_HALTED;
281 }
282
283 if (arm7_9->force_hw_bkpts)
284 {
285 LOG_DEBUG("forcing use of hardware breakpoint at address 0x%8.8x", breakpoint->address);
286 breakpoint->type = BKPT_HARD;
287 }
288
289 if ((breakpoint->type == BKPT_SOFT) && (arm7_9->sw_bkpts_enabled == 0))
290 {
291 LOG_INFO("sw breakpoint requested, but software breakpoints not enabled");
292 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
293 }
294
295 if ((breakpoint->type == BKPT_HARD) && (arm7_9->wp_available < 1))
296 {
297 LOG_INFO("no watchpoint unit available for hardware breakpoint");
298 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
299 }
300
301 if ((breakpoint->length != 2) && (breakpoint->length != 4))
302 {
303 LOG_INFO("only breakpoints of two (Thumb) or four (ARM) bytes length supported");
304 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
305 }
306
307 if (breakpoint->type == BKPT_HARD)
308 arm7_9->wp_available--;
309
310 return ERROR_OK;
311 }
312
313 int arm7_9_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
314 {
315 armv4_5_common_t *armv4_5 = target->arch_info;
316 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
317
318 if (target->state != TARGET_HALTED)
319 {
320 LOG_WARNING("target not halted");
321 return ERROR_TARGET_NOT_HALTED;
322 }
323
324 if (breakpoint->set)
325 {
326 arm7_9_unset_breakpoint(target, breakpoint);
327 }
328
329 if (breakpoint->type == BKPT_HARD)
330 arm7_9->wp_available++;
331
332 return ERROR_OK;
333 }
334
335 int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
336 {
337 armv4_5_common_t *armv4_5 = target->arch_info;
338 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
339 int rw_mask = 1;
340 u32 mask;
341
342 mask = watchpoint->length - 1;
343
344 if (target->state != TARGET_HALTED)
345 {
346 LOG_WARNING("target not halted");
347 return ERROR_TARGET_NOT_HALTED;
348 }
349
350 if (watchpoint->rw == WPT_ACCESS)
351 rw_mask = 0;
352 else
353 rw_mask = 1;
354
355 if (!arm7_9->wp0_used)
356 {
357 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], watchpoint->address);
358 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask);
359 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], watchpoint->mask);
360 if( watchpoint->mask != 0xffffffffu )
361 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], watchpoint->value);
362 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
363 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
364
365 jtag_execute_queue();
366 watchpoint->set = 1;
367 arm7_9->wp0_used = 2;
368 }
369 else if (!arm7_9->wp1_used)
370 {
371 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], watchpoint->address);
372 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask);
373 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], watchpoint->mask);
374 if( watchpoint->mask != 0xffffffffu )
375 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], watchpoint->value);
376 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
377 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
378
379 jtag_execute_queue();
380 watchpoint->set = 2;
381 arm7_9->wp1_used = 2;
382 }
383 else
384 {
385 LOG_ERROR("BUG: no hardware comparator available");
386 return ERROR_OK;
387 }
388
389 return ERROR_OK;
390 }
391
392 int arm7_9_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
393 {
394 armv4_5_common_t *armv4_5 = target->arch_info;
395 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
396
397 if (target->state != TARGET_HALTED)
398 {
399 LOG_WARNING("target not halted");
400 return ERROR_TARGET_NOT_HALTED;
401 }
402
403 if (!watchpoint->set)
404 {
405 LOG_WARNING("breakpoint not set");
406 return ERROR_OK;
407 }
408
409 if (watchpoint->set == 1)
410 {
411 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
412 jtag_execute_queue();
413 arm7_9->wp0_used = 0;
414 }
415 else if (watchpoint->set == 2)
416 {
417 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
418 jtag_execute_queue();
419 arm7_9->wp1_used = 0;
420 }
421 watchpoint->set = 0;
422
423 return ERROR_OK;
424 }
425
426 int arm7_9_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
427 {
428 armv4_5_common_t *armv4_5 = target->arch_info;
429 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
430
431 if (target->state != TARGET_HALTED)
432 {
433 LOG_WARNING("target not halted");
434 return ERROR_TARGET_NOT_HALTED;
435 }
436
437 if (arm7_9->wp_available < 1)
438 {
439 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
440 }
441
442 if ((watchpoint->length != 1) && (watchpoint->length != 2) && (watchpoint->length != 4))
443 {
444 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
445 }
446
447 arm7_9->wp_available--;
448
449 return ERROR_OK;
450 }
451
452 int arm7_9_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
453 {
454 armv4_5_common_t *armv4_5 = target->arch_info;
455 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
456
457 if (target->state != TARGET_HALTED)
458 {
459 LOG_WARNING("target not halted");
460 return ERROR_TARGET_NOT_HALTED;
461 }
462
463 if (watchpoint->set)
464 {
465 arm7_9_unset_watchpoint(target, watchpoint);
466 }
467
468 arm7_9->wp_available++;
469
470 return ERROR_OK;
471 }
472
473 int arm7_9_enable_sw_bkpts(struct target_s *target)
474 {
475 armv4_5_common_t *armv4_5 = target->arch_info;
476 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
477 int retval;
478
479 if (arm7_9->sw_bkpts_enabled)
480 return ERROR_OK;
481
482 if (arm7_9->wp_available < 1)
483 {
484 LOG_WARNING("can't enable sw breakpoints with no watchpoint unit available");
485 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
486 }
487 arm7_9->wp_available--;
488
489 if (!arm7_9->wp0_used)
490 {
491 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], arm7_9->arm_bkpt);
492 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0x0);
493 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffffu);
494 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
495 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
496 arm7_9->sw_bkpts_enabled = 1;
497 arm7_9->wp0_used = 3;
498 }
499 else if (!arm7_9->wp1_used)
500 {
501 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], arm7_9->arm_bkpt);
502 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0x0);
503 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0xffffffffu);
504 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
505 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
506 arm7_9->sw_bkpts_enabled = 2;
507 arm7_9->wp1_used = 3;
508 }
509 else
510 {
511 LOG_ERROR("BUG: both watchpoints used, but wp_available >= 1");
512 return ERROR_FAIL;
513 }
514
515 if ((retval = jtag_execute_queue()) != ERROR_OK)
516 {
517 LOG_ERROR("error writing EmbeddedICE registers to enable sw breakpoints");
518 return ERROR_FAIL;
519 };
520
521 return ERROR_OK;
522 }
523
524 int arm7_9_disable_sw_bkpts(struct target_s *target)
525 {
526 armv4_5_common_t *armv4_5 = target->arch_info;
527 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
528
529 if (!arm7_9->sw_bkpts_enabled)
530 return ERROR_OK;
531
532 if (arm7_9->sw_bkpts_enabled == 1)
533 {
534 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
535 arm7_9->sw_bkpts_enabled = 0;
536 arm7_9->wp0_used = 0;
537 arm7_9->wp_available++;
538 }
539 else if (arm7_9->sw_bkpts_enabled == 2)
540 {
541 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
542 arm7_9->sw_bkpts_enabled = 0;
543 arm7_9->wp1_used = 0;
544 arm7_9->wp_available++;
545 }
546
547 return ERROR_OK;
548 }
549
550 int arm7_9_execute_sys_speed(struct target_s *target)
551 {
552 int timeout;
553 int retval;
554
555 armv4_5_common_t *armv4_5 = target->arch_info;
556 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
557 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
558 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
559
560 /* set RESTART instruction */
561 jtag_add_end_state(TAP_RTI);
562 if (arm7_9->need_bypass_before_restart) {
563 arm7_9->need_bypass_before_restart = 0;
564 arm_jtag_set_instr(jtag_info, 0xf, NULL);
565 }
566 arm_jtag_set_instr(jtag_info, 0x4, NULL);
567
568 for (timeout=0; timeout<50; timeout++)
569 {
570 /* read debug status register */
571 embeddedice_read_reg(dbg_stat);
572 if ((retval = jtag_execute_queue()) != ERROR_OK)
573 return retval;
574 if ((buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))
575 && (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_SYSCOMP, 1)))
576 break;
577 usleep(100000);
578 }
579 if (timeout == 50)
580 {
581 LOG_ERROR("timeout waiting for SYSCOMP & DBGACK, last DBG_STATUS: %x", buf_get_u32(dbg_stat->value, 0, dbg_stat->size));
582 return ERROR_TARGET_TIMEOUT;
583 }
584
585 return ERROR_OK;
586 }
587
588 int arm7_9_execute_fast_sys_speed(struct target_s *target)
589 {
590 static int set=0;
591 static u8 check_value[4], check_mask[4];
592
593 armv4_5_common_t *armv4_5 = target->arch_info;
594 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
595 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
596 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
597
598 /* set RESTART instruction */
599 jtag_add_end_state(TAP_RTI);
600 if (arm7_9->need_bypass_before_restart) {
601 arm7_9->need_bypass_before_restart = 0;
602 arm_jtag_set_instr(jtag_info, 0xf, NULL);
603 }
604 arm_jtag_set_instr(jtag_info, 0x4, NULL);
605
606 if (!set)
607 {
608 /* check for DBGACK and SYSCOMP set (others don't care) */
609
610 /* NB! These are constants that must be available until after next jtag_execute() and
611 we evaluate the values upon first execution in lieu of setting up these constants
612 during early setup.
613 */
614 buf_set_u32(check_value, 0, 32, 0x9);
615 buf_set_u32(check_mask, 0, 32, 0x9);
616 set=1;
617 }
618
619 /* read debug status register */
620 embeddedice_read_reg_w_check(dbg_stat, check_value, check_value);
621
622 return ERROR_OK;
623 }
624
625 int arm7_9_target_request_data(target_t *target, u32 size, u8 *buffer)
626 {
627 armv4_5_common_t *armv4_5 = target->arch_info;
628 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
629 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
630 u32 *data;
631 int i;
632
633 data = malloc(size * (sizeof(u32)));
634
635 embeddedice_receive(jtag_info, data, size);
636
637 for (i = 0; i < size; i++)
638 {
639 h_u32_to_le(buffer + (i * 4), data[i]);
640 }
641
642 free(data);
643
644 return ERROR_OK;
645 }
646
647 int arm7_9_handle_target_request(void *priv)
648 {
649 target_t *target = priv;
650 if (!target->type->examined)
651 return ERROR_OK;
652 armv4_5_common_t *armv4_5 = target->arch_info;
653 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
654 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
655 reg_t *dcc_control = &arm7_9->eice_cache->reg_list[EICE_COMMS_CTRL];
656
657
658 if (!target->dbg_msg_enabled)
659 return ERROR_OK;
660
661 if (target->state == TARGET_RUNNING)
662 {
663 /* read DCC control register */
664 embeddedice_read_reg(dcc_control);
665 jtag_execute_queue();
666
667 /* check W bit */
668 if (buf_get_u32(dcc_control->value, 1, 1) == 1)
669 {
670 u32 request;
671
672 embeddedice_receive(jtag_info, &request, 1);
673 target_request(target, request);
674 }
675 }
676
677 return ERROR_OK;
678 }
679
680 int arm7_9_poll(target_t *target)
681 {
682 int retval;
683 armv4_5_common_t *armv4_5 = target->arch_info;
684 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
685 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
686
687 /* read debug status register */
688 embeddedice_read_reg(dbg_stat);
689 if ((retval = jtag_execute_queue()) != ERROR_OK)
690 {
691 return retval;
692 }
693
694 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))
695 {
696 /* LOG_DEBUG("DBGACK set, dbg_state->value: 0x%x", buf_get_u32(dbg_stat->value, 0, 32));*/
697 if (target->state == TARGET_UNKNOWN)
698 {
699 target->state = TARGET_RUNNING;
700 LOG_WARNING("DBGACK set while target was in unknown state. Reset or initialize target.");
701 }
702 if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET))
703 {
704 int check_pc=0;
705 if (target->state == TARGET_RESET)
706 {
707 if ((target->reset_mode == RESET_HALT) || (target->reset_mode == RESET_INIT))
708 {
709 if ((jtag_reset_config & RESET_SRST_PULLS_TRST)==0)
710 {
711 check_pc = 1;
712 }
713 }
714 }
715
716 target->state = TARGET_HALTED;
717
718 if ((retval = arm7_9_debug_entry(target)) != ERROR_OK)
719 return retval;
720
721 if (check_pc)
722 {
723 reg_t *reg = register_get_by_name(target->reg_cache, "pc", 1);
724 u32 t=*((u32 *)reg->value);
725 if (t!=0)
726 {
727 LOG_ERROR("PC was not 0. Does this target need srst_pulls_trst?");
728 }
729 }
730
731 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
732 }
733 if (target->state == TARGET_DEBUG_RUNNING)
734 {
735 target->state = TARGET_HALTED;
736 if ((retval = arm7_9_debug_entry(target)) != ERROR_OK)
737 return retval;
738
739 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
740 }
741 if (target->state != TARGET_HALTED)
742 {
743 LOG_WARNING("DBGACK set, but the target did not end up in the halted stated %d", target->state);
744 }
745 }
746 else
747 {
748 if (target->state != TARGET_DEBUG_RUNNING)
749 target->state = TARGET_RUNNING;
750 }
751
752 return ERROR_OK;
753 }
754
755 /*
756 Some -S targets (ARM966E-S in the STR912 isn't affected, ARM926EJ-S
757 in the LPC3180 and AT91SAM9260 is affected) completely stop the JTAG clock
758 while the core is held in reset(SRST). It isn't possible to program the halt
759 condition once reset was asserted, hence a hook that allows the target to set
760 up its reset-halt condition prior to asserting reset.
761 */
762
763 int arm7_9_assert_reset(target_t *target)
764 {
765 armv4_5_common_t *armv4_5 = target->arch_info;
766 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
767 LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
768
769 if (!(jtag_reset_config & RESET_HAS_SRST))
770 {
771 LOG_ERROR("Can't assert SRST");
772 return ERROR_FAIL;
773 }
774
775 if ((target->reset_mode == RESET_HALT) || (target->reset_mode == RESET_INIT))
776 {
777 /*
778 * Some targets do not support communication while SRST is asserted. We need to
779 * set up the reset vector catch here.
780 *
781 * If TRST is asserted, then these settings will be reset anyway, so setting them
782 * here is harmless.
783 */
784 if (arm7_9->has_vector_catch)
785 {
786 /* program vector catch register to catch reset vector */
787 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH], 0x1);
788 }
789 else
790 {
791 /* program watchpoint unit to match on reset vector address */
792 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0x3);
793 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0x0);
794 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x100);
795 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xf7);
796 }
797 }
798
799 /* here we should issue a srst only, but we may have to assert trst as well */
800 if (jtag_reset_config & RESET_SRST_PULLS_TRST)
801 {
802 jtag_add_reset(1, 1);
803 } else
804 {
805 jtag_add_reset(0, 1);
806 }
807
808
809 target->state = TARGET_RESET;
810 jtag_add_sleep(50000);
811
812 armv4_5_invalidate_core_regs(target);
813
814 return ERROR_OK;
815
816 }
817
818 int arm7_9_deassert_reset(target_t *target)
819 {
820 LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
821
822 /* deassert reset lines */
823 jtag_add_reset(0, 0);
824
825 return ERROR_OK;
826 }
827
828 int arm7_9_clear_halt(target_t *target)
829 {
830 armv4_5_common_t *armv4_5 = target->arch_info;
831 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
832 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
833
834 /* we used DBGRQ only if we didn't come out of reset */
835 if (!arm7_9->debug_entry_from_reset && arm7_9->use_dbgrq)
836 {
837 /* program EmbeddedICE Debug Control Register to deassert DBGRQ
838 */
839 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
840 embeddedice_store_reg(dbg_ctrl);
841 }
842 else
843 {
844 if (arm7_9->debug_entry_from_reset && arm7_9->has_vector_catch)
845 {
846 /* if we came out of reset, and vector catch is supported, we used
847 * vector catch to enter debug state
848 * restore the register in that case
849 */
850 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH]);
851 }
852 else
853 {
854 /* restore registers if watchpoint unit 0 was in use
855 */
856 if (arm7_9->wp0_used)
857 {
858 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
859 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);
860 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK]);
861 }
862 /* control value always has to be restored, as it was either disabled,
863 * or enabled with possibly different bits
864 */
865 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]);
866 }
867 }
868
869 return ERROR_OK;
870 }
871
872 int arm7_9_soft_reset_halt(struct target_s *target)
873 {
874 armv4_5_common_t *armv4_5 = target->arch_info;
875 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
876 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
877 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
878 int i;
879 int retval;
880
881 if ((retval=target_halt(target))!=ERROR_OK)
882 return retval;
883
884 for (i=0; i<10; i++)
885 {
886 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) != 0)
887 break;
888 embeddedice_read_reg(dbg_stat);
889 if ((retval=jtag_execute_queue())!=ERROR_OK)
890 return retval;
891 /* do not eat all CPU, time out after 1 se*/
892 usleep(100*1000);
893
894 }
895 if (i==10)
896 {
897 LOG_ERROR("Failed to halt CPU after 1 sec");
898 return ERROR_TARGET_TIMEOUT;
899 }
900 target->state = TARGET_HALTED;
901
902 /* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS
903 * ensure that DBGRQ is cleared
904 */
905 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
906 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
907 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 1);
908 embeddedice_store_reg(dbg_ctrl);
909
910 arm7_9_clear_halt(target);
911
912 /* if the target is in Thumb state, change to ARM state */
913 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_ITBIT, 1))
914 {
915 u32 r0_thumb, pc_thumb;
916 LOG_DEBUG("target entered debug from Thumb state, changing to ARM");
917 /* Entered debug from Thumb mode */
918 armv4_5->core_state = ARMV4_5_STATE_THUMB;
919 arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb);
920 }
921
922 /* all register content is now invalid */
923 armv4_5_invalidate_core_regs(target);
924
925 /* SVC, ARM state, IRQ and FIQ disabled */
926 buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
927 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
928 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
929
930 /* start fetching from 0x0 */
931 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
932 armv4_5->core_cache->reg_list[15].dirty = 1;
933 armv4_5->core_cache->reg_list[15].valid = 1;
934
935 armv4_5->core_mode = ARMV4_5_MODE_SVC;
936 armv4_5->core_state = ARMV4_5_STATE_ARM;
937
938 if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
939 return ERROR_FAIL;
940
941 /* reset registers */
942 for (i = 0; i <= 14; i++)
943 {
944 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32, 0xffffffff);
945 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 1;
946 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid = 1;
947 }
948
949 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
950
951 return ERROR_OK;
952 }
953
954 int arm7_9_halt(target_t *target)
955 {
956 armv4_5_common_t *armv4_5 = target->arch_info;
957 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
958 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
959
960 LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
961
962 if (target->state == TARGET_HALTED)
963 {
964 LOG_DEBUG("target was already halted");
965 return ERROR_OK;
966 }
967
968 if (target->state == TARGET_UNKNOWN)
969 {
970 LOG_WARNING("target was in unknown state when halt was requested");
971 }
972
973 if (target->state == TARGET_RESET)
974 {
975 if ((jtag_reset_config & RESET_SRST_PULLS_TRST) && jtag_srst)
976 {
977 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
978 return ERROR_TARGET_FAILURE;
979 }
980 else
981 {
982 /* we came here in a reset_halt or reset_init sequence
983 * debug entry was already prepared in arm7_9_prepare_reset_halt()
984 */
985 target->debug_reason = DBG_REASON_DBGRQ;
986
987 return ERROR_OK;
988 }
989 }
990
991 if (arm7_9->use_dbgrq)
992 {
993 /* program EmbeddedICE Debug Control Register to assert DBGRQ
994 */
995 if (arm7_9->set_special_dbgrq) {
996 arm7_9->set_special_dbgrq(target);
997 } else {
998 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 1);
999 embeddedice_store_reg(dbg_ctrl);
1000 }
1001 }
1002 else
1003 {
1004 /* program watchpoint unit to match on any address
1005 */
1006 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
1007 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
1008 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x100);
1009 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xf7);
1010 }
1011
1012 target->debug_reason = DBG_REASON_DBGRQ;
1013
1014 return ERROR_OK;
1015 }
1016
1017 int arm7_9_debug_entry(target_t *target)
1018 {
1019 int i;
1020 u32 context[16];
1021 u32* context_p[16];
1022 u32 r0_thumb, pc_thumb;
1023 u32 cpsr;
1024 int retval;
1025 /* get pointers to arch-specific information */
1026 armv4_5_common_t *armv4_5 = target->arch_info;
1027 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1028 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
1029 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1030
1031 #ifdef _DEBUG_ARM7_9_
1032 LOG_DEBUG("-");
1033 #endif
1034
1035 if (arm7_9->pre_debug_entry)
1036 arm7_9->pre_debug_entry(target);
1037
1038 /* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS
1039 * ensure that DBGRQ is cleared
1040 */
1041 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
1042 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
1043 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 1);
1044 embeddedice_store_reg(dbg_ctrl);
1045
1046 arm7_9_clear_halt(target);
1047
1048 if ((retval = jtag_execute_queue()) != ERROR_OK)
1049 {
1050 return retval;
1051 }
1052
1053 if ((retval = arm7_9->examine_debug_reason(target)) != ERROR_OK)
1054 return retval;
1055
1056
1057 if (target->state != TARGET_HALTED)
1058 {
1059 LOG_WARNING("target not halted");
1060 return ERROR_TARGET_NOT_HALTED;
1061 }
1062
1063 /* if the target is in Thumb state, change to ARM state */
1064 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_ITBIT, 1))
1065 {
1066 LOG_DEBUG("target entered debug from Thumb state");
1067 /* Entered debug from Thumb mode */
1068 armv4_5->core_state = ARMV4_5_STATE_THUMB;
1069 arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb);
1070 LOG_DEBUG("r0_thumb: 0x%8.8x, pc_thumb: 0x%8.8x", r0_thumb, pc_thumb);
1071 }
1072 else
1073 {
1074 LOG_DEBUG("target entered debug from ARM state");
1075 /* Entered debug from ARM mode */
1076 armv4_5->core_state = ARMV4_5_STATE_ARM;
1077 }
1078
1079 for (i = 0; i < 16; i++)
1080 context_p[i] = &context[i];
1081 /* save core registers (r0 - r15 of current core mode) */
1082 arm7_9->read_core_regs(target, 0xffff, context_p);
1083
1084 arm7_9->read_xpsr(target, &cpsr, 0);
1085
1086 if ((retval = jtag_execute_queue()) != ERROR_OK)
1087 return retval;
1088
1089 /* if the core has been executing in Thumb state, set the T bit */
1090 if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1091 cpsr |= 0x20;
1092
1093 buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32, cpsr);
1094 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 0;
1095 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
1096
1097 armv4_5->core_mode = cpsr & 0x1f;
1098
1099 if (armv4_5_mode_to_number(armv4_5->core_mode) == -1)
1100 {
1101 target->state = TARGET_UNKNOWN;
1102 LOG_ERROR("cpsr contains invalid mode value - communication failure");
1103 return ERROR_TARGET_FAILURE;
1104 }
1105
1106 LOG_DEBUG("target entered debug state in %s mode", armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)]);
1107
1108 if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1109 {
1110 LOG_DEBUG("thumb state, applying fixups");
1111 context[0] = r0_thumb;
1112 context[15] = pc_thumb;
1113 } else if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1114 {
1115 /* adjust value stored by STM */
1116 context[15] -= 3 * 4;
1117 }
1118
1119 if ((target->debug_reason == DBG_REASON_BREAKPOINT)
1120 || (target->debug_reason == DBG_REASON_SINGLESTEP)
1121 || (target->debug_reason == DBG_REASON_WATCHPOINT)
1122 || (target->debug_reason == DBG_REASON_WPTANDBKPT)
1123 || ((target->debug_reason == DBG_REASON_DBGRQ) && (arm7_9->use_dbgrq == 0)))
1124 context[15] -= 3 * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2);
1125 else if (target->debug_reason == DBG_REASON_DBGRQ)
1126 context[15] -= arm7_9->dbgreq_adjust_pc * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2);
1127 else
1128 {
1129 LOG_ERROR("unknown debug reason: %i", target->debug_reason);
1130 }
1131
1132 if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
1133 return ERROR_FAIL;
1134
1135 for (i=0; i<=15; i++)
1136 {
1137 LOG_DEBUG("r%i: 0x%8.8x", i, context[i]);
1138 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32, context[i]);
1139 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 0;
1140 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid = 1;
1141 }
1142
1143 LOG_DEBUG("entered debug state at PC 0x%x", context[15]);
1144
1145 if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
1146 return ERROR_FAIL;
1147
1148 /* exceptions other than USR & SYS have a saved program status register */
1149 if ((armv4_5->core_mode != ARMV4_5_MODE_USR) && (armv4_5->core_mode != ARMV4_5_MODE_SYS))
1150 {
1151 u32 spsr;
1152 arm7_9->read_xpsr(target, &spsr, 1);
1153 jtag_execute_queue();
1154 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).value, 0, 32, spsr);
1155 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).dirty = 0;
1156 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).valid = 1;
1157 }
1158
1159 /* r0 and r15 (pc) have to be restored later */
1160 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).valid;
1161 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15).valid;
1162
1163 if ((retval = jtag_execute_queue()) != ERROR_OK)
1164 return retval;
1165
1166 if (arm7_9->post_debug_entry)
1167 arm7_9->post_debug_entry(target);
1168
1169 return ERROR_OK;
1170 }
1171
1172 int arm7_9_full_context(target_t *target)
1173 {
1174 int i;
1175 int retval;
1176 armv4_5_common_t *armv4_5 = target->arch_info;
1177 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1178
1179 LOG_DEBUG("-");
1180
1181 if (target->state != TARGET_HALTED)
1182 {
1183 LOG_WARNING("target not halted");
1184 return ERROR_TARGET_NOT_HALTED;
1185 }
1186
1187 if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
1188 return ERROR_FAIL;
1189
1190 /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
1191 * SYS shares registers with User, so we don't touch SYS
1192 */
1193 for(i = 0; i < 6; i++)
1194 {
1195 u32 mask = 0;
1196 u32* reg_p[16];
1197 int j;
1198 int valid = 1;
1199
1200 /* check if there are invalid registers in the current mode
1201 */
1202 for (j = 0; j <= 16; j++)
1203 {
1204 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid == 0)
1205 valid = 0;
1206 }
1207
1208 if (!valid)
1209 {
1210 u32 tmp_cpsr;
1211
1212 /* change processor mode (and mask T bit) */
1213 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1214 tmp_cpsr |= armv4_5_number_to_mode(i);
1215 tmp_cpsr &= ~0x20;
1216 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1217
1218 for (j = 0; j < 15; j++)
1219 {
1220 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid == 0)
1221 {
1222 reg_p[j] = (u32*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).value;
1223 mask |= 1 << j;
1224 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid = 1;
1225 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).dirty = 0;
1226 }
1227 }
1228
1229 /* if only the PSR is invalid, mask is all zeroes */
1230 if (mask)
1231 arm7_9->read_core_regs(target, mask, reg_p);
1232
1233 /* check if the PSR has to be read */
1234 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).valid == 0)
1235 {
1236 arm7_9->read_xpsr(target, (u32*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).value, 1);
1237 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).valid = 1;
1238 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).dirty = 0;
1239 }
1240 }
1241 }
1242
1243 /* restore processor mode (mask T bit) */
1244 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
1245
1246 if ((retval = jtag_execute_queue()) != ERROR_OK)
1247 {
1248 return retval;
1249 }
1250 return ERROR_OK;
1251 }
1252
1253 int arm7_9_restore_context(target_t *target)
1254 {
1255 armv4_5_common_t *armv4_5 = target->arch_info;
1256 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1257 reg_t *reg;
1258 armv4_5_core_reg_t *reg_arch_info;
1259 enum armv4_5_mode current_mode = armv4_5->core_mode;
1260 int i, j;
1261 int dirty;
1262 int mode_change;
1263
1264 LOG_DEBUG("-");
1265
1266 if (target->state != TARGET_HALTED)
1267 {
1268 LOG_WARNING("target not halted");
1269 return ERROR_TARGET_NOT_HALTED;
1270 }
1271
1272 if (arm7_9->pre_restore_context)
1273 arm7_9->pre_restore_context(target);
1274
1275 if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
1276 return ERROR_FAIL;
1277
1278 /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
1279 * SYS shares registers with User, so we don't touch SYS
1280 */
1281 for (i = 0; i < 6; i++)
1282 {
1283 LOG_DEBUG("examining %s mode", armv4_5_mode_strings[i]);
1284 dirty = 0;
1285 mode_change = 0;
1286 /* check if there are dirty registers in the current mode
1287 */
1288 for (j = 0; j <= 16; j++)
1289 {
1290 reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j);
1291 reg_arch_info = reg->arch_info;
1292 if (reg->dirty == 1)
1293 {
1294 if (reg->valid == 1)
1295 {
1296 dirty = 1;
1297 LOG_DEBUG("examining dirty reg: %s", reg->name);
1298 if ((reg_arch_info->mode != ARMV4_5_MODE_ANY)
1299 && (reg_arch_info->mode != current_mode)
1300 && !((reg_arch_info->mode == ARMV4_5_MODE_USR) && (armv4_5->core_mode == ARMV4_5_MODE_SYS))
1301 && !((reg_arch_info->mode == ARMV4_5_MODE_SYS) && (armv4_5->core_mode == ARMV4_5_MODE_USR)))
1302 {
1303 mode_change = 1;
1304 LOG_DEBUG("require mode change");
1305 }
1306 }
1307 else
1308 {
1309 LOG_ERROR("BUG: dirty register '%s', but no valid data", reg->name);
1310 }
1311 }
1312 }
1313
1314 if (dirty)
1315 {
1316 u32 mask = 0x0;
1317 int num_regs = 0;
1318 u32 regs[16];
1319
1320 if (mode_change)
1321 {
1322 u32 tmp_cpsr;
1323
1324 /* change processor mode (mask T bit) */
1325 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1326 tmp_cpsr |= armv4_5_number_to_mode(i);
1327 tmp_cpsr &= ~0x20;
1328 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1329 current_mode = armv4_5_number_to_mode(i);
1330 }
1331
1332 for (j = 0; j <= 14; j++)
1333 {
1334 reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j);
1335 reg_arch_info = reg->arch_info;
1336
1337
1338 if (reg->dirty == 1)
1339 {
1340 regs[j] = buf_get_u32(reg->value, 0, 32);
1341 mask |= 1 << j;
1342 num_regs++;
1343 reg->dirty = 0;
1344 reg->valid = 1;
1345 LOG_DEBUG("writing register %i of mode %s with value 0x%8.8x", j, armv4_5_mode_strings[i], regs[j]);
1346 }
1347 }
1348
1349 if (mask)
1350 {
1351 arm7_9->write_core_regs(target, mask, regs);
1352 }
1353
1354 reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16);
1355 reg_arch_info = reg->arch_info;
1356 if ((reg->dirty) && (reg_arch_info->mode != ARMV4_5_MODE_ANY))
1357 {
1358 LOG_DEBUG("writing SPSR of mode %i with value 0x%8.8x", i, buf_get_u32(reg->value, 0, 32));
1359 arm7_9->write_xpsr(target, buf_get_u32(reg->value, 0, 32), 1);
1360 }
1361 }
1362 }
1363
1364 if ((armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty == 0) && (armv4_5->core_mode != current_mode))
1365 {
1366 /* restore processor mode (mask T bit) */
1367 u32 tmp_cpsr;
1368
1369 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1370 tmp_cpsr |= armv4_5_number_to_mode(i);
1371 tmp_cpsr &= ~0x20;
1372 LOG_DEBUG("writing lower 8 bit of cpsr with value 0x%2.2x", tmp_cpsr);
1373 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1374 }
1375 else if (armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty == 1)
1376 {
1377 /* CPSR has been changed, full restore necessary (mask T bit) */
1378 LOG_DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
1379 arm7_9->write_xpsr(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32) & ~0x20, 0);
1380 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 0;
1381 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
1382 }
1383
1384 /* restore PC */
1385 LOG_DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1386 arm7_9->write_pc(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1387 armv4_5->core_cache->reg_list[15].dirty = 0;
1388
1389 if (arm7_9->post_restore_context)
1390 arm7_9->post_restore_context(target);
1391
1392 return ERROR_OK;
1393 }
1394
1395 int arm7_9_restart_core(struct target_s *target)
1396 {
1397 armv4_5_common_t *armv4_5 = target->arch_info;
1398 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1399 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
1400
1401 /* set RESTART instruction */
1402 jtag_add_end_state(TAP_RTI);
1403 if (arm7_9->need_bypass_before_restart) {
1404 arm7_9->need_bypass_before_restart = 0;
1405 arm_jtag_set_instr(jtag_info, 0xf, NULL);
1406 }
1407 arm_jtag_set_instr(jtag_info, 0x4, NULL);
1408
1409 jtag_add_runtest(1, TAP_RTI);
1410 return jtag_execute_queue();
1411 }
1412
1413 void arm7_9_enable_watchpoints(struct target_s *target)
1414 {
1415 watchpoint_t *watchpoint = target->watchpoints;
1416
1417 while (watchpoint)
1418 {
1419 if (watchpoint->set == 0)
1420 arm7_9_set_watchpoint(target, watchpoint);
1421 watchpoint = watchpoint->next;
1422 }
1423 }
1424
1425 void arm7_9_enable_breakpoints(struct target_s *target)
1426 {
1427 breakpoint_t *breakpoint = target->breakpoints;
1428
1429 /* set any pending breakpoints */
1430 while (breakpoint)
1431 {
1432 if (breakpoint->set == 0)
1433 arm7_9_set_breakpoint(target, breakpoint);
1434 breakpoint = breakpoint->next;
1435 }
1436 }
1437
1438 void arm7_9_disable_bkpts_and_wpts(struct target_s *target)
1439 {
1440 breakpoint_t *breakpoint = target->breakpoints;
1441 watchpoint_t *watchpoint = target->watchpoints;
1442
1443 /* set any pending breakpoints */
1444 while (breakpoint)
1445 {
1446 if (breakpoint->set != 0)
1447 arm7_9_unset_breakpoint(target, breakpoint);
1448 breakpoint = breakpoint->next;
1449 }
1450
1451 while (watchpoint)
1452 {
1453 if (watchpoint->set != 0)
1454 arm7_9_unset_watchpoint(target, watchpoint);
1455 watchpoint = watchpoint->next;
1456 }
1457 }
1458
1459 int arm7_9_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution)
1460 {
1461 armv4_5_common_t *armv4_5 = target->arch_info;
1462 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1463 breakpoint_t *breakpoint = target->breakpoints;
1464 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1465 int err;
1466
1467 LOG_DEBUG("-");
1468
1469 if (target->state != TARGET_HALTED)
1470 {
1471 LOG_WARNING("target not halted");
1472 return ERROR_TARGET_NOT_HALTED;
1473 }
1474
1475 if (!debug_execution)
1476 {
1477 target_free_all_working_areas(target);
1478 }
1479
1480 /* current = 1: continue on current pc, otherwise continue at <address> */
1481 if (!current)
1482 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
1483
1484 /* the front-end may request us not to handle breakpoints */
1485 if (handle_breakpoints)
1486 {
1487 if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
1488 {
1489 LOG_DEBUG("unset breakpoint at 0x%8.8x", breakpoint->address);
1490 arm7_9_unset_breakpoint(target, breakpoint);
1491
1492 LOG_DEBUG("enable single-step");
1493 arm7_9->enable_single_step(target);
1494
1495 target->debug_reason = DBG_REASON_SINGLESTEP;
1496
1497 arm7_9_restore_context(target);
1498
1499 if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1500 arm7_9->branch_resume(target);
1501 else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1502 {
1503 arm7_9->branch_resume_thumb(target);
1504 }
1505 else
1506 {
1507 LOG_ERROR("unhandled core state");
1508 return ERROR_FAIL;
1509 }
1510
1511 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
1512 embeddedice_write_reg(dbg_ctrl, buf_get_u32(dbg_ctrl->value, 0, dbg_ctrl->size));
1513 err = arm7_9_execute_sys_speed(target);
1514
1515 LOG_DEBUG("disable single-step");
1516 arm7_9->disable_single_step(target);
1517
1518 if (err != ERROR_OK)
1519 {
1520 arm7_9_set_breakpoint(target, breakpoint);
1521 target->state = TARGET_UNKNOWN;
1522 return err;
1523 }
1524
1525 arm7_9_debug_entry(target);
1526 LOG_DEBUG("new PC after step: 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1527
1528 LOG_DEBUG("set breakpoint at 0x%8.8x", breakpoint->address);
1529 arm7_9_set_breakpoint(target, breakpoint);
1530 }
1531 }
1532
1533 /* enable any pending breakpoints and watchpoints */
1534 arm7_9_enable_breakpoints(target);
1535 arm7_9_enable_watchpoints(target);
1536
1537 arm7_9_restore_context(target);
1538
1539 if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1540 {
1541 arm7_9->branch_resume(target);
1542 }
1543 else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1544 {
1545 arm7_9->branch_resume_thumb(target);
1546 }
1547 else
1548 {
1549 LOG_ERROR("unhandled core state");
1550 return ERROR_FAIL;
1551 }
1552
1553 /* deassert DBGACK and INTDIS */
1554 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
1555 /* INTDIS only when we really resume, not during debug execution */
1556 if (!debug_execution)
1557 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 0);
1558 embeddedice_write_reg(dbg_ctrl, buf_get_u32(dbg_ctrl->value, 0, dbg_ctrl->size));
1559
1560 arm7_9_restart_core(target);
1561
1562 target->debug_reason = DBG_REASON_NOTHALTED;
1563
1564 if (!debug_execution)
1565 {
1566 /* registers are now invalid */
1567 armv4_5_invalidate_core_regs(target);
1568 target->state = TARGET_RUNNING;
1569 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1570 }
1571 else
1572 {
1573 target->state = TARGET_DEBUG_RUNNING;
1574 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
1575 }
1576
1577 LOG_DEBUG("target resumed");
1578
1579 return ERROR_OK;
1580 }
1581
1582 void arm7_9_enable_eice_step(target_t *target)
1583 {
1584 armv4_5_common_t *armv4_5 = target->arch_info;
1585 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1586
1587 /* setup an inverse breakpoint on the current PC
1588 * - comparator 1 matches the current address
1589 * - rangeout from comparator 1 is connected to comparator 0 rangein
1590 * - comparator 0 matches any address, as long as rangein is low */
1591 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
1592 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
1593 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x100);
1594 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0x77);
1595 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1596 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0);
1597 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffff);
1598 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
1599 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], 0xf7);
1600 }
1601
1602 void arm7_9_disable_eice_step(target_t *target)
1603 {
1604 armv4_5_common_t *armv4_5 = target->arch_info;
1605 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1606
1607 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
1608 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);
1609 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]);
1610 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK]);
1611 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE]);
1612 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK]);
1613 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK]);
1614 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK]);
1615 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE]);
1616 }
1617
1618 int arm7_9_step(struct target_s *target, int current, u32 address, int handle_breakpoints)
1619 {
1620 armv4_5_common_t *armv4_5 = target->arch_info;
1621 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1622 breakpoint_t *breakpoint = NULL;
1623 int err;
1624
1625 if (target->state != TARGET_HALTED)
1626 {
1627 LOG_WARNING("target not halted");
1628 return ERROR_TARGET_NOT_HALTED;
1629 }
1630
1631 /* current = 1: continue on current pc, otherwise continue at <address> */
1632 if (!current)
1633 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
1634
1635 /* the front-end may request us not to handle breakpoints */
1636 if (handle_breakpoints)
1637 if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
1638 arm7_9_unset_breakpoint(target, breakpoint);
1639
1640 target->debug_reason = DBG_REASON_SINGLESTEP;
1641
1642 arm7_9_restore_context(target);
1643
1644 arm7_9->enable_single_step(target);
1645
1646 if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1647 {
1648 arm7_9->branch_resume(target);
1649 }
1650 else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1651 {
1652 arm7_9->branch_resume_thumb(target);
1653 }
1654 else
1655 {
1656 LOG_ERROR("unhandled core state");
1657 return ERROR_FAIL;
1658 }
1659
1660 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1661
1662 err = arm7_9_execute_sys_speed(target);
1663 arm7_9->disable_single_step(target);
1664
1665 /* registers are now invalid */
1666 armv4_5_invalidate_core_regs(target);
1667
1668 if (err != ERROR_OK)
1669 {
1670 target->state = TARGET_UNKNOWN;
1671 } else {
1672 arm7_9_debug_entry(target);
1673 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
1674 LOG_DEBUG("target stepped");
1675 }
1676
1677 if (breakpoint)
1678 arm7_9_set_breakpoint(target, breakpoint);
1679
1680 return err;
1681
1682 }
1683
1684 int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mode)
1685 {
1686 u32* reg_p[16];
1687 u32 value;
1688 int retval;
1689 armv4_5_common_t *armv4_5 = target->arch_info;
1690 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1691
1692 if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
1693 return ERROR_FAIL;
1694
1695 enum armv4_5_mode reg_mode = ((armv4_5_core_reg_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode;
1696
1697 if ((num < 0) || (num > 16))
1698 return ERROR_INVALID_ARGUMENTS;
1699
1700 if ((mode != ARMV4_5_MODE_ANY)
1701 && (mode != armv4_5->core_mode)
1702 && (reg_mode != ARMV4_5_MODE_ANY))
1703 {
1704 u32 tmp_cpsr;
1705
1706 /* change processor mode (mask T bit) */
1707 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1708 tmp_cpsr |= mode;
1709 tmp_cpsr &= ~0x20;
1710 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1711 }
1712
1713 if ((num >= 0) && (num <= 15))
1714 {
1715 /* read a normal core register */
1716 reg_p[num] = &value;
1717
1718 arm7_9->read_core_regs(target, 1 << num, reg_p);
1719 }
1720 else
1721 {
1722 /* read a program status register
1723 * if the register mode is MODE_ANY, we read the cpsr, otherwise a spsr
1724 */
1725 armv4_5_core_reg_t *arch_info = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info;
1726 int spsr = (arch_info->mode == ARMV4_5_MODE_ANY) ? 0 : 1;
1727
1728 arm7_9->read_xpsr(target, &value, spsr);
1729 }
1730
1731 if ((retval = jtag_execute_queue()) != ERROR_OK)
1732 {
1733 return retval;
1734 }
1735
1736 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
1737 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
1738 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).value, 0, 32, value);
1739
1740 if ((mode != ARMV4_5_MODE_ANY)
1741 && (mode != armv4_5->core_mode)
1742 && (reg_mode != ARMV4_5_MODE_ANY)) {
1743 /* restore processor mode (mask T bit) */
1744 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
1745 }
1746
1747 return ERROR_OK;
1748
1749 }
1750
1751 int arm7_9_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mode, u32 value)
1752 {
1753 u32 reg[16];
1754 armv4_5_common_t *armv4_5 = target->arch_info;
1755 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1756
1757 if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
1758 return ERROR_FAIL;
1759
1760 enum armv4_5_mode reg_mode = ((armv4_5_core_reg_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode;
1761
1762 if ((num < 0) || (num > 16))
1763 return ERROR_INVALID_ARGUMENTS;
1764
1765 if ((mode != ARMV4_5_MODE_ANY)
1766 && (mode != armv4_5->core_mode)
1767 && (reg_mode != ARMV4_5_MODE_ANY)) {
1768 u32 tmp_cpsr;
1769
1770 /* change processor mode (mask T bit) */
1771 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1772 tmp_cpsr |= mode;
1773 tmp_cpsr &= ~0x20;
1774 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1775 }
1776
1777 if ((num >= 0) && (num <= 15))
1778 {
1779 /* write a normal core register */
1780 reg[num] = value;
1781
1782 arm7_9->write_core_regs(target, 1 << num, reg);
1783 }
1784 else
1785 {
1786 /* write a program status register
1787 * if the register mode is MODE_ANY, we write the cpsr, otherwise a spsr
1788 */
1789 armv4_5_core_reg_t *arch_info = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info;
1790 int spsr = (arch_info->mode == ARMV4_5_MODE_ANY) ? 0 : 1;
1791
1792 /* if we're writing the CPSR, mask the T bit */
1793 if (!spsr)
1794 value &= ~0x20;
1795
1796 arm7_9->write_xpsr(target, value, spsr);
1797 }
1798
1799 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
1800 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
1801
1802 if ((mode != ARMV4_5_MODE_ANY)
1803 && (mode != armv4_5->core_mode)
1804 && (reg_mode != ARMV4_5_MODE_ANY)) {
1805 /* restore processor mode (mask T bit) */
1806 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
1807 }
1808
1809 return jtag_execute_queue();
1810 }
1811
1812 int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1813 {
1814 armv4_5_common_t *armv4_5 = target->arch_info;
1815 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1816
1817 u32 reg[16];
1818 int num_accesses = 0;
1819 int thisrun_accesses;
1820 int i;
1821 u32 cpsr;
1822 int retval;
1823 int last_reg = 0;
1824
1825 LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
1826
1827 if (target->state != TARGET_HALTED)
1828 {
1829 LOG_WARNING("target not halted");
1830 return ERROR_TARGET_NOT_HALTED;
1831 }
1832
1833 /* sanitize arguments */
1834 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
1835 return ERROR_INVALID_ARGUMENTS;
1836
1837 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1838 return ERROR_TARGET_UNALIGNED_ACCESS;
1839
1840 /* load the base register with the address of the first word */
1841 reg[0] = address;
1842 arm7_9->write_core_regs(target, 0x1, reg);
1843
1844 switch (size)
1845 {
1846 case 4:
1847 while (num_accesses < count)
1848 {
1849 u32 reg_list;
1850 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1851 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1852
1853 if (last_reg <= thisrun_accesses)
1854 last_reg = thisrun_accesses;
1855
1856 arm7_9->load_word_regs(target, reg_list);
1857
1858 /* fast memory reads are only safe when the target is running
1859 * from a sufficiently high clock (32 kHz is usually too slow)
1860 */
1861 if (arm7_9->fast_memory_access)
1862 arm7_9_execute_fast_sys_speed(target);
1863 else
1864 arm7_9_execute_sys_speed(target);
1865
1866 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 4);
1867
1868 /* advance buffer, count number of accesses */
1869 buffer += thisrun_accesses * 4;
1870 num_accesses += thisrun_accesses;
1871 }
1872 break;
1873 case 2:
1874 while (num_accesses < count)
1875 {
1876 u32 reg_list;
1877 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1878 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1879
1880 for (i = 1; i <= thisrun_accesses; i++)
1881 {
1882 if (i > last_reg)
1883 last_reg = i;
1884 arm7_9->load_hword_reg(target, i);
1885 /* fast memory reads are only safe when the target is running
1886 * from a sufficiently high clock (32 kHz is usually too slow)
1887 */
1888 if (arm7_9->fast_memory_access)
1889 arm7_9_execute_fast_sys_speed(target);
1890 else
1891 arm7_9_execute_sys_speed(target);
1892 }
1893
1894 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 2);
1895
1896 /* advance buffer, count number of accesses */
1897 buffer += thisrun_accesses * 2;
1898 num_accesses += thisrun_accesses;
1899 }
1900 break;
1901 case 1:
1902 while (num_accesses < count)
1903 {
1904 u32 reg_list;
1905 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1906 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1907
1908 for (i = 1; i <= thisrun_accesses; i++)
1909 {
1910 if (i > last_reg)
1911 last_reg = i;
1912 arm7_9->load_byte_reg(target, i);
1913 /* fast memory reads are only safe when the target is running
1914 * from a sufficiently high clock (32 kHz is usually too slow)
1915 */
1916 if (arm7_9->fast_memory_access)
1917 arm7_9_execute_fast_sys_speed(target);
1918 else
1919 arm7_9_execute_sys_speed(target);
1920 }
1921
1922 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 1);
1923
1924 /* advance buffer, count number of accesses */
1925 buffer += thisrun_accesses * 1;
1926 num_accesses += thisrun_accesses;
1927 }
1928 break;
1929 default:
1930 LOG_ERROR("BUG: we shouldn't get here");
1931 exit(-1);
1932 break;
1933 }
1934
1935 if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
1936 return ERROR_FAIL;
1937
1938 for (i=0; i<=last_reg; i++)
1939 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid;
1940
1941 arm7_9->read_xpsr(target, &cpsr, 0);
1942 if ((retval = jtag_execute_queue()) != ERROR_OK)
1943 {
1944 LOG_ERROR("JTAG error while reading cpsr");
1945 return ERROR_TARGET_DATA_ABORT;
1946 }
1947
1948 if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))
1949 {
1950 LOG_WARNING("memory read caused data abort (address: 0x%8.8x, size: 0x%x, count: 0x%x)", address, size, count);
1951
1952 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
1953
1954 return ERROR_TARGET_DATA_ABORT;
1955 }
1956
1957 return ERROR_OK;
1958 }
1959
1960 int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1961 {
1962 armv4_5_common_t *armv4_5 = target->arch_info;
1963 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1964 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1965
1966 u32 reg[16];
1967 int num_accesses = 0;
1968 int thisrun_accesses;
1969 int i;
1970 u32 cpsr;
1971 int retval;
1972 int last_reg = 0;
1973
1974 #ifdef _DEBUG_ARM7_9_
1975 LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
1976 #endif
1977
1978 if (target->state != TARGET_HALTED)
1979 {
1980 LOG_WARNING("target not halted");
1981 return ERROR_TARGET_NOT_HALTED;
1982 }
1983
1984 /* sanitize arguments */
1985 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
1986 return ERROR_INVALID_ARGUMENTS;
1987
1988 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1989 return ERROR_TARGET_UNALIGNED_ACCESS;
1990
1991 /* load the base register with the address of the first word */
1992 reg[0] = address;
1993 arm7_9->write_core_regs(target, 0x1, reg);
1994
1995 /* Clear DBGACK, to make sure memory fetches work as expected */
1996 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
1997 embeddedice_store_reg(dbg_ctrl);
1998
1999 switch (size)
2000 {
2001 case 4:
2002 while (num_accesses < count)
2003 {
2004 u32 reg_list;
2005 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
2006 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2007
2008 for (i = 1; i <= thisrun_accesses; i++)
2009 {
2010 if (i > last_reg)
2011 last_reg = i;
2012 reg[i] = target_buffer_get_u32(target, buffer);
2013 buffer += 4;
2014 }
2015
2016 arm7_9->write_core_regs(target, reg_list, reg);
2017
2018 arm7_9->store_word_regs(target, reg_list);
2019
2020 /* fast memory writes are only safe when the target is running
2021 * from a sufficiently high clock (32 kHz is usually too slow)
2022 */
2023 if (arm7_9->fast_memory_access)
2024 arm7_9_execute_fast_sys_speed(target);
2025 else
2026 arm7_9_execute_sys_speed(target);
2027
2028 num_accesses += thisrun_accesses;
2029 }
2030 break;
2031 case 2:
2032 while (num_accesses < count)
2033 {
2034 u32 reg_list;
2035 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
2036 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2037
2038 for (i = 1; i <= thisrun_accesses; i++)
2039 {
2040 if (i > last_reg)
2041 last_reg = i;
2042 reg[i] = target_buffer_get_u16(target, buffer) & 0xffff;
2043 buffer += 2;
2044 }
2045
2046 arm7_9->write_core_regs(target, reg_list, reg);
2047
2048 for (i = 1; i <= thisrun_accesses; i++)
2049 {
2050 arm7_9->store_hword_reg(target, i);
2051
2052 /* fast memory writes are only safe when the target is running
2053 * from a sufficiently high clock (32 kHz is usually too slow)
2054 */
2055 if (arm7_9->fast_memory_access)
2056 arm7_9_execute_fast_sys_speed(target);
2057 else
2058 arm7_9_execute_sys_speed(target);
2059 }
2060
2061 num_accesses += thisrun_accesses;
2062 }
2063 break;
2064 case 1:
2065 while (num_accesses < count)
2066 {
2067 u32 reg_list;
2068 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
2069 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2070
2071 for (i = 1; i <= thisrun_accesses; i++)
2072 {
2073 if (i > last_reg)
2074 last_reg = i;
2075 reg[i] = *buffer++ & 0xff;
2076 }
2077
2078 arm7_9->write_core_regs(target, reg_list, reg);
2079
2080 for (i = 1; i <= thisrun_accesses; i++)
2081 {
2082 arm7_9->store_byte_reg(target, i);
2083 /* fast memory writes are only safe when the target is running
2084 * from a sufficiently high clock (32 kHz is usually too slow)
2085 */
2086 if (arm7_9->fast_memory_access)
2087 arm7_9_execute_fast_sys_speed(target);
2088 else
2089 arm7_9_execute_sys_speed(target);
2090 }
2091
2092 num_accesses += thisrun_accesses;
2093 }
2094 break;
2095 default:
2096 LOG_ERROR("BUG: we shouldn't get here");
2097 exit(-1);
2098 break;
2099 }
2100
2101 /* Re-Set DBGACK */
2102 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
2103 embeddedice_store_reg(dbg_ctrl);
2104
2105 if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
2106 return ERROR_FAIL;
2107
2108 for (i=0; i<=last_reg; i++)
2109 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid;
2110
2111 arm7_9->read_xpsr(target, &cpsr, 0);
2112 if ((retval = jtag_execute_queue()) != ERROR_OK)
2113 {
2114 LOG_ERROR("JTAG error while reading cpsr");
2115 return ERROR_TARGET_DATA_ABORT;
2116 }
2117
2118 if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))
2119 {
2120 LOG_WARNING("memory write caused data abort (address: 0x%8.8x, size: 0x%x, count: 0x%x)", address, size, count);
2121
2122 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
2123
2124 return ERROR_TARGET_DATA_ABORT;
2125 }
2126
2127 return ERROR_OK;
2128 }
2129
2130 static const u32 dcc_code[] =
2131 {
2132 /* MRC TST BNE MRC STR B */
2133 0xee101e10, 0xe3110001, 0x0afffffc, 0xee111e10, 0xe4801004, 0xeafffff9
2134 };
2135
2136 int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer)
2137 {
2138 armv4_5_common_t *armv4_5 = target->arch_info;
2139 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
2140 enum armv4_5_state core_state = armv4_5->core_state;
2141 u32 r0 = buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32);
2142 u32 r1 = buf_get_u32(armv4_5->core_cache->reg_list[1].value, 0, 32);
2143 u32 pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
2144 int i;
2145
2146 if (!arm7_9->dcc_downloads)
2147 return target->type->write_memory(target, address, 4, count, buffer);
2148
2149 /* regrab previously allocated working_area, or allocate a new one */
2150 if (!arm7_9->dcc_working_area)
2151 {
2152 u8 dcc_code_buf[6 * 4];
2153
2154 /* make sure we have a working area */
2155 if (target_alloc_working_area(target, 24, &arm7_9->dcc_working_area) != ERROR_OK)
2156 {
2157 LOG_INFO("no working area available, falling back to memory writes");
2158 return target->type->write_memory(target, address, 4, count, buffer);
2159 }
2160
2161 /* copy target instructions to target endianness */
2162 for (i = 0; i < 6; i++)
2163 {
2164 target_buffer_set_u32(target, dcc_code_buf + i*4, dcc_code[i]);
2165 }
2166
2167 /* write DCC code to working area */
2168 target->type->write_memory(target, arm7_9->dcc_working_area->address, 4, 6, dcc_code_buf);
2169 }
2170
2171 buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, address);
2172 armv4_5->core_cache->reg_list[0].valid = 1;
2173 armv4_5->core_cache->reg_list[0].dirty = 1;
2174 armv4_5->core_state = ARMV4_5_STATE_ARM;
2175
2176 arm7_9_resume(target, 0, arm7_9->dcc_working_area->address, 1, 1);
2177
2178 int little=target->endianness==TARGET_LITTLE_ENDIAN;
2179 if (count>2)
2180 {
2181 /* Handle first & last using standard embeddedice_write_reg and the middle ones w/the
2182 core function repeated.
2183 */
2184 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
2185 buffer+=4;
2186
2187 embeddedice_reg_t *ice_reg = arm7_9->eice_cache->reg_list[EICE_COMMS_DATA].arch_info;
2188 u8 reg_addr = ice_reg->addr & 0x1f;
2189 int chain_pos = ice_reg->jtag_info->chain_pos;
2190 /* we want the compiler to duplicate the code, which it does not
2191 * do automatically.
2192 */
2193 if (little)
2194 {
2195 for (i = 1; i < count - 1; i++)
2196 {
2197 embeddedice_write_reg_inner(chain_pos, reg_addr, fast_target_buffer_get_u32(buffer, little));
2198 buffer += 4;
2199 }
2200 } else
2201 {
2202 for (i = 1; i < count - 1; i++)
2203 {
2204 embeddedice_write_reg_inner(chain_pos, reg_addr, fast_target_buffer_get_u32(buffer, little));
2205 buffer += 4;
2206 }
2207 }
2208 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
2209 } else
2210 {
2211 for (i = 0; i < count; i++)
2212 {
2213 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
2214 buffer += 4;
2215 }
2216 }
2217
2218 target_halt(target);
2219
2220 for (i=0; i<100; i++)
2221 {
2222 target_poll(target);
2223 if (target->state == TARGET_HALTED)
2224 break;
2225 usleep(1000); /* sleep 1ms */
2226 }
2227 if (i == 100)
2228 {
2229 LOG_ERROR("bulk write timed out, target not halted");
2230 return ERROR_TARGET_TIMEOUT;
2231 }
2232
2233 /* restore target state */
2234 buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, r0);
2235 armv4_5->core_cache->reg_list[0].valid = 1;
2236 armv4_5->core_cache->reg_list[0].dirty = 1;
2237 buf_set_u32(armv4_5->core_cache->reg_list[1].value, 0, 32, r1);
2238 armv4_5->core_cache->reg_list[1].valid = 1;
2239 armv4_5->core_cache->reg_list[1].dirty = 1;
2240 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, pc);
2241 armv4_5->core_cache->reg_list[15].valid = 1;
2242 armv4_5->core_cache->reg_list[15].dirty = 1;
2243 armv4_5->core_state = core_state;
2244
2245 return ERROR_OK;
2246 }
2247
2248 int arm7_9_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum)
2249 {
2250 working_area_t *crc_algorithm;
2251 armv4_5_algorithm_t armv4_5_info;
2252 reg_param_t reg_params[2];
2253 int retval;
2254
2255 u32 arm7_9_crc_code[] = {
2256 0xE1A02000, /* mov r2, r0 */
2257 0xE3E00000, /* mov r0, #0xffffffff */
2258 0xE1A03001, /* mov r3, r1 */
2259 0xE3A04000, /* mov r4, #0 */
2260 0xEA00000B, /* b ncomp */
2261 /* nbyte: */
2262 0xE7D21004, /* ldrb r1, [r2, r4] */
2263 0xE59F7030, /* ldr r7, CRC32XOR */
2264 0xE0200C01, /* eor r0, r0, r1, asl 24 */
2265 0xE3A05000, /* mov r5, #0 */
2266 /* loop: */
2267 0xE3500000, /* cmp r0, #0 */
2268 0xE1A06080, /* mov r6, r0, asl #1 */
2269 0xE2855001, /* add r5, r5, #1 */
2270 0xE1A00006, /* mov r0, r6 */
2271 0xB0260007, /* eorlt r0, r6, r7 */
2272 0xE3550008, /* cmp r5, #8 */
2273 0x1AFFFFF8, /* bne loop */
2274 0xE2844001, /* add r4, r4, #1 */
2275 /* ncomp: */
2276 0xE1540003, /* cmp r4, r3 */
2277 0x1AFFFFF1, /* bne nbyte */
2278 /* end: */
2279 0xEAFFFFFE, /* b end */
2280 0x04C11DB7 /* CRC32XOR: .word 0x04C11DB7 */
2281 };
2282
2283 int i;
2284
2285 if (target_alloc_working_area(target, sizeof(arm7_9_crc_code), &crc_algorithm) != ERROR_OK)
2286 {
2287 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
2288 }
2289
2290 /* convert flash writing code into a buffer in target endianness */
2291 for (i = 0; i < (sizeof(arm7_9_crc_code)/sizeof(u32)); i++)
2292 target_write_u32(target, crc_algorithm->address + i*sizeof(u32), arm7_9_crc_code[i]);
2293
2294 armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
2295 armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
2296 armv4_5_info.core_state = ARMV4_5_STATE_ARM;
2297
2298 init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT);
2299 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
2300
2301 buf_set_u32(reg_params[0].value, 0, 32, address);
2302 buf_set_u32(reg_params[1].value, 0, 32, count);
2303
2304 if ((retval = target->type->run_algorithm(target, 0, NULL, 2, reg_params,
2305 crc_algorithm->address, crc_algorithm->address + (sizeof(arm7_9_crc_code) - 8), 20000, &armv4_5_info)) != ERROR_OK)
2306 {
2307 LOG_ERROR("error executing arm7_9 crc algorithm");
2308 destroy_reg_param(&reg_params[0]);
2309 destroy_reg_param(&reg_params[1]);
2310 target_free_working_area(target, crc_algorithm);
2311 return retval;
2312 }
2313
2314 *checksum = buf_get_u32(reg_params[0].value, 0, 32);
2315
2316 destroy_reg_param(&reg_params[0]);
2317 destroy_reg_param(&reg_params[1]);
2318
2319 target_free_working_area(target, crc_algorithm);
2320
2321 return ERROR_OK;
2322 }
2323
2324 int arm7_9_blank_check_memory(struct target_s *target, u32 address, u32 count, u32* blank)
2325 {
2326 working_area_t *erase_check_algorithm;
2327 reg_param_t reg_params[3];
2328 armv4_5_algorithm_t armv4_5_info;
2329 int retval;
2330 int i;
2331
2332 u32 erase_check_code[] =
2333 {
2334 /* loop: */
2335 0xe4d03001, /* ldrb r3, [r0], #1 */
2336 0xe0022003, /* and r2, r2, r3 */
2337 0xe2511001, /* subs r1, r1, #1 */
2338 0x1afffffb, /* bne loop */
2339 /* end: */
2340 0xeafffffe /* b end */
2341 };
2342
2343 /* make sure we have a working area */
2344 if (target_alloc_working_area(target, sizeof(erase_check_code), &erase_check_algorithm) != ERROR_OK)
2345 {
2346 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
2347 }
2348
2349 /* convert flash writing code into a buffer in target endianness */
2350 for (i = 0; i < (sizeof(erase_check_code)/sizeof(u32)); i++)
2351 target_write_u32(target, erase_check_algorithm->address + i*sizeof(u32), erase_check_code[i]);
2352
2353 armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
2354 armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
2355 armv4_5_info.core_state = ARMV4_5_STATE_ARM;
2356
2357 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
2358 buf_set_u32(reg_params[0].value, 0, 32, address);
2359
2360 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
2361 buf_set_u32(reg_params[1].value, 0, 32, count);
2362
2363 init_reg_param(&reg_params[2], "r2", 32, PARAM_IN_OUT);
2364 buf_set_u32(reg_params[2].value, 0, 32, 0xff);
2365
2366 if ((retval = target->type->run_algorithm(target, 0, NULL, 3, reg_params,
2367 erase_check_algorithm->address, erase_check_algorithm->address + (sizeof(erase_check_code) - 4), 10000, &armv4_5_info)) != ERROR_OK)
2368 {
2369 destroy_reg_param(&reg_params[0]);
2370 destroy_reg_param(&reg_params[1]);
2371 destroy_reg_param(&reg_params[2]);
2372 target_free_working_area(target, erase_check_algorithm);
2373 return 0;
2374 }
2375
2376 *blank = buf_get_u32(reg_params[2].value, 0, 32);
2377
2378 destroy_reg_param(&reg_params[0]);
2379 destroy_reg_param(&reg_params[1]);
2380 destroy_reg_param(&reg_params[2]);
2381
2382 target_free_working_area(target, erase_check_algorithm);
2383
2384 return ERROR_OK;
2385 }
2386
2387 int arm7_9_register_commands(struct command_context_s *cmd_ctx)
2388 {
2389 command_t *arm7_9_cmd;
2390
2391 arm7_9_cmd = register_command(cmd_ctx, NULL, "arm7_9", NULL, COMMAND_ANY, "arm7/9 specific commands");
2392
2393 register_command(cmd_ctx, arm7_9_cmd, "write_xpsr", handle_arm7_9_write_xpsr_command, COMMAND_EXEC, "write program status register <value> <not cpsr|spsr>");
2394 register_command(cmd_ctx, arm7_9_cmd, "write_xpsr_im8", handle_arm7_9_write_xpsr_im8_command, COMMAND_EXEC, "write program status register <8bit immediate> <rotate> <not cpsr|spsr>");
2395
2396 register_command(cmd_ctx, arm7_9_cmd, "write_core_reg", handle_arm7_9_write_core_reg_command, COMMAND_EXEC, "write core register <num> <mode> <value>");
2397
2398 register_command(cmd_ctx, arm7_9_cmd, "sw_bkpts", handle_arm7_9_sw_bkpts_command, COMMAND_EXEC, "support for software breakpoints <enable|disable>");
2399 register_command(cmd_ctx, arm7_9_cmd, "force_hw_bkpts", handle_arm7_9_force_hw_bkpts_command, COMMAND_EXEC, "use hardware breakpoints for all breakpoints (disables sw breakpoint support) <enable|disable>");
2400 register_command(cmd_ctx, arm7_9_cmd, "dbgrq", handle_arm7_9_dbgrq_command,
2401 COMMAND_ANY, "use EmbeddedICE dbgrq instead of breakpoint for target halt requests <enable|disable>");
2402 register_command(cmd_ctx, arm7_9_cmd, "fast_writes", handle_arm7_9_fast_memory_access_command,
2403 COMMAND_ANY, "(deprecated, see: arm7_9 fast_memory_access)");
2404 register_command(cmd_ctx, arm7_9_cmd, "fast_memory_access", handle_arm7_9_fast_memory_access_command,
2405 COMMAND_ANY, "use fast memory accesses instead of slower but potentially unsafe slow accesses <enable|disable>");
2406 register_command(cmd_ctx, arm7_9_cmd, "dcc_downloads", handle_arm7_9_dcc_downloads_command,
2407 COMMAND_ANY, "use DCC downloads for larger memory writes <enable|disable>");
2408
2409 armv4_5_register_commands(cmd_ctx);
2410
2411 etm_register_commands(cmd_ctx);
2412
2413 return ERROR_OK;
2414 }
2415
2416 int handle_arm7_9_write_xpsr_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2417 {
2418 u32 value;
2419 int spsr;
2420 int retval;
2421 target_t *target = get_current_target(cmd_ctx);
2422 armv4_5_common_t *armv4_5;
2423 arm7_9_common_t *arm7_9;
2424
2425 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2426 {
2427 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2428 return ERROR_OK;
2429 }
2430
2431 if (target->state != TARGET_HALTED)
2432 {
2433 command_print(cmd_ctx, "can't write registers while running");
2434 return ERROR_OK;
2435 }
2436
2437 if (argc < 2)
2438 {
2439 command_print(cmd_ctx, "usage: write_xpsr <value> <not cpsr|spsr>");
2440 return ERROR_OK;
2441 }
2442
2443 value = strtoul(args[0], NULL, 0);
2444 spsr = strtol(args[1], NULL, 0);
2445
2446 /* if we're writing the CPSR, mask the T bit */
2447 if (!spsr)
2448 value &= ~0x20;
2449
2450 arm7_9->write_xpsr(target, value, spsr);
2451 if ((retval = jtag_execute_queue()) != ERROR_OK)
2452 {
2453 LOG_ERROR("JTAG error while writing to xpsr");
2454 return retval;
2455 }
2456
2457 return ERROR_OK;
2458 }
2459
2460 int handle_arm7_9_write_xpsr_im8_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2461 {
2462 u32 value;
2463 int rotate;
2464 int spsr;
2465 int retval;
2466 target_t *target = get_current_target(cmd_ctx);
2467 armv4_5_common_t *armv4_5;
2468 arm7_9_common_t *arm7_9;
2469
2470 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2471 {
2472 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2473 return ERROR_OK;
2474 }
2475
2476 if (target->state != TARGET_HALTED)
2477 {
2478 command_print(cmd_ctx, "can't write registers while running");
2479 return ERROR_OK;
2480 }
2481
2482 if (argc < 3)
2483 {
2484 command_print(cmd_ctx, "usage: write_xpsr_im8 <im8> <rotate> <not cpsr|spsr>");
2485 return ERROR_OK;
2486 }
2487
2488 value = strtoul(args[0], NULL, 0);
2489 rotate = strtol(args[1], NULL, 0);
2490 spsr = strtol(args[2], NULL, 0);
2491
2492 arm7_9->write_xpsr_im8(target, value, rotate, spsr);
2493 if ((retval = jtag_execute_queue()) != ERROR_OK)
2494 {
2495 LOG_ERROR("JTAG error while writing 8-bit immediate to xpsr");
2496 return retval;
2497 }
2498
2499 return ERROR_OK;
2500 }
2501
2502 int handle_arm7_9_write_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2503 {
2504 u32 value;
2505 u32 mode;
2506 int num;
2507 target_t *target = get_current_target(cmd_ctx);
2508 armv4_5_common_t *armv4_5;
2509 arm7_9_common_t *arm7_9;
2510
2511 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2512 {
2513 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2514 return ERROR_OK;
2515 }
2516
2517 if (target->state != TARGET_HALTED)
2518 {
2519 command_print(cmd_ctx, "can't write registers while running");
2520 return ERROR_OK;
2521 }
2522
2523 if (argc < 3)
2524 {
2525 command_print(cmd_ctx, "usage: write_core_reg <num> <mode> <value>");
2526 return ERROR_OK;
2527 }
2528
2529 num = strtol(args[0], NULL, 0);
2530 mode = strtoul(args[1], NULL, 0);
2531 value = strtoul(args[2], NULL, 0);
2532
2533 arm7_9_write_core_reg(target, num, mode, value);
2534
2535 return ERROR_OK;
2536 }
2537
2538 int handle_arm7_9_sw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2539 {
2540 target_t *target = get_current_target(cmd_ctx);
2541 armv4_5_common_t *armv4_5;
2542 arm7_9_common_t *arm7_9;
2543
2544 if (target->state != TARGET_HALTED)
2545 {
2546 LOG_ERROR("target not halted");
2547 return ERROR_TARGET_NOT_HALTED;
2548 }
2549
2550 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2551 {
2552 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2553 return ERROR_OK;
2554 }
2555
2556 if (argc == 0)
2557 {
2558 command_print(cmd_ctx, "software breakpoints %s", (arm7_9->sw_bkpts_enabled) ? "enabled" : "disabled");
2559 return ERROR_OK;
2560 }
2561
2562 if (strcmp("enable", args[0]) == 0)
2563 {
2564 if (arm7_9->sw_bkpts_use_wp)
2565 {
2566 arm7_9_enable_sw_bkpts(target);
2567 }
2568 else
2569 {
2570 arm7_9->sw_bkpts_enabled = 1;
2571 }
2572 }
2573 else if (strcmp("disable", args[0]) == 0)
2574 {
2575 if (arm7_9->sw_bkpts_use_wp)
2576 {
2577 arm7_9_disable_sw_bkpts(target);
2578 }
2579 else
2580 {
2581 arm7_9->sw_bkpts_enabled = 0;
2582 }
2583 }
2584 else
2585 {
2586 command_print(cmd_ctx, "usage: arm7_9 sw_bkpts <enable|disable>");
2587 }
2588
2589 command_print(cmd_ctx, "software breakpoints %s", (arm7_9->sw_bkpts_enabled) ? "enabled" : "disabled");
2590
2591 return ERROR_OK;
2592 }
2593
2594 int handle_arm7_9_force_hw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2595 {
2596 target_t *target = get_current_target(cmd_ctx);
2597 armv4_5_common_t *armv4_5;
2598 arm7_9_common_t *arm7_9;
2599
2600 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2601 {
2602 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2603 return ERROR_OK;
2604 }
2605
2606 if ((argc >= 1) && (strcmp("enable", args[0]) == 0))
2607 {
2608 arm7_9->force_hw_bkpts = 1;
2609 if (arm7_9->sw_bkpts_use_wp)
2610 {
2611 arm7_9_disable_sw_bkpts(target);
2612 }
2613 }
2614 else if ((argc >= 1) && (strcmp("disable", args[0]) == 0))
2615 {
2616 arm7_9->force_hw_bkpts = 0;
2617 }
2618 else
2619 {
2620 command_print(cmd_ctx, "usage: arm7_9 force_hw_bkpts <enable|disable>");
2621 }
2622
2623 command_print(cmd_ctx, "force hardware breakpoints %s", (arm7_9->force_hw_bkpts) ? "enabled" : "disabled");
2624
2625 return ERROR_OK;
2626 }
2627
2628 int handle_arm7_9_dbgrq_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2629 {
2630 target_t *target = get_current_target(cmd_ctx);
2631 armv4_5_common_t *armv4_5;
2632 arm7_9_common_t *arm7_9;
2633
2634 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2635 {
2636 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2637 return ERROR_OK;
2638 }
2639
2640 if (argc > 0)
2641 {
2642 if (strcmp("enable", args[0]) == 0)
2643 {
2644 arm7_9->use_dbgrq = 1;
2645 }
2646 else if (strcmp("disable", args[0]) == 0)
2647 {
2648 arm7_9->use_dbgrq = 0;
2649 }
2650 else
2651 {
2652 command_print(cmd_ctx, "usage: arm7_9 dbgrq <enable|disable>");
2653 }
2654 }
2655
2656 command_print(cmd_ctx, "use of EmbeddedICE dbgrq instead of breakpoint for target halt %s", (arm7_9->use_dbgrq) ? "enabled" : "disabled");
2657
2658 return ERROR_OK;
2659 }
2660
2661 int handle_arm7_9_fast_memory_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2662 {
2663 target_t *target = get_current_target(cmd_ctx);
2664 armv4_5_common_t *armv4_5;
2665 arm7_9_common_t *arm7_9;
2666
2667 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2668 {
2669 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2670 return ERROR_OK;
2671 }
2672
2673 if (argc > 0)
2674 {
2675 if (strcmp("enable", args[0]) == 0)
2676 {
2677 arm7_9->fast_memory_access = 1;
2678 }
2679 else if (strcmp("disable", args[0]) == 0)
2680 {
2681 arm7_9->fast_memory_access = 0;
2682 }
2683 else
2684 {
2685 command_print(cmd_ctx, "usage: arm7_9 fast_memory_access <enable|disable>");
2686 }
2687 }
2688
2689 command_print(cmd_ctx, "fast memory access is %s", (arm7_9->fast_memory_access) ? "enabled" : "disabled");
2690
2691 return ERROR_OK;
2692 }
2693
2694 int handle_arm7_9_dcc_downloads_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2695 {
2696 target_t *target = get_current_target(cmd_ctx);
2697 armv4_5_common_t *armv4_5;
2698 arm7_9_common_t *arm7_9;
2699
2700 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2701 {
2702 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2703 return ERROR_OK;
2704 }
2705
2706 if (argc > 0)
2707 {
2708 if (strcmp("enable", args[0]) == 0)
2709 {
2710 arm7_9->dcc_downloads = 1;
2711 }
2712 else if (strcmp("disable", args[0]) == 0)
2713 {
2714 arm7_9->dcc_downloads = 0;
2715 }
2716 else
2717 {
2718 command_print(cmd_ctx, "usage: arm7_9 dcc_downloads <enable|disable>");
2719 }
2720 }
2721
2722 command_print(cmd_ctx, "dcc downloads are %s", (arm7_9->dcc_downloads) ? "enabled" : "disabled");
2723
2724 return ERROR_OK;
2725 }
2726
2727 int arm7_9_init_arch_info(target_t *target, arm7_9_common_t *arm7_9)
2728 {
2729 armv4_5_common_t *armv4_5 = &arm7_9->armv4_5_common;
2730
2731 arm7_9->common_magic = ARM7_9_COMMON_MAGIC;
2732
2733 arm_jtag_setup_connection(&arm7_9->jtag_info);
2734 arm7_9->wp_available = 2;
2735 arm7_9->wp0_used = 0;
2736 arm7_9->wp1_used = 0;
2737 arm7_9->force_hw_bkpts = 0;
2738 arm7_9->use_dbgrq = 0;
2739
2740 arm7_9->etm_ctx = NULL;
2741 arm7_9->has_single_step = 0;
2742 arm7_9->has_monitor_mode = 0;
2743 arm7_9->has_vector_catch = 0;
2744
2745 arm7_9->debug_entry_from_reset = 0;
2746
2747 arm7_9->dcc_working_area = NULL;
2748
2749 arm7_9->fast_memory_access = fast_and_dangerous;
2750 arm7_9->dcc_downloads = fast_and_dangerous;
2751
2752 arm7_9->need_bypass_before_restart = 0;
2753
2754 armv4_5->arch_info = arm7_9;
2755 armv4_5->read_core_reg = arm7_9_read_core_reg;
2756 armv4_5->write_core_reg = arm7_9_write_core_reg;
2757 armv4_5->full_context = arm7_9_full_context;
2758
2759 armv4_5_init_arch_info(target, armv4_5);
2760
2761 target_register_timer_callback(arm7_9_handle_target_request, 1, 1, target);
2762
2763 return ERROR_OK;
2764 }
Open On-Chip Debugger

Linking to existing account procedure

If you already have an account and want to add another login method you MUST first sign in with your existing account and then change URL to read https://review.openocd.org/login/?link to get to this page again but this time it'll work for linking. Thank you.

SSH host keys fingerprints

1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=..              |
|+o..   .         |
|*.o   . .        |
|+B . . .         |
|Bo. = o S        |
|Oo.+ + =         |
|oB=.* = . o      |
| =+=.+   + E     |
|. .=o   . o      |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)