ARM: simplify CPSR handling
[openocd.git] / src / target / arm7_9_common.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2007,2008 √ėyvind Harboe *
6 * oyvind.harboe@zylin.com *
7 * *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
10 * *
11 * Copyright (C) 2008 by Hongtao Zheng *
12 * hontor@126.com *
13 * *
14 * This program is free software; you can redistribute it and/or modify *
15 * it under the terms of the GNU General Public License as published by *
16 * the Free Software Foundation; either version 2 of the License, or *
17 * (at your option) any later version. *
18 * *
19 * This program is distributed in the hope that it will be useful, *
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
22 * GNU General Public License for more details. *
23 * *
24 * You should have received a copy of the GNU General Public License *
25 * along with this program; if not, write to the *
26 * Free Software Foundation, Inc., *
27 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
28 ***************************************************************************/
29 #ifdef HAVE_CONFIG_H
30 #include "config.h"
31 #endif
32
33 #include "breakpoints.h"
34 #include "embeddedice.h"
35 #include "target_request.h"
36 #include "etm.h"
37 #include "time_support.h"
38 #include "arm_simulator.h"
39 #include "algorithm.h"
40 #include "register.h"
41
42
43 /**
44 * @file
45 * Hold common code supporting the ARM7 and ARM9 core generations.
46 *
47 * While the ARM core implementations evolved substantially during these
48 * two generations, they look quite similar from the JTAG perspective.
49 * Both have similar debug facilities, based on the same two scan chains
50 * providing access to the core and to an EmbeddedICE module. Both can
51 * support similar ETM and ETB modules, for tracing. And both expose
52 * what could be viewed as "ARM Classic", with multiple processor modes,
53 * shadowed registers, and support for the Thumb instruction set.
54 *
55 * Processor differences include things like presence or absence of MMU
56 * and cache, pipeline sizes, use of a modified Harvard Architecure
57 * (with separate instruction and data busses from the CPU), support
58 * for cpu clock gating during idle, and more.
59 */
60
61 static int arm7_9_debug_entry(struct target *target);
62
63 /**
64 * Clear watchpoints for an ARM7/9 target.
65 *
66 * @param arm7_9 Pointer to the common struct for an ARM7/9 target
67 * @return JTAG error status after executing queue
68 */
69 static int arm7_9_clear_watchpoints(struct arm7_9_common *arm7_9)
70 {
71 LOG_DEBUG("-");
72 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
73 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
74 arm7_9->sw_breakpoint_count = 0;
75 arm7_9->sw_breakpoints_added = 0;
76 arm7_9->wp0_used = 0;
77 arm7_9->wp1_used = arm7_9->wp1_used_default;
78 arm7_9->wp_available = arm7_9->wp_available_max;
79
80 return jtag_execute_queue();
81 }
82
83 /**
84 * Assign a watchpoint to one of the two available hardware comparators in an
85 * ARM7 or ARM9 target.
86 *
87 * @param arm7_9 Pointer to the common struct for an ARM7/9 target
88 * @param breakpoint Pointer to the breakpoint to be used as a watchpoint
89 */
90 static void arm7_9_assign_wp(struct arm7_9_common *arm7_9, struct breakpoint *breakpoint)
91 {
92 if (!arm7_9->wp0_used)
93 {
94 arm7_9->wp0_used = 1;
95 breakpoint->set = 1;
96 arm7_9->wp_available--;
97 }
98 else if (!arm7_9->wp1_used)
99 {
100 arm7_9->wp1_used = 1;
101 breakpoint->set = 2;
102 arm7_9->wp_available--;
103 }
104 else
105 {
106 LOG_ERROR("BUG: no hardware comparator available");
107 }
108 LOG_DEBUG("BPID: %d (0x%08" PRIx32 ") using hw wp: %d",
109 breakpoint->unique_id,
110 breakpoint->address,
111 breakpoint->set );
112 }
113
114 /**
115 * Setup an ARM7/9 target's embedded ICE registers for software breakpoints.
116 *
117 * @param arm7_9 Pointer to common struct for ARM7/9 targets
118 * @return Error codes if there is a problem finding a watchpoint or the result
119 * of executing the JTAG queue
120 */
121 static int arm7_9_set_software_breakpoints(struct arm7_9_common *arm7_9)
122 {
123 if (arm7_9->sw_breakpoints_added)
124 {
125 return ERROR_OK;
126 }
127 if (arm7_9->wp_available < 1)
128 {
129 LOG_WARNING("can't enable sw breakpoints with no watchpoint unit available");
130 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
131 }
132 arm7_9->wp_available--;
133
134 /* pick a breakpoint unit */
135 if (!arm7_9->wp0_used)
136 {
137 arm7_9->sw_breakpoints_added = 1;
138 arm7_9->wp0_used = 3;
139 } else if (!arm7_9->wp1_used)
140 {
141 arm7_9->sw_breakpoints_added = 2;
142 arm7_9->wp1_used = 3;
143 }
144 else
145 {
146 LOG_ERROR("BUG: both watchpoints used, but wp_available >= 1");
147 return ERROR_FAIL;
148 }
149
150 if (arm7_9->sw_breakpoints_added == 1)
151 {
152 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], arm7_9->arm_bkpt);
153 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0x0);
154 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffffu);
155 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
156 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
157 }
158 else if (arm7_9->sw_breakpoints_added == 2)
159 {
160 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], arm7_9->arm_bkpt);
161 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0x0);
162 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0xffffffffu);
163 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
164 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
165 }
166 else
167 {
168 LOG_ERROR("BUG: both watchpoints used, but wp_available >= 1");
169 return ERROR_FAIL;
170 }
171 LOG_DEBUG("SW BP using hw wp: %d",
172 arm7_9->sw_breakpoints_added );
173
174 return jtag_execute_queue();
175 }
176
177 /**
178 * Setup the common pieces for an ARM7/9 target after reset or on startup.
179 *
180 * @param target Pointer to an ARM7/9 target to setup
181 * @return Result of clearing the watchpoints on the target
182 */
183 int arm7_9_setup(struct target *target)
184 {
185 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
186
187 return arm7_9_clear_watchpoints(arm7_9);
188 }
189
190 /**
191 * Set either a hardware or software breakpoint on an ARM7/9 target. The
192 * breakpoint is set up even if it is already set. Some actions, e.g. reset,
193 * might have erased the values in Embedded ICE.
194 *
195 * @param target Pointer to the target device to set the breakpoints on
196 * @param breakpoint Pointer to the breakpoint to be set
197 * @return For hardware breakpoints, this is the result of executing the JTAG
198 * queue. For software breakpoints, this will be the status of the
199 * required memory reads and writes
200 */
201 int arm7_9_set_breakpoint(struct target *target, struct breakpoint *breakpoint)
202 {
203 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
204 int retval = ERROR_OK;
205
206 LOG_DEBUG("BPID: %d, Address: 0x%08" PRIx32 ", Type: %d" ,
207 breakpoint->unique_id,
208 breakpoint->address,
209 breakpoint->type);
210
211 if (target->state != TARGET_HALTED)
212 {
213 LOG_WARNING("target not halted");
214 return ERROR_TARGET_NOT_HALTED;
215 }
216
217 if (breakpoint->type == BKPT_HARD)
218 {
219 /* either an ARM (4 byte) or Thumb (2 byte) breakpoint */
220 uint32_t mask = (breakpoint->length == 4) ? 0x3u : 0x1u;
221
222 /* reassign a hw breakpoint */
223 if (breakpoint->set == 0)
224 {
225 arm7_9_assign_wp(arm7_9, breakpoint);
226 }
227
228 if (breakpoint->set == 1)
229 {
230 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], breakpoint->address);
231 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask);
232 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffffu);
233 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
234 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
235 }
236 else if (breakpoint->set == 2)
237 {
238 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], breakpoint->address);
239 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask);
240 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffffu);
241 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
242 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
243 }
244 else
245 {
246 LOG_ERROR("BUG: no hardware comparator available");
247 return ERROR_OK;
248 }
249
250 retval = jtag_execute_queue();
251 }
252 else if (breakpoint->type == BKPT_SOFT)
253 {
254 /* did we already set this breakpoint? */
255 if (breakpoint->set)
256 return ERROR_OK;
257
258 if (breakpoint->length == 4)
259 {
260 uint32_t verify = 0xffffffff;
261 /* keep the original instruction in target endianness */
262 if ((retval = target_read_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
263 {
264 return retval;
265 }
266 /* write the breakpoint instruction in target endianness (arm7_9->arm_bkpt is host endian) */
267 if ((retval = target_write_u32(target, breakpoint->address, arm7_9->arm_bkpt)) != ERROR_OK)
268 {
269 return retval;
270 }
271
272 if ((retval = target_read_u32(target, breakpoint->address, &verify)) != ERROR_OK)
273 {
274 return retval;
275 }
276 if (verify != arm7_9->arm_bkpt)
277 {
278 LOG_ERROR("Unable to set 32 bit software breakpoint at address %08" PRIx32 " - check that memory is read/writable", breakpoint->address);
279 return ERROR_OK;
280 }
281 }
282 else
283 {
284 uint16_t verify = 0xffff;
285 /* keep the original instruction in target endianness */
286 if ((retval = target_read_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
287 {
288 return retval;
289 }
290 /* write the breakpoint instruction in target endianness (arm7_9->thumb_bkpt is host endian) */
291 if ((retval = target_write_u16(target, breakpoint->address, arm7_9->thumb_bkpt)) != ERROR_OK)
292 {
293 return retval;
294 }
295
296 if ((retval = target_read_u16(target, breakpoint->address, &verify)) != ERROR_OK)
297 {
298 return retval;
299 }
300 if (verify != arm7_9->thumb_bkpt)
301 {
302 LOG_ERROR("Unable to set thumb software breakpoint at address %08" PRIx32 " - check that memory is read/writable", breakpoint->address);
303 return ERROR_OK;
304 }
305 }
306
307 if ((retval = arm7_9_set_software_breakpoints(arm7_9)) != ERROR_OK)
308 return retval;
309
310 arm7_9->sw_breakpoint_count++;
311
312 breakpoint->set = 1;
313 }
314
315 return retval;
316 }
317
318 /**
319 * Unsets an existing breakpoint on an ARM7/9 target. If it is a hardware
320 * breakpoint, the watchpoint used will be freed and the Embedded ICE registers
321 * will be updated. Otherwise, the software breakpoint will be restored to its
322 * original instruction if it hasn't already been modified.
323 *
324 * @param target Pointer to ARM7/9 target to unset the breakpoint from
325 * @param breakpoint Pointer to breakpoint to be unset
326 * @return For hardware breakpoints, this is the result of executing the JTAG
327 * queue. For software breakpoints, this will be the status of the
328 * required memory reads and writes
329 */
330 int arm7_9_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
331 {
332 int retval = ERROR_OK;
333 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
334
335 LOG_DEBUG("BPID: %d, Address: 0x%08" PRIx32,
336 breakpoint->unique_id,
337 breakpoint->address );
338
339 if (!breakpoint->set)
340 {
341 LOG_WARNING("breakpoint not set");
342 return ERROR_OK;
343 }
344
345 if (breakpoint->type == BKPT_HARD)
346 {
347 LOG_DEBUG("BPID: %d Releasing hw wp: %d",
348 breakpoint->unique_id,
349 breakpoint->set );
350 if (breakpoint->set == 1)
351 {
352 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
353 arm7_9->wp0_used = 0;
354 arm7_9->wp_available++;
355 }
356 else if (breakpoint->set == 2)
357 {
358 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
359 arm7_9->wp1_used = 0;
360 arm7_9->wp_available++;
361 }
362 retval = jtag_execute_queue();
363 breakpoint->set = 0;
364 }
365 else
366 {
367 /* restore original instruction (kept in target endianness) */
368 if (breakpoint->length == 4)
369 {
370 uint32_t current_instr;
371 /* check that user program as not modified breakpoint instruction */
372 if ((retval = target_read_memory(target, breakpoint->address, 4, 1, (uint8_t*)&current_instr)) != ERROR_OK)
373 {
374 return retval;
375 }
376 if (current_instr == arm7_9->arm_bkpt)
377 if ((retval = target_write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
378 {
379 return retval;
380 }
381 }
382 else
383 {
384 uint16_t current_instr;
385 /* check that user program as not modified breakpoint instruction */
386 if ((retval = target_read_memory(target, breakpoint->address, 2, 1, (uint8_t*)&current_instr)) != ERROR_OK)
387 {
388 return retval;
389 }
390 if (current_instr == arm7_9->thumb_bkpt)
391 if ((retval = target_write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
392 {
393 return retval;
394 }
395 }
396
397 if (--arm7_9->sw_breakpoint_count==0)
398 {
399 /* We have removed the last sw breakpoint, clear the hw breakpoint we used to implement it */
400 if (arm7_9->sw_breakpoints_added == 1)
401 {
402 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0);
403 }
404 else if (arm7_9->sw_breakpoints_added == 2)
405 {
406 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0);
407 }
408 }
409
410 breakpoint->set = 0;
411 }
412
413 return retval;
414 }
415
416 /**
417 * Add a breakpoint to an ARM7/9 target. This makes sure that there are no
418 * dangling breakpoints and that the desired breakpoint can be added.
419 *
420 * @param target Pointer to the target ARM7/9 device to add a breakpoint to
421 * @param breakpoint Pointer to the breakpoint to be added
422 * @return An error status if there is a problem adding the breakpoint or the
423 * result of setting the breakpoint
424 */
425 int arm7_9_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
426 {
427 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
428
429 if (target->state != TARGET_HALTED)
430 {
431 LOG_WARNING("target not halted");
432 return ERROR_TARGET_NOT_HALTED;
433 }
434
435 if (arm7_9->breakpoint_count == 0)
436 {
437 /* make sure we don't have any dangling breakpoints. This is vital upon
438 * GDB connect/disconnect
439 */
440 arm7_9_clear_watchpoints(arm7_9);
441 }
442
443 if ((breakpoint->type == BKPT_HARD) && (arm7_9->wp_available < 1))
444 {
445 LOG_INFO("no watchpoint unit available for hardware breakpoint");
446 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
447 }
448
449 if ((breakpoint->length != 2) && (breakpoint->length != 4))
450 {
451 LOG_INFO("only breakpoints of two (Thumb) or four (ARM) bytes length supported");
452 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
453 }
454
455 if (breakpoint->type == BKPT_HARD)
456 {
457 arm7_9_assign_wp(arm7_9, breakpoint);
458 }
459
460 arm7_9->breakpoint_count++;
461
462 return arm7_9_set_breakpoint(target, breakpoint);
463 }
464
465 /**
466 * Removes a breakpoint from an ARM7/9 target. This will make sure there are no
467 * dangling breakpoints and updates available watchpoints if it is a hardware
468 * breakpoint.
469 *
470 * @param target Pointer to the target to have a breakpoint removed
471 * @param breakpoint Pointer to the breakpoint to be removed
472 * @return Error status if there was a problem unsetting the breakpoint or the
473 * watchpoints could not be cleared
474 */
475 int arm7_9_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
476 {
477 int retval = ERROR_OK;
478 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
479
480 if ((retval = arm7_9_unset_breakpoint(target, breakpoint)) != ERROR_OK)
481 {
482 return retval;
483 }
484
485 if (breakpoint->type == BKPT_HARD)
486 arm7_9->wp_available++;
487
488 arm7_9->breakpoint_count--;
489 if (arm7_9->breakpoint_count == 0)
490 {
491 /* make sure we don't have any dangling breakpoints */
492 if ((retval = arm7_9_clear_watchpoints(arm7_9)) != ERROR_OK)
493 {
494 return retval;
495 }
496 }
497
498 return ERROR_OK;
499 }
500
501 /**
502 * Sets a watchpoint for an ARM7/9 target in one of the watchpoint units. It is
503 * considered a bug to call this function when there are no available watchpoint
504 * units.
505 *
506 * @param target Pointer to an ARM7/9 target to set a watchpoint on
507 * @param watchpoint Pointer to the watchpoint to be set
508 * @return Error status if watchpoint set fails or the result of executing the
509 * JTAG queue
510 */
511 int arm7_9_set_watchpoint(struct target *target, struct watchpoint *watchpoint)
512 {
513 int retval = ERROR_OK;
514 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
515 int rw_mask = 1;
516 uint32_t mask;
517
518 mask = watchpoint->length - 1;
519
520 if (target->state != TARGET_HALTED)
521 {
522 LOG_WARNING("target not halted");
523 return ERROR_TARGET_NOT_HALTED;
524 }
525
526 if (watchpoint->rw == WPT_ACCESS)
527 rw_mask = 0;
528 else
529 rw_mask = 1;
530
531 if (!arm7_9->wp0_used)
532 {
533 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], watchpoint->address);
534 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask);
535 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], watchpoint->mask);
536 if (watchpoint->mask != 0xffffffffu)
537 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], watchpoint->value);
538 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
539 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
540
541 if ((retval = jtag_execute_queue()) != ERROR_OK)
542 {
543 return retval;
544 }
545 watchpoint->set = 1;
546 arm7_9->wp0_used = 2;
547 }
548 else if (!arm7_9->wp1_used)
549 {
550 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], watchpoint->address);
551 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask);
552 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], watchpoint->mask);
553 if (watchpoint->mask != 0xffffffffu)
554 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], watchpoint->value);
555 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
556 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
557
558 if ((retval = jtag_execute_queue()) != ERROR_OK)
559 {
560 return retval;
561 }
562 watchpoint->set = 2;
563 arm7_9->wp1_used = 2;
564 }
565 else
566 {
567 LOG_ERROR("BUG: no hardware comparator available");
568 return ERROR_OK;
569 }
570
571 return ERROR_OK;
572 }
573
574 /**
575 * Unset an existing watchpoint and clear the used watchpoint unit.
576 *
577 * @param target Pointer to the target to have the watchpoint removed
578 * @param watchpoint Pointer to the watchpoint to be removed
579 * @return Error status while trying to unset the watchpoint or the result of
580 * executing the JTAG queue
581 */
582 int arm7_9_unset_watchpoint(struct target *target, struct watchpoint *watchpoint)
583 {
584 int retval = ERROR_OK;
585 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
586
587 if (target->state != TARGET_HALTED)
588 {
589 LOG_WARNING("target not halted");
590 return ERROR_TARGET_NOT_HALTED;
591 }
592
593 if (!watchpoint->set)
594 {
595 LOG_WARNING("breakpoint not set");
596 return ERROR_OK;
597 }
598
599 if (watchpoint->set == 1)
600 {
601 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
602 if ((retval = jtag_execute_queue()) != ERROR_OK)
603 {
604 return retval;
605 }
606 arm7_9->wp0_used = 0;
607 }
608 else if (watchpoint->set == 2)
609 {
610 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
611 if ((retval = jtag_execute_queue()) != ERROR_OK)
612 {
613 return retval;
614 }
615 arm7_9->wp1_used = 0;
616 }
617 watchpoint->set = 0;
618
619 return ERROR_OK;
620 }
621
622 /**
623 * Add a watchpoint to an ARM7/9 target. If there are no watchpoint units
624 * available, an error response is returned.
625 *
626 * @param target Pointer to the ARM7/9 target to add a watchpoint to
627 * @param watchpoint Pointer to the watchpoint to be added
628 * @return Error status while trying to add the watchpoint
629 */
630 int arm7_9_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
631 {
632 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
633
634 if (target->state != TARGET_HALTED)
635 {
636 LOG_WARNING("target not halted");
637 return ERROR_TARGET_NOT_HALTED;
638 }
639
640 if (arm7_9->wp_available < 1)
641 {
642 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
643 }
644
645 if ((watchpoint->length != 1) && (watchpoint->length != 2) && (watchpoint->length != 4))
646 {
647 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
648 }
649
650 arm7_9->wp_available--;
651
652 return ERROR_OK;
653 }
654
655 /**
656 * Remove a watchpoint from an ARM7/9 target. The watchpoint will be unset and
657 * the used watchpoint unit will be reopened.
658 *
659 * @param target Pointer to the target to remove a watchpoint from
660 * @param watchpoint Pointer to the watchpoint to be removed
661 * @return Result of trying to unset the watchpoint
662 */
663 int arm7_9_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
664 {
665 int retval = ERROR_OK;
666 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
667
668 if (watchpoint->set)
669 {
670 if ((retval = arm7_9_unset_watchpoint(target, watchpoint)) != ERROR_OK)
671 {
672 return retval;
673 }
674 }
675
676 arm7_9->wp_available++;
677
678 return ERROR_OK;
679 }
680
681 /**
682 * Restarts the target by sending a RESTART instruction and moving the JTAG
683 * state to IDLE. This includes a timeout waiting for DBGACK and SYSCOMP to be
684 * asserted by the processor.
685 *
686 * @param target Pointer to target to issue commands to
687 * @return Error status if there is a timeout or a problem while executing the
688 * JTAG queue
689 */
690 int arm7_9_execute_sys_speed(struct target *target)
691 {
692 int retval;
693 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
694 struct arm_jtag *jtag_info = &arm7_9->jtag_info;
695 struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
696
697 /* set RESTART instruction */
698 jtag_set_end_state(TAP_IDLE);
699 if (arm7_9->need_bypass_before_restart) {
700 arm7_9->need_bypass_before_restart = 0;
701 arm_jtag_set_instr(jtag_info, 0xf, NULL);
702 }
703 arm_jtag_set_instr(jtag_info, 0x4, NULL);
704
705 long long then = timeval_ms();
706 int timeout;
707 while (!(timeout = ((timeval_ms()-then) > 1000)))
708 {
709 /* read debug status register */
710 embeddedice_read_reg(dbg_stat);
711 if ((retval = jtag_execute_queue()) != ERROR_OK)
712 return retval;
713 if ((buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))
714 && (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_SYSCOMP, 1)))
715 break;
716 if (debug_level >= 3)
717 {
718 alive_sleep(100);
719 } else
720 {
721 keep_alive();
722 }
723 }
724 if (timeout)
725 {
726 LOG_ERROR("timeout waiting for SYSCOMP & DBGACK, last DBG_STATUS: %" PRIx32 "", buf_get_u32(dbg_stat->value, 0, dbg_stat->size));
727 return ERROR_TARGET_TIMEOUT;
728 }
729
730 return ERROR_OK;
731 }
732
733 /**
734 * Restarts the target by sending a RESTART instruction and moving the JTAG
735 * state to IDLE. This validates that DBGACK and SYSCOMP are set without
736 * waiting until they are.
737 *
738 * @param target Pointer to the target to issue commands to
739 * @return Always ERROR_OK
740 */
741 int arm7_9_execute_fast_sys_speed(struct target *target)
742 {
743 static int set = 0;
744 static uint8_t check_value[4], check_mask[4];
745
746 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
747 struct arm_jtag *jtag_info = &arm7_9->jtag_info;
748 struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
749
750 /* set RESTART instruction */
751 jtag_set_end_state(TAP_IDLE);
752 if (arm7_9->need_bypass_before_restart) {
753 arm7_9->need_bypass_before_restart = 0;
754 arm_jtag_set_instr(jtag_info, 0xf, NULL);
755 }
756 arm_jtag_set_instr(jtag_info, 0x4, NULL);
757
758 if (!set)
759 {
760 /* check for DBGACK and SYSCOMP set (others don't care) */
761
762 /* NB! These are constants that must be available until after next jtag_execute() and
763 * we evaluate the values upon first execution in lieu of setting up these constants
764 * during early setup.
765 * */
766 buf_set_u32(check_value, 0, 32, 0x9);
767 buf_set_u32(check_mask, 0, 32, 0x9);
768 set = 1;
769 }
770
771 /* read debug status register */
772 embeddedice_read_reg_w_check(dbg_stat, check_value, check_mask);
773
774 return ERROR_OK;
775 }
776
777 /**
778 * Get some data from the ARM7/9 target.
779 *
780 * @param target Pointer to the ARM7/9 target to read data from
781 * @param size The number of 32bit words to be read
782 * @param buffer Pointer to the buffer that will hold the data
783 * @return The result of receiving data from the Embedded ICE unit
784 */
785 int arm7_9_target_request_data(struct target *target, uint32_t size, uint8_t *buffer)
786 {
787 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
788 struct arm_jtag *jtag_info = &arm7_9->jtag_info;
789 uint32_t *data;
790 int retval = ERROR_OK;
791 uint32_t i;
792
793 data = malloc(size * (sizeof(uint32_t)));
794
795 retval = embeddedice_receive(jtag_info, data, size);
796
797 /* return the 32-bit ints in the 8-bit array */
798 for (i = 0; i < size; i++)
799 {
800 h_u32_to_le(buffer + (i * 4), data[i]);
801 }
802
803 free(data);
804
805 return retval;
806 }
807
808 /**
809 * Handles requests to an ARM7/9 target. If debug messaging is enabled, the
810 * target is running and the DCC control register has the W bit high, this will
811 * execute the request on the target.
812 *
813 * @param priv Void pointer expected to be a struct target pointer
814 * @return ERROR_OK unless there are issues with the JTAG queue or when reading
815 * from the Embedded ICE unit
816 */
817 int arm7_9_handle_target_request(void *priv)
818 {
819 int retval = ERROR_OK;
820 struct target *target = priv;
821 if (!target_was_examined(target))
822 return ERROR_OK;
823 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
824 struct arm_jtag *jtag_info = &arm7_9->jtag_info;
825 struct reg *dcc_control = &arm7_9->eice_cache->reg_list[EICE_COMMS_CTRL];
826
827 if (!target->dbg_msg_enabled)
828 return ERROR_OK;
829
830 if (target->state == TARGET_RUNNING)
831 {
832 /* read DCC control register */
833 embeddedice_read_reg(dcc_control);
834 if ((retval = jtag_execute_queue()) != ERROR_OK)
835 {
836 return retval;
837 }
838
839 /* check W bit */
840 if (buf_get_u32(dcc_control->value, 1, 1) == 1)
841 {
842 uint32_t request;
843
844 if ((retval = embeddedice_receive(jtag_info, &request, 1)) != ERROR_OK)
845 {
846 return retval;
847 }
848 if ((retval = target_request(target, request)) != ERROR_OK)
849 {
850 return retval;
851 }
852 }
853 }
854
855 return ERROR_OK;
856 }
857
858 /**
859 * Polls an ARM7/9 target for its current status. If DBGACK is set, the target
860 * is manipulated to the right halted state based on its current state. This is
861 * what happens:
862 *
863 * <table>
864 * <tr><th > State</th><th > Action</th></tr>
865 * <tr><td > TARGET_RUNNING | TARGET_RESET</td><td > Enters debug mode. If TARGET_RESET, pc may be checked</td></tr>
866 * <tr><td > TARGET_UNKNOWN</td><td > Warning is logged</td></tr>
867 * <tr><td > TARGET_DEBUG_RUNNING</td><td > Enters debug mode</td></tr>
868 * <tr><td > TARGET_HALTED</td><td > Nothing</td></tr>
869 * </table>
870 *
871 * If the target does not end up in the halted state, a warning is produced. If
872 * DBGACK is cleared, then the target is expected to either be running or
873 * running in debug.
874 *
875 * @param target Pointer to the ARM7/9 target to poll
876 * @return ERROR_OK or an error status if a command fails
877 */
878 int arm7_9_poll(struct target *target)
879 {
880 int retval;
881 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
882 struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
883
884 /* read debug status register */
885 embeddedice_read_reg(dbg_stat);
886 if ((retval = jtag_execute_queue()) != ERROR_OK)
887 {
888 return retval;
889 }
890
891 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))
892 {
893 /* LOG_DEBUG("DBGACK set, dbg_state->value: 0x%x", buf_get_u32(dbg_stat->value, 0, 32));*/
894 if (target->state == TARGET_UNKNOWN)
895 {
896 /* Starting OpenOCD with target in debug-halt */
897 target->state = TARGET_RUNNING;
898 LOG_DEBUG("DBGACK already set during server startup.");
899 }
900 if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET))
901 {
902 int check_pc = 0;
903 if (target->state == TARGET_RESET)
904 {
905 if (target->reset_halt)
906 {
907 enum reset_types jtag_reset_config = jtag_get_reset_config();
908 if ((jtag_reset_config & RESET_SRST_PULLS_TRST) == 0)
909 {
910 check_pc = 1;
911 }
912 }
913 }
914
915 target->state = TARGET_HALTED;
916
917 if ((retval = arm7_9_debug_entry(target)) != ERROR_OK)
918 return retval;
919
920 if (check_pc)
921 {
922 struct reg *reg = register_get_by_name(target->reg_cache, "pc", 1);
923 uint32_t t=*((uint32_t *)reg->value);
924 if (t != 0)
925 {
926 LOG_ERROR("PC was not 0. Does this target need srst_pulls_trst?");
927 }
928 }
929
930 if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
931 {
932 return retval;
933 }
934 }
935 if (target->state == TARGET_DEBUG_RUNNING)
936 {
937 target->state = TARGET_HALTED;
938 if ((retval = arm7_9_debug_entry(target)) != ERROR_OK)
939 return retval;
940
941 if ((retval = target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED)) != ERROR_OK)
942 {
943 return retval;
944 }
945 }
946 if (target->state != TARGET_HALTED)
947 {
948 LOG_WARNING("DBGACK set, but the target did not end up in the halted state %d", target->state);
949 }
950 }
951 else
952 {
953 if (target->state != TARGET_DEBUG_RUNNING)
954 target->state = TARGET_RUNNING;
955 }
956
957 return ERROR_OK;
958 }
959
960 /**
961 * Asserts the reset (SRST) on an ARM7/9 target. Some -S targets (ARM966E-S in
962 * the STR912 isn't affected, ARM926EJ-S in the LPC3180 and AT91SAM9260 is
963 * affected) completely stop the JTAG clock while the core is held in reset
964 * (SRST). It isn't possible to program the halt condition once reset is
965 * asserted, hence a hook that allows the target to set up its reset-halt
966 * condition is setup prior to asserting reset.
967 *
968 * @param target Pointer to an ARM7/9 target to assert reset on
969 * @return ERROR_FAIL if the JTAG device does not have SRST, otherwise ERROR_OK
970 */
971 int arm7_9_assert_reset(struct target *target)
972 {
973 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
974
975 LOG_DEBUG("target->state: %s",
976 target_state_name(target));
977
978 enum reset_types jtag_reset_config = jtag_get_reset_config();
979 if (!(jtag_reset_config & RESET_HAS_SRST))
980 {
981 LOG_ERROR("Can't assert SRST");
982 return ERROR_FAIL;
983 }
984
985 /* At this point trst has been asserted/deasserted once. We would
986 * like to program EmbeddedICE while SRST is asserted, instead of
987 * depending on SRST to leave that module alone. However, many CPUs
988 * gate the JTAG clock while SRST is asserted; or JTAG may need
989 * clock stability guarantees (adaptive clocking might help).
990 *
991 * So we assume JTAG access during SRST is off the menu unless it's
992 * been specifically enabled.
993 */
994 bool srst_asserted = false;
995
996 if (((jtag_reset_config & RESET_SRST_PULLS_TRST) == 0)
997 && (jtag_reset_config & RESET_SRST_NO_GATING))
998 {
999 jtag_add_reset(0, 1);
1000 srst_asserted = true;
1001 }
1002
1003 if (target->reset_halt)
1004 {
1005 /*
1006 * Some targets do not support communication while SRST is asserted. We need to
1007 * set up the reset vector catch here.
1008 *
1009 * If TRST is asserted, then these settings will be reset anyway, so setting them
1010 * here is harmless.
1011 */
1012 if (arm7_9->has_vector_catch)
1013 {
1014 /* program vector catch register to catch reset vector */
1015 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH], 0x1);
1016
1017 /* extra runtest added as issues were found with certain ARM9 cores (maybe more) - AT91SAM9260 and STR9 */
1018 jtag_add_runtest(1, jtag_get_end_state());
1019 }
1020 else
1021 {
1022 /* program watchpoint unit to match on reset vector address */
1023 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], 0x0);
1024 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0x3);
1025 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
1026 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
1027 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
1028 }
1029 }
1030
1031 /* here we should issue an SRST only, but we may have to assert TRST as well */
1032 if (jtag_reset_config & RESET_SRST_PULLS_TRST)
1033 {
1034 jtag_add_reset(1, 1);
1035 } else if (!srst_asserted)
1036 {
1037 jtag_add_reset(0, 1);
1038 }
1039
1040 target->state = TARGET_RESET;
1041 jtag_add_sleep(50000);
1042
1043 register_cache_invalidate(arm7_9->armv4_5_common.core_cache);
1044
1045 if ((target->reset_halt) && ((jtag_reset_config & RESET_SRST_PULLS_TRST) == 0))
1046 {
1047 /* debug entry was already prepared in arm7_9_assert_reset() */
1048 target->debug_reason = DBG_REASON_DBGRQ;
1049 }
1050
1051 return ERROR_OK;
1052 }
1053
1054 /**
1055 * Deassert the reset (SRST) signal on an ARM7/9 target. If SRST pulls TRST
1056 * and the target is being reset into a halt, a warning will be triggered
1057 * because it is not possible to reset into a halted mode in this case. The
1058 * target is halted using the target's functions.
1059 *
1060 * @param target Pointer to the target to have the reset deasserted
1061 * @return ERROR_OK or an error from polling or halting the target
1062 */
1063 int arm7_9_deassert_reset(struct target *target)
1064 {
1065 int retval = ERROR_OK;
1066 LOG_DEBUG("target->state: %s",
1067 target_state_name(target));
1068
1069 /* deassert reset lines */
1070 jtag_add_reset(0, 0);
1071
1072 enum reset_types jtag_reset_config = jtag_get_reset_config();
1073 if (target->reset_halt && (jtag_reset_config & RESET_SRST_PULLS_TRST) != 0)
1074 {
1075 LOG_WARNING("srst pulls trst - can not reset into halted mode. Issuing halt after reset.");
1076 /* set up embedded ice registers again */
1077 if ((retval = target_examine_one(target)) != ERROR_OK)
1078 return retval;
1079
1080 if ((retval = target_poll(target)) != ERROR_OK)
1081 {
1082 return retval;
1083 }
1084
1085 if ((retval = target_halt(target)) != ERROR_OK)
1086 {
1087 return retval;
1088 }
1089
1090 }
1091 return retval;
1092 }
1093
1094 /**
1095 * Clears the halt condition for an ARM7/9 target. If it isn't coming out of
1096 * reset and if DBGRQ is used, it is progammed to be deasserted. If the reset
1097 * vector catch was used, it is restored. Otherwise, the control value is
1098 * restored and the watchpoint unit is restored if it was in use.
1099 *
1100 * @param target Pointer to the ARM7/9 target to have halt cleared
1101 * @return Always ERROR_OK
1102 */
1103 int arm7_9_clear_halt(struct target *target)
1104 {
1105 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
1106 struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1107
1108 /* we used DBGRQ only if we didn't come out of reset */
1109 if (!arm7_9->debug_entry_from_reset && arm7_9->use_dbgrq)
1110 {
1111 /* program EmbeddedICE Debug Control Register to deassert DBGRQ
1112 */
1113 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
1114 embeddedice_store_reg(dbg_ctrl);
1115 }
1116 else
1117 {
1118 if (arm7_9->debug_entry_from_reset && arm7_9->has_vector_catch)
1119 {
1120 /* if we came out of reset, and vector catch is supported, we used
1121 * vector catch to enter debug state
1122 * restore the register in that case
1123 */
1124 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH]);
1125 }
1126 else
1127 {
1128 /* restore registers if watchpoint unit 0 was in use
1129 */
1130 if (arm7_9->wp0_used)
1131 {
1132 if (arm7_9->debug_entry_from_reset)
1133 {
1134 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE]);
1135 }
1136 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
1137 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);
1138 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK]);
1139 }
1140 /* control value always has to be restored, as it was either disabled,
1141 * or enabled with possibly different bits
1142 */
1143 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]);
1144 }
1145 }
1146
1147 return ERROR_OK;
1148 }
1149
1150 /**
1151 * Issue a software reset and halt to an ARM7/9 target. The target is halted
1152 * and then there is a wait until the processor shows the halt. This wait can
1153 * timeout and results in an error being returned. The software reset involves
1154 * clearing the halt, updating the debug control register, changing to ARM mode,
1155 * reset of the program counter, and reset of all of the registers.
1156 *
1157 * @param target Pointer to the ARM7/9 target to be reset and halted by software
1158 * @return Error status if any of the commands fail, otherwise ERROR_OK
1159 */
1160 int arm7_9_soft_reset_halt(struct target *target)
1161 {
1162 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
1163 struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
1164 struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
1165 struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1166 int i;
1167 int retval;
1168
1169 /* FIX!!! replace some of this code with tcl commands
1170 *
1171 * halt # the halt command is synchronous
1172 * armv4_5 core_state arm
1173 *
1174 */
1175
1176 if ((retval = target_halt(target)) != ERROR_OK)
1177 return retval;
1178
1179 long long then = timeval_ms();
1180 int timeout;
1181 while (!(timeout = ((timeval_ms()-then) > 1000)))
1182 {
1183 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) != 0)
1184 break;
1185 embeddedice_read_reg(dbg_stat);
1186 if ((retval = jtag_execute_queue()) != ERROR_OK)
1187 return retval;
1188 if (debug_level >= 3)
1189 {
1190 alive_sleep(100);
1191 } else
1192 {
1193 keep_alive();
1194 }
1195 }
1196 if (timeout)
1197 {
1198 LOG_ERROR("Failed to halt CPU after 1 sec");
1199 return ERROR_TARGET_TIMEOUT;
1200 }
1201 target->state = TARGET_HALTED;
1202
1203 /* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS
1204 * ensure that DBGRQ is cleared
1205 */
1206 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
1207 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
1208 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 1);
1209 embeddedice_store_reg(dbg_ctrl);
1210
1211 if ((retval = arm7_9_clear_halt(target)) != ERROR_OK)
1212 {
1213 return retval;
1214 }
1215
1216 /* if the target is in Thumb state, change to ARM state */
1217 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_ITBIT, 1))
1218 {
1219 uint32_t r0_thumb, pc_thumb;
1220 LOG_DEBUG("target entered debug from Thumb state, changing to ARM");
1221 /* Entered debug from Thumb mode */
1222 armv4_5->core_state = ARMV4_5_STATE_THUMB;
1223 arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb);
1224 }
1225
1226 /* all register content is now invalid */
1227 register_cache_invalidate(armv4_5->core_cache);
1228
1229 /* SVC, ARM state, IRQ and FIQ disabled */
1230 buf_set_u32(armv4_5->cpsr->value, 0, 8, 0xd3);
1231 armv4_5->cpsr->dirty = 1;
1232 armv4_5->cpsr->valid = 1;
1233
1234 /* start fetching from 0x0 */
1235 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
1236 armv4_5->core_cache->reg_list[15].dirty = 1;
1237 armv4_5->core_cache->reg_list[15].valid = 1;
1238
1239 armv4_5->core_mode = ARMV4_5_MODE_SVC;
1240 armv4_5->core_state = ARMV4_5_STATE_ARM;
1241
1242 /* reset registers */
1243 for (i = 0; i <= 14; i++)
1244 {
1245 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32, 0xffffffff);
1246 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 1;
1247 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid = 1;
1248 }
1249
1250 if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
1251 {
1252 return retval;
1253 }
1254
1255 return ERROR_OK;
1256 }
1257
1258 /**
1259 * Halt an ARM7/9 target. This is accomplished by either asserting the DBGRQ
1260 * line or by programming a watchpoint to trigger on any address. It is
1261 * considered a bug to call this function while the target is in the
1262 * TARGET_RESET state.
1263 *
1264 * @param target Pointer to the ARM7/9 target to be halted
1265 * @return Always ERROR_OK
1266 */
1267 int arm7_9_halt(struct target *target)
1268 {
1269 if (target->state == TARGET_RESET)
1270 {
1271 LOG_ERROR("BUG: arm7/9 does not support halt during reset. This is handled in arm7_9_assert_reset()");
1272 return ERROR_OK;
1273 }
1274
1275 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
1276 struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1277
1278 LOG_DEBUG("target->state: %s",
1279 target_state_name(target));
1280
1281 if (target->state == TARGET_HALTED)
1282 {
1283 LOG_DEBUG("target was already halted");
1284 return ERROR_OK;
1285 }
1286
1287 if (target->state == TARGET_UNKNOWN)
1288 {
1289 LOG_WARNING("target was in unknown state when halt was requested");
1290 }
1291
1292 if (arm7_9->use_dbgrq)
1293 {
1294 /* program EmbeddedICE Debug Control Register to assert DBGRQ
1295 */
1296 if (arm7_9->set_special_dbgrq) {
1297 arm7_9->set_special_dbgrq(target);
1298 } else {
1299 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 1);
1300 embeddedice_store_reg(dbg_ctrl);
1301 }
1302 }
1303 else
1304 {
1305 /* program watchpoint unit to match on any address
1306 */
1307 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
1308 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
1309 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
1310 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
1311 }
1312
1313 target->debug_reason = DBG_REASON_DBGRQ;
1314
1315 return ERROR_OK;
1316 }
1317
1318 /**
1319 * Handle an ARM7/9 target's entry into debug mode. The halt is cleared on the
1320 * ARM. The JTAG queue is then executed and the reason for debug entry is
1321 * examined. Once done, the target is verified to be halted and the processor
1322 * is forced into ARM mode. The core registers are saved for the current core
1323 * mode and the program counter (register 15) is updated as needed. The core
1324 * registers and CPSR and SPSR are saved for restoration later.
1325 *
1326 * @param target Pointer to target that is entering debug mode
1327 * @return Error code if anything fails, otherwise ERROR_OK
1328 */
1329 static int arm7_9_debug_entry(struct target *target)
1330 {
1331 int i;
1332 uint32_t context[16];
1333 uint32_t* context_p[16];
1334 uint32_t r0_thumb, pc_thumb;
1335 uint32_t cpsr;
1336 int retval;
1337 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
1338 struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
1339 struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
1340 struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1341
1342 #ifdef _DEBUG_ARM7_9_
1343 LOG_DEBUG("-");
1344 #endif
1345
1346 /* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS
1347 * ensure that DBGRQ is cleared
1348 */
1349 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
1350 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
1351 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 1);
1352 embeddedice_store_reg(dbg_ctrl);
1353
1354 if ((retval = arm7_9_clear_halt(target)) != ERROR_OK)
1355 {
1356 return retval;
1357 }
1358
1359 if ((retval = jtag_execute_queue()) != ERROR_OK)
1360 {
1361 return retval;
1362 }
1363
1364 if ((retval = arm7_9->examine_debug_reason(target)) != ERROR_OK)
1365 return retval;
1366
1367
1368 if (target->state != TARGET_HALTED)
1369 {
1370 LOG_WARNING("target not halted");
1371 return ERROR_TARGET_NOT_HALTED;
1372 }
1373
1374 /* if the target is in Thumb state, change to ARM state */
1375 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_ITBIT, 1))
1376 {
1377 LOG_DEBUG("target entered debug from Thumb state");
1378 /* Entered debug from Thumb mode */
1379 armv4_5->core_state = ARMV4_5_STATE_THUMB;
1380 arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb);
1381 LOG_DEBUG("r0_thumb: 0x%8.8" PRIx32 ", pc_thumb: 0x%8.8" PRIx32 "", r0_thumb, pc_thumb);
1382 }
1383 else
1384 {
1385 LOG_DEBUG("target entered debug from ARM state");
1386 /* Entered debug from ARM mode */
1387 armv4_5->core_state = ARMV4_5_STATE_ARM;
1388 }
1389
1390 for (i = 0; i < 16; i++)
1391 context_p[i] = &context[i];
1392 /* save core registers (r0 - r15 of current core mode) */
1393 arm7_9->read_core_regs(target, 0xffff, context_p);
1394
1395 arm7_9->read_xpsr(target, &cpsr, 0);
1396
1397 if ((retval = jtag_execute_queue()) != ERROR_OK)
1398 return retval;
1399
1400 /* if the core has been executing in Thumb state, set the T bit */
1401 if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1402 cpsr |= 0x20;
1403
1404 buf_set_u32(armv4_5->cpsr->value, 0, 32, cpsr);
1405 armv4_5->cpsr->dirty = 0;
1406 armv4_5->cpsr->valid = 1;
1407
1408 armv4_5->core_mode = cpsr & 0x1f;
1409
1410 if (!is_arm_mode(armv4_5->core_mode))
1411 {
1412 target->state = TARGET_UNKNOWN;
1413 LOG_ERROR("cpsr contains invalid mode value - communication failure");
1414 return ERROR_TARGET_FAILURE;
1415 }
1416
1417 LOG_DEBUG("target entered debug state in %s mode",
1418 arm_mode_name(armv4_5->core_mode));
1419
1420 if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1421 {
1422 LOG_DEBUG("thumb state, applying fixups");
1423 context[0] = r0_thumb;
1424 context[15] = pc_thumb;
1425 } else if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1426 {
1427 /* adjust value stored by STM */
1428 context[15] -= 3 * 4;
1429 }
1430
1431 if ((target->debug_reason != DBG_REASON_DBGRQ) || (!arm7_9->use_dbgrq))
1432 context[15] -= 3 * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2);
1433 else
1434 context[15] -= arm7_9->dbgreq_adjust_pc * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2);
1435
1436 for (i = 0; i <= 15; i++)
1437 {
1438 LOG_DEBUG("r%i: 0x%8.8" PRIx32 "", i, context[i]);
1439 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32, context[i]);
1440 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 0;
1441 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid = 1;
1442 }
1443
1444 LOG_DEBUG("entered debug state at PC 0x%" PRIx32 "", context[15]);
1445
1446 /* exceptions other than USR & SYS have a saved program status register */
1447 if ((armv4_5->core_mode != ARMV4_5_MODE_USR) && (armv4_5->core_mode != ARMV4_5_MODE_SYS))
1448 {
1449 uint32_t spsr;
1450 arm7_9->read_xpsr(target, &spsr, 1);
1451 if ((retval = jtag_execute_queue()) != ERROR_OK)
1452 {
1453 return retval;
1454 }
1455 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).value, 0, 32, spsr);
1456 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).dirty = 0;
1457 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).valid = 1;
1458 }
1459
1460 /* r0 and r15 (pc) have to be restored later */
1461 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).valid;
1462 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15).valid;
1463
1464 if ((retval = jtag_execute_queue()) != ERROR_OK)
1465 return retval;
1466
1467 if (arm7_9->post_debug_entry)
1468 arm7_9->post_debug_entry(target);
1469
1470 return ERROR_OK;
1471 }
1472
1473 /**
1474 * Validate the full context for an ARM7/9 target in all processor modes. If
1475 * there are any invalid registers for the target, they will all be read. This
1476 * includes the PSR.
1477 *
1478 * @param target Pointer to the ARM7/9 target to capture the full context from
1479 * @return Error if the target is not halted, has an invalid core mode, or if
1480 * the JTAG queue fails to execute
1481 */
1482 int arm7_9_full_context(struct target *target)
1483 {
1484 int i;
1485 int retval;
1486 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
1487 struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
1488
1489 LOG_DEBUG("-");
1490
1491 if (target->state != TARGET_HALTED)
1492 {
1493 LOG_WARNING("target not halted");
1494 return ERROR_TARGET_NOT_HALTED;
1495 }
1496
1497 if (!is_arm_mode(armv4_5->core_mode))
1498 return ERROR_FAIL;
1499
1500 /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
1501 * SYS shares registers with User, so we don't touch SYS
1502 */
1503 for (i = 0; i < 6; i++)
1504 {
1505 uint32_t mask = 0;
1506 uint32_t* reg_p[16];
1507 int j;
1508 int valid = 1;
1509
1510 /* check if there are invalid registers in the current mode
1511 */
1512 for (j = 0; j <= 16; j++)
1513 {
1514 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid == 0)
1515 valid = 0;
1516 }
1517
1518 if (!valid)
1519 {
1520 uint32_t tmp_cpsr;
1521
1522 /* change processor mode (and mask T bit) */
1523 tmp_cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 8)
1524 & 0xe0;
1525 tmp_cpsr |= armv4_5_number_to_mode(i);
1526 tmp_cpsr &= ~0x20;
1527 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1528
1529 for (j = 0; j < 15; j++)
1530 {
1531 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid == 0)
1532 {
1533 reg_p[j] = (uint32_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).value;
1534 mask |= 1 << j;
1535 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid = 1;
1536 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).dirty = 0;
1537 }
1538 }
1539
1540 /* if only the PSR is invalid, mask is all zeroes */
1541 if (mask)
1542 arm7_9->read_core_regs(target, mask, reg_p);
1543
1544 /* check if the PSR has to be read */
1545 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).valid == 0)
1546 {
1547 arm7_9->read_xpsr(target, (uint32_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).value, 1);
1548 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).valid = 1;
1549 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).dirty = 0;
1550 }
1551 }
1552 }
1553
1554 /* restore processor mode (mask T bit) */
1555 arm7_9->write_xpsr_im8(target,
1556 buf_get_u32(armv4_5->cpsr->value, 0, 8) & ~0x20,
1557 0, 0);
1558
1559 if ((retval = jtag_execute_queue()) != ERROR_OK)
1560 {
1561 return retval;
1562 }
1563 return ERROR_OK;
1564 }
1565
1566 /**
1567 * Restore the processor context on an ARM7/9 target. The full processor
1568 * context is analyzed to see if any of the registers are dirty on this end, but
1569 * have a valid new value. If this is the case, the processor is changed to the
1570 * appropriate mode and the new register values are written out to the
1571 * processor. If there happens to be a dirty register with an invalid value, an
1572 * error will be logged.
1573 *
1574 * @param target Pointer to the ARM7/9 target to have its context restored
1575 * @return Error status if the target is not halted or the core mode in the
1576 * armv4_5 struct is invalid.
1577 */
1578 int arm7_9_restore_context(struct target *target)
1579 {
1580 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
1581 struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
1582 struct reg *reg;
1583 struct arm_reg *reg_arch_info;
1584 enum armv4_5_mode current_mode = armv4_5->core_mode;
1585 int i, j;
1586 int dirty;
1587 int mode_change;
1588
1589 LOG_DEBUG("-");
1590
1591 if (target->state != TARGET_HALTED)
1592 {
1593 LOG_WARNING("target not halted");
1594 return ERROR_TARGET_NOT_HALTED;
1595 }
1596
1597 if (arm7_9->pre_restore_context)
1598 arm7_9->pre_restore_context(target);
1599
1600 if (!is_arm_mode(armv4_5->core_mode))
1601 return ERROR_FAIL;
1602
1603 /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
1604 * SYS shares registers with User, so we don't touch SYS
1605 */
1606 for (i = 0; i < 6; i++)
1607 {
1608 LOG_DEBUG("examining %s mode",
1609 arm_mode_name(armv4_5->core_mode));
1610 dirty = 0;
1611 mode_change = 0;
1612 /* check if there are dirty registers in the current mode
1613 */
1614 for (j = 0; j <= 16; j++)
1615 {
1616 reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j);
1617 reg_arch_info = reg->arch_info;
1618 if (reg->dirty == 1)
1619 {
1620 if (reg->valid == 1)
1621 {
1622 dirty = 1;
1623 LOG_DEBUG("examining dirty reg: %s", reg->name);
1624 if ((reg_arch_info->mode != ARMV4_5_MODE_ANY)
1625 && (reg_arch_info->mode != current_mode)
1626 && !((reg_arch_info->mode == ARMV4_5_MODE_USR) && (armv4_5->core_mode == ARMV4_5_MODE_SYS))
1627 && !((reg_arch_info->mode == ARMV4_5_MODE_SYS) && (armv4_5->core_mode == ARMV4_5_MODE_USR)))
1628 {
1629 mode_change = 1;
1630 LOG_DEBUG("require mode change");
1631 }
1632 }
1633 else
1634 {
1635 LOG_ERROR("BUG: dirty register '%s', but no valid data", reg->name);
1636 }
1637 }
1638 }
1639
1640 if (dirty)
1641 {
1642 uint32_t mask = 0x0;
1643 int num_regs = 0;
1644 uint32_t regs[16];
1645
1646 if (mode_change)
1647 {
1648 uint32_t tmp_cpsr;
1649
1650 /* change processor mode (mask T bit) */
1651 tmp_cpsr = buf_get_u32(armv4_5->cpsr->value,
1652 0, 8) & 0xe0;
1653 tmp_cpsr |= armv4_5_number_to_mode(i);
1654 tmp_cpsr &= ~0x20;
1655 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1656 current_mode = armv4_5_number_to_mode(i);
1657 }
1658
1659 for (j = 0; j <= 14; j++)
1660 {
1661 reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j);
1662 reg_arch_info = reg->arch_info;
1663
1664
1665 if (reg->dirty == 1)
1666 {
1667 regs[j] = buf_get_u32(reg->value, 0, 32);
1668 mask |= 1 << j;
1669 num_regs++;
1670 reg->dirty = 0;
1671 reg->valid = 1;
1672 LOG_DEBUG("writing register %i mode %s "
1673 "with value 0x%8.8" PRIx32, j,
1674 arm_mode_name(armv4_5->core_mode),
1675 regs[j]);
1676 }
1677 }
1678
1679 if (mask)
1680 {
1681 arm7_9->write_core_regs(target, mask, regs);
1682 }
1683
1684 reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16);
1685 reg_arch_info = reg->arch_info;
1686 if ((reg->dirty) && (reg_arch_info->mode != ARMV4_5_MODE_ANY))
1687 {
1688 LOG_DEBUG("writing SPSR of mode %i with value 0x%8.8" PRIx32 "", i, buf_get_u32(reg->value, 0, 32));
1689 arm7_9->write_xpsr(target, buf_get_u32(reg->value, 0, 32), 1);
1690 }
1691 }
1692 }
1693
1694 if (!armv4_5->cpsr->dirty && (armv4_5->core_mode != current_mode))
1695 {
1696 /* restore processor mode (mask T bit) */
1697 uint32_t tmp_cpsr;
1698
1699 tmp_cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 8) & 0xE0;
1700 tmp_cpsr |= armv4_5_number_to_mode(i);
1701 tmp_cpsr &= ~0x20;
1702 LOG_DEBUG("writing lower 8 bit of cpsr with value 0x%2.2x", (unsigned)(tmp_cpsr));
1703 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1704 }
1705 else if (armv4_5->cpsr->dirty)
1706 {
1707 /* CPSR has been changed, full restore necessary (mask T bit) */
1708 LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32,
1709 buf_get_u32(armv4_5->cpsr->value, 0, 32));
1710 arm7_9->write_xpsr(target,
1711 buf_get_u32(armv4_5->cpsr->value, 0, 32)
1712 & ~0x20, 0);
1713 armv4_5->cpsr->dirty = 0;
1714 armv4_5->cpsr->valid = 1;
1715 }
1716
1717 /* restore PC */
1718 LOG_DEBUG("writing PC with value 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1719 arm7_9->write_pc(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1720 armv4_5->core_cache->reg_list[15].dirty = 0;
1721
1722 if (arm7_9->post_restore_context)
1723 arm7_9->post_restore_context(target);
1724
1725 return ERROR_OK;
1726 }
1727
1728 /**
1729 * Restart the core of an ARM7/9 target. A RESTART command is sent to the
1730 * instruction register and the JTAG state is set to TAP_IDLE causing a core
1731 * restart.
1732 *
1733 * @param target Pointer to the ARM7/9 target to be restarted
1734 * @return Result of executing the JTAG queue
1735 */
1736 int arm7_9_restart_core(struct target *target)
1737 {
1738 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
1739 struct arm_jtag *jtag_info = &arm7_9->jtag_info;
1740
1741 /* set RESTART instruction */
1742 jtag_set_end_state(TAP_IDLE);
1743 if (arm7_9->need_bypass_before_restart) {
1744 arm7_9->need_bypass_before_restart = 0;
1745 arm_jtag_set_instr(jtag_info, 0xf, NULL);
1746 }
1747 arm_jtag_set_instr(jtag_info, 0x4, NULL);
1748
1749 jtag_add_runtest(1, jtag_set_end_state(TAP_IDLE));
1750 return jtag_execute_queue();
1751 }
1752
1753 /**
1754 * Enable the watchpoints on an ARM7/9 target. The target's watchpoints are
1755 * iterated through and are set on the target if they aren't already set.
1756 *
1757 * @param target Pointer to the ARM7/9 target to enable watchpoints on
1758 */
1759 void arm7_9_enable_watchpoints(struct target *target)
1760 {
1761 struct watchpoint *watchpoint = target->watchpoints;
1762
1763 while (watchpoint)
1764 {
1765 if (watchpoint->set == 0)
1766 arm7_9_set_watchpoint(target, watchpoint);
1767 watchpoint = watchpoint->next;
1768 }
1769 }
1770
1771 /**
1772 * Enable the breakpoints on an ARM7/9 target. The target's breakpoints are
1773 * iterated through and are set on the target.
1774 *
1775 * @param target Pointer to the ARM7/9 target to enable breakpoints on
1776 */
1777 void arm7_9_enable_breakpoints(struct target *target)
1778 {
1779 struct breakpoint *breakpoint = target->breakpoints;
1780
1781 /* set any pending breakpoints */
1782 while (breakpoint)
1783 {
1784 arm7_9_set_breakpoint(target, breakpoint);
1785 breakpoint = breakpoint->next;
1786 }
1787 }
1788
1789 int arm7_9_resume(struct target *target, int current, uint32_t address, int handle_breakpoints, int debug_execution)
1790 {
1791 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
1792 struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
1793 struct breakpoint *breakpoint = target->breakpoints;
1794 struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1795 int err, retval = ERROR_OK;
1796
1797 LOG_DEBUG("-");
1798
1799 if (target->state != TARGET_HALTED)
1800 {
1801 LOG_WARNING("target not halted");
1802 return ERROR_TARGET_NOT_HALTED;
1803 }
1804
1805 if (!debug_execution)
1806 {
1807 target_free_all_working_areas(target);
1808 }
1809
1810 /* current = 1: continue on current pc, otherwise continue at <address> */
1811 if (!current)
1812 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
1813
1814 uint32_t current_pc;
1815 current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
1816
1817 /* the front-end may request us not to handle breakpoints */
1818 if (handle_breakpoints)
1819 {
1820 if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
1821 {
1822 LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 " (id: %d)", breakpoint->address, breakpoint->unique_id );
1823 if ((retval = arm7_9_unset_breakpoint(target, breakpoint)) != ERROR_OK)
1824 {
1825 return retval;
1826 }
1827
1828 /* calculate PC of next instruction */
1829 uint32_t next_pc;
1830 if ((retval = arm_simulate_step(target, &next_pc)) != ERROR_OK)
1831 {
1832 uint32_t current_opcode;
1833 target_read_u32(target, current_pc, &current_opcode);
1834 LOG_ERROR("Couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32 "", current_opcode);
1835 return retval;
1836 }
1837
1838 LOG_DEBUG("enable single-step");
1839 arm7_9->enable_single_step(target, next_pc);
1840
1841 target->debug_reason = DBG_REASON_SINGLESTEP;
1842
1843 if ((retval = arm7_9_restore_context(target)) != ERROR_OK)
1844 {
1845 return retval;
1846 }
1847
1848 if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1849 arm7_9->branch_resume(target);
1850 else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1851 {
1852 arm7_9->branch_resume_thumb(target);
1853 }
1854 else
1855 {
1856 LOG_ERROR("unhandled core state");
1857 return ERROR_FAIL;
1858 }
1859
1860 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
1861 embeddedice_write_reg(dbg_ctrl, buf_get_u32(dbg_ctrl->value, 0, dbg_ctrl->size));
1862 err = arm7_9_execute_sys_speed(target);
1863
1864 LOG_DEBUG("disable single-step");
1865 arm7_9->disable_single_step(target);
1866
1867 if (err != ERROR_OK)
1868 {
1869 if ((retval = arm7_9_set_breakpoint(target, breakpoint)) != ERROR_OK)
1870 {
1871 return retval;
1872 }
1873 target->state = TARGET_UNKNOWN;
1874 return err;
1875 }
1876
1877 arm7_9_debug_entry(target);
1878 LOG_DEBUG("new PC after step: 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1879
1880 LOG_DEBUG("set breakpoint at 0x%8.8" PRIx32 "", breakpoint->address);
1881 if ((retval = arm7_9_set_breakpoint(target, breakpoint)) != ERROR_OK)
1882 {
1883 return retval;
1884 }
1885 }
1886 }
1887
1888 /* enable any pending breakpoints and watchpoints */
1889 arm7_9_enable_breakpoints(target);
1890 arm7_9_enable_watchpoints(target);
1891
1892 if ((retval = arm7_9_restore_context(target)) != ERROR_OK)
1893 {
1894 return retval;
1895 }
1896
1897 if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1898 {
1899 arm7_9->branch_resume(target);
1900 }
1901 else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1902 {
1903 arm7_9->branch_resume_thumb(target);
1904 }
1905 else
1906 {
1907 LOG_ERROR("unhandled core state");
1908 return ERROR_FAIL;
1909 }
1910
1911 /* deassert DBGACK and INTDIS */
1912 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
1913 /* INTDIS only when we really resume, not during debug execution */
1914 if (!debug_execution)
1915 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 0);
1916 embeddedice_write_reg(dbg_ctrl, buf_get_u32(dbg_ctrl->value, 0, dbg_ctrl->size));
1917
1918 if ((retval = arm7_9_restart_core(target)) != ERROR_OK)
1919 {
1920 return retval;
1921 }
1922
1923 target->debug_reason = DBG_REASON_NOTHALTED;
1924
1925 if (!debug_execution)
1926 {
1927 /* registers are now invalid */
1928 register_cache_invalidate(armv4_5->core_cache);
1929 target->state = TARGET_RUNNING;
1930 if ((retval = target_call_event_callbacks(target, TARGET_EVENT_RESUMED)) != ERROR_OK)
1931 {
1932 return retval;
1933 }
1934 }
1935 else
1936 {
1937 target->state = TARGET_DEBUG_RUNNING;
1938 if ((retval = target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED)) != ERROR_OK)
1939 {
1940 return retval;
1941 }
1942 }
1943
1944 LOG_DEBUG("target resumed");
1945
1946 return ERROR_OK;
1947 }
1948
1949 void arm7_9_enable_eice_step(struct target *target, uint32_t next_pc)
1950 {
1951 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
1952 struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
1953 uint32_t current_pc;
1954 current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
1955
1956 if (next_pc != current_pc)
1957 {
1958 /* setup an inverse breakpoint on the current PC
1959 * - comparator 1 matches the current address
1960 * - rangeout from comparator 1 is connected to comparator 0 rangein
1961 * - comparator 0 matches any address, as long as rangein is low */
1962 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
1963 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
1964 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
1965 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~(EICE_W_CTRL_RANGE | EICE_W_CTRL_nOPC) & 0xff);
1966 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], current_pc);
1967 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0);
1968 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffff);
1969 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
1970 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
1971 }
1972 else
1973 {
1974 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
1975 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
1976 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
1977 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xff);
1978 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], next_pc);
1979 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0);
1980 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffff);
1981 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
1982 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
1983 }
1984 }
1985
1986 void arm7_9_disable_eice_step(struct target *target)
1987 {
1988 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
1989
1990 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
1991 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);
1992 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]);
1993 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK]);
1994 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE]);
1995 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK]);
1996 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK]);
1997 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK]);
1998 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE]);
1999 }
2000
2001 int arm7_9_step(struct target *target, int current, uint32_t address, int handle_breakpoints)
2002 {
2003 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2004 struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
2005 struct breakpoint *breakpoint = NULL;
2006 int err, retval;
2007
2008 if (target->state != TARGET_HALTED)
2009 {
2010 LOG_WARNING("target not halted");
2011 return ERROR_TARGET_NOT_HALTED;
2012 }
2013
2014 /* current = 1: continue on current pc, otherwise continue at <address> */
2015 if (!current)
2016 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
2017
2018 uint32_t current_pc;
2019 current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
2020
2021 /* the front-end may request us not to handle breakpoints */
2022 if (handle_breakpoints)
2023 if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
2024 if ((retval = arm7_9_unset_breakpoint(target, breakpoint)) != ERROR_OK)
2025 {
2026 return retval;
2027 }
2028
2029 target->debug_reason = DBG_REASON_SINGLESTEP;
2030
2031 /* calculate PC of next instruction */
2032 uint32_t next_pc;
2033 if ((retval = arm_simulate_step(target, &next_pc)) != ERROR_OK)
2034 {
2035 uint32_t current_opcode;
2036 target_read_u32(target, current_pc, &current_opcode);
2037 LOG_ERROR("Couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32 "", current_opcode);
2038 return retval;
2039 }
2040
2041 if ((retval = arm7_9_restore_context(target)) != ERROR_OK)
2042 {
2043 return retval;
2044 }
2045
2046 arm7_9->enable_single_step(target, next_pc);
2047
2048 if (armv4_5->core_state == ARMV4_5_STATE_ARM)
2049 {
2050 arm7_9->branch_resume(target);
2051 }
2052 else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
2053 {
2054 arm7_9->branch_resume_thumb(target);
2055 }
2056 else
2057 {
2058 LOG_ERROR("unhandled core state");
2059 return ERROR_FAIL;
2060 }
2061
2062 if ((retval = target_call_event_callbacks(target, TARGET_EVENT_RESUMED)) != ERROR_OK)
2063 {
2064 return retval;
2065 }
2066
2067 err = arm7_9_execute_sys_speed(target);
2068 arm7_9->disable_single_step(target);
2069
2070 /* registers are now invalid */
2071 register_cache_invalidate(armv4_5->core_cache);
2072
2073 if (err != ERROR_OK)
2074 {
2075 target->state = TARGET_UNKNOWN;
2076 } else {
2077 arm7_9_debug_entry(target);
2078 if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
2079 {
2080 return retval;
2081 }
2082 LOG_DEBUG("target stepped");
2083 }
2084
2085 if (breakpoint)
2086 if ((retval = arm7_9_set_breakpoint(target, breakpoint)) != ERROR_OK)
2087 {
2088 return retval;
2089 }
2090
2091 return err;
2092 }
2093
2094 static int arm7_9_read_core_reg(struct target *target, struct reg *r,
2095 int num, enum armv4_5_mode mode)
2096 {
2097 uint32_t* reg_p[16];
2098 uint32_t value;
2099 int retval;
2100 struct arm_reg *areg = r->arch_info;
2101 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2102 struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
2103
2104 if (!is_arm_mode(armv4_5->core_mode))
2105 return ERROR_FAIL;
2106 if ((num < 0) || (num > 16))
2107 return ERROR_INVALID_ARGUMENTS;
2108
2109 if ((mode != ARMV4_5_MODE_ANY)
2110 && (mode != armv4_5->core_mode)
2111 && (areg->mode != ARMV4_5_MODE_ANY))
2112 {
2113 uint32_t tmp_cpsr;
2114
2115 /* change processor mode (mask T bit) */
2116 tmp_cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 8) & 0xE0;
2117 tmp_cpsr |= mode;
2118 tmp_cpsr &= ~0x20;
2119 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
2120 }
2121
2122 if ((num >= 0) && (num <= 15))
2123 {
2124 /* read a normal core register */
2125 reg_p[num] = &value;
2126
2127 arm7_9->read_core_regs(target, 1 << num, reg_p);
2128 }
2129 else
2130 {
2131 /* read a program status register
2132 * if the register mode is MODE_ANY, we read the cpsr, otherwise a spsr
2133 */
2134 arm7_9->read_xpsr(target, &value, areg->mode != ARMV4_5_MODE_ANY);
2135 }
2136
2137 if ((retval = jtag_execute_queue()) != ERROR_OK)
2138 {
2139 return retval;
2140 }
2141
2142 r->valid = 1;
2143 r->dirty = 0;
2144 buf_set_u32(r->value, 0, 32, value);
2145
2146 if ((mode != ARMV4_5_MODE_ANY)
2147 && (mode != armv4_5->core_mode)
2148 && (areg->mode != ARMV4_5_MODE_ANY)) {
2149 /* restore processor mode (mask T bit) */
2150 arm7_9->write_xpsr_im8(target,
2151 buf_get_u32(armv4_5->cpsr->value, 0, 8)
2152 & ~0x20, 0, 0);
2153 }
2154
2155 return ERROR_OK;
2156 }
2157
2158 static int arm7_9_write_core_reg(struct target *target, struct reg *r,
2159 int num, enum armv4_5_mode mode, uint32_t value)
2160 {
2161 uint32_t reg[16];
2162 struct arm_reg *areg = r->arch_info;
2163 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2164 struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
2165
2166 if (!is_arm_mode(armv4_5->core_mode))
2167 return ERROR_FAIL;
2168 if ((num < 0) || (num > 16))
2169 return ERROR_INVALID_ARGUMENTS;
2170
2171 if ((mode != ARMV4_5_MODE_ANY)
2172 && (mode != armv4_5->core_mode)
2173 && (areg->mode != ARMV4_5_MODE_ANY)) {
2174 uint32_t tmp_cpsr;
2175
2176 /* change processor mode (mask T bit) */
2177 tmp_cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 8) & 0xE0;
2178 tmp_cpsr |= mode;
2179 tmp_cpsr &= ~0x20;
2180 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
2181 }
2182
2183 if ((num >= 0) && (num <= 15))
2184 {
2185 /* write a normal core register */
2186 reg[num] = value;
2187
2188 arm7_9->write_core_regs(target, 1 << num, reg);
2189 }
2190 else
2191 {
2192 /* write a program status register
2193 * if the register mode is MODE_ANY, we write the cpsr, otherwise a spsr
2194 */
2195 int spsr = (areg->mode != ARMV4_5_MODE_ANY);
2196
2197 /* if we're writing the CPSR, mask the T bit */
2198 if (!spsr)
2199 value &= ~0x20;
2200
2201 arm7_9->write_xpsr(target, value, spsr);
2202 }
2203
2204 r->valid = 1;
2205 r->dirty = 0;
2206
2207 if ((mode != ARMV4_5_MODE_ANY)
2208 && (mode != armv4_5->core_mode)
2209 && (areg->mode != ARMV4_5_MODE_ANY)) {
2210 /* restore processor mode (mask T bit) */
2211 arm7_9->write_xpsr_im8(target,
2212 buf_get_u32(armv4_5->cpsr->value, 0, 8)
2213 & ~0x20, 0, 0);
2214 }
2215
2216 return jtag_execute_queue();
2217 }
2218
2219 int arm7_9_read_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
2220 {
2221 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2222 struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
2223 uint32_t reg[16];
2224 uint32_t num_accesses = 0;
2225 int thisrun_accesses;
2226 int i;
2227 uint32_t cpsr;
2228 int retval;
2229 int last_reg = 0;
2230
2231 LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "", address, size, count);
2232
2233 if (target->state != TARGET_HALTED)
2234 {
2235 LOG_WARNING("target not halted");
2236 return ERROR_TARGET_NOT_HALTED;
2237 }
2238
2239 /* sanitize arguments */
2240 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
2241 return ERROR_INVALID_ARGUMENTS;
2242
2243 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
2244 return ERROR_TARGET_UNALIGNED_ACCESS;
2245
2246 /* load the base register with the address of the first word */
2247 reg[0] = address;
2248 arm7_9->write_core_regs(target, 0x1, reg);
2249
2250 int j = 0;
2251
2252 switch (size)
2253 {
2254 case 4:
2255 while (num_accesses < count)
2256 {
2257 uint32_t reg_list;
2258 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
2259 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2260
2261 if (last_reg <= thisrun_accesses)
2262 last_reg = thisrun_accesses;
2263
2264 arm7_9->load_word_regs(target, reg_list);
2265
2266 /* fast memory reads are only safe when the target is running
2267 * from a sufficiently high clock (32 kHz is usually too slow)
2268 */
2269 if (arm7_9->fast_memory_access)
2270 retval = arm7_9_execute_fast_sys_speed(target);
2271 else
2272 retval = arm7_9_execute_sys_speed(target);
2273 if (retval != ERROR_OK)
2274 return retval;
2275
2276 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 4);
2277
2278 /* advance buffer, count number of accesses */
2279 buffer += thisrun_accesses * 4;
2280 num_accesses += thisrun_accesses;
2281
2282 if ((j++%1024) == 0)
2283 {
2284 keep_alive();
2285 }
2286 }
2287 break;
2288 case 2:
2289 while (num_accesses < count)
2290 {
2291 uint32_t reg_list;
2292 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
2293 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2294
2295 for (i = 1; i <= thisrun_accesses; i++)
2296 {
2297 if (i > last_reg)
2298 last_reg = i;
2299 arm7_9->load_hword_reg(target, i);
2300 /* fast memory reads are only safe when the target is running
2301 * from a sufficiently high clock (32 kHz is usually too slow)
2302 */
2303 if (arm7_9->fast_memory_access)
2304 retval = arm7_9_execute_fast_sys_speed(target);
2305 else
2306 retval = arm7_9_execute_sys_speed(target);
2307 if (retval != ERROR_OK)
2308 {
2309 return retval;
2310 }
2311
2312 }
2313
2314 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 2);
2315
2316 /* advance buffer, count number of accesses */
2317 buffer += thisrun_accesses * 2;
2318 num_accesses += thisrun_accesses;
2319
2320 if ((j++%1024) == 0)
2321 {
2322 keep_alive();
2323 }
2324 }
2325 break;
2326 case 1:
2327 while (num_accesses < count)
2328 {
2329 uint32_t reg_list;
2330 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
2331 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2332
2333 for (i = 1; i <= thisrun_accesses; i++)
2334 {
2335 if (i > last_reg)
2336 last_reg = i;
2337 arm7_9->load_byte_reg(target, i);
2338 /* fast memory reads are only safe when the target is running
2339 * from a sufficiently high clock (32 kHz is usually too slow)
2340 */
2341 if (arm7_9->fast_memory_access)
2342 retval = arm7_9_execute_fast_sys_speed(target);
2343 else
2344 retval = arm7_9_execute_sys_speed(target);
2345 if (retval != ERROR_OK)
2346 {
2347 return retval;
2348 }
2349 }
2350
2351 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 1);
2352
2353 /* advance buffer, count number of accesses */
2354 buffer += thisrun_accesses * 1;
2355 num_accesses += thisrun_accesses;
2356
2357 if ((j++%1024) == 0)
2358 {
2359 keep_alive();
2360 }
2361 }
2362 break;
2363 default:
2364 LOG_ERROR("BUG: we shouldn't get here");
2365 exit(-1);
2366 break;
2367 }
2368
2369 if (!is_arm_mode(armv4_5->core_mode))
2370 return ERROR_FAIL;
2371
2372 for (i = 0; i <= last_reg; i++)
2373 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid;
2374
2375 arm7_9->read_xpsr(target, &cpsr, 0);
2376 if ((retval = jtag_execute_queue()) != ERROR_OK)
2377 {
2378 LOG_ERROR("JTAG error while reading cpsr");
2379 return ERROR_TARGET_DATA_ABORT;
2380 }
2381
2382 if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))
2383 {
2384 LOG_WARNING("memory read caused data abort (address: 0x%8.8" PRIx32 ", size: 0x%" PRIx32 ", count: 0x%" PRIx32 ")", address, size, count);
2385
2386 arm7_9->write_xpsr_im8(target,
2387 buf_get_u32(armv4_5->cpsr->value, 0, 8)
2388 & ~0x20, 0, 0);
2389
2390 return ERROR_TARGET_DATA_ABORT;
2391 }
2392
2393 return ERROR_OK;
2394 }
2395
2396 int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
2397 {
2398 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2399 struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
2400 struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
2401
2402 uint32_t reg[16];
2403 uint32_t num_accesses = 0;
2404 int thisrun_accesses;
2405 int i;
2406 uint32_t cpsr;
2407 int retval;
2408 int last_reg = 0;
2409
2410 #ifdef _DEBUG_ARM7_9_
2411 LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
2412 #endif
2413
2414 if (target->state != TARGET_HALTED)
2415 {
2416 LOG_WARNING("target not halted");
2417 return ERROR_TARGET_NOT_HALTED;
2418 }
2419
2420 /* sanitize arguments */
2421 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
2422 return ERROR_INVALID_ARGUMENTS;
2423
2424 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
2425 return ERROR_TARGET_UNALIGNED_ACCESS;
2426
2427 /* load the base register with the address of the first word */
2428 reg[0] = address;
2429 arm7_9->write_core_regs(target, 0x1, reg);
2430
2431 /* Clear DBGACK, to make sure memory fetches work as expected */
2432 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
2433 embeddedice_store_reg(dbg_ctrl);
2434
2435 switch (size)
2436 {
2437 case 4:
2438 while (num_accesses < count)
2439 {
2440 uint32_t reg_list;
2441 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
2442 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2443
2444 for (i = 1; i <= thisrun_accesses; i++)
2445 {
2446 if (i > last_reg)
2447 last_reg = i;
2448 reg[i] = target_buffer_get_u32(target, buffer);
2449 buffer += 4;
2450 }
2451
2452 arm7_9->write_core_regs(target, reg_list, reg);
2453
2454 arm7_9->store_word_regs(target, reg_list);
2455
2456 /* fast memory writes are only safe when the target is running
2457 * from a sufficiently high clock (32 kHz is usually too slow)
2458 */
2459 if (arm7_9->fast_memory_access)
2460 retval = arm7_9_execute_fast_sys_speed(target);
2461 else
2462 retval = arm7_9_execute_sys_speed(target);
2463 if (retval != ERROR_OK)
2464 {
2465 return retval;
2466 }
2467
2468 num_accesses += thisrun_accesses;
2469 }
2470 break;
2471 case 2:
2472 while (num_accesses < count)
2473 {
2474 uint32_t reg_list;
2475 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
2476 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2477
2478 for (i = 1; i <= thisrun_accesses; i++)
2479 {
2480 if (i > last_reg)
2481 last_reg = i;
2482 reg[i] = target_buffer_get_u16(target, buffer) & 0xffff;
2483 buffer += 2;
2484 }
2485
2486 arm7_9->write_core_regs(target, reg_list, reg);
2487
2488 for (i = 1; i <= thisrun_accesses; i++)
2489 {
2490 arm7_9->store_hword_reg(target, i);
2491
2492 /* fast memory writes are only safe when the target is running
2493 * from a sufficiently high clock (32 kHz is usually too slow)
2494 */
2495 if (arm7_9->fast_memory_access)
2496 retval = arm7_9_execute_fast_sys_speed(target);
2497 else
2498 retval = arm7_9_execute_sys_speed(target);
2499 if (retval != ERROR_OK)
2500 {
2501 return retval;
2502 }
2503 }
2504
2505 num_accesses += thisrun_accesses;
2506 }
2507 break;
2508 case 1:
2509 while (num_accesses < count)
2510 {
2511 uint32_t reg_list;
2512 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
2513 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2514
2515 for (i = 1; i <= thisrun_accesses; i++)
2516 {
2517 if (i > last_reg)
2518 last_reg = i;
2519 reg[i] = *buffer++ & 0xff;
2520 }
2521
2522 arm7_9->write_core_regs(target, reg_list, reg);
2523
2524 for (i = 1; i <= thisrun_accesses; i++)
2525 {
2526 arm7_9->store_byte_reg(target, i);
2527 /* fast memory writes are only safe when the target is running
2528 * from a sufficiently high clock (32 kHz is usually too slow)
2529 */
2530 if (arm7_9->fast_memory_access)
2531 retval = arm7_9_execute_fast_sys_speed(target);
2532 else
2533 retval = arm7_9_execute_sys_speed(target);
2534 if (retval != ERROR_OK)
2535 {
2536 return retval;
2537 }
2538
2539 }
2540
2541 num_accesses += thisrun_accesses;
2542 }
2543 break;
2544 default:
2545 LOG_ERROR("BUG: we shouldn't get here");
2546 exit(-1);
2547 break;
2548 }
2549
2550 /* Re-Set DBGACK */
2551 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
2552 embeddedice_store_reg(dbg_ctrl);
2553
2554 if (!is_arm_mode(armv4_5->core_mode))
2555 return ERROR_FAIL;
2556
2557 for (i = 0; i <= last_reg; i++)
2558 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid;
2559
2560 arm7_9->read_xpsr(target, &cpsr, 0);
2561 if ((retval = jtag_execute_queue()) != ERROR_OK)
2562 {
2563 LOG_ERROR("JTAG error while reading cpsr");
2564 return ERROR_TARGET_DATA_ABORT;
2565 }
2566
2567 if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))
2568 {
2569 LOG_WARNING("memory write caused data abort (address: 0x%8.8" PRIx32 ", size: 0x%" PRIx32 ", count: 0x%" PRIx32 ")", address, size, count);
2570
2571 arm7_9->write_xpsr_im8(target,
2572 buf_get_u32(armv4_5->cpsr->value, 0, 8)
2573 & ~0x20, 0, 0);
2574
2575 return ERROR_TARGET_DATA_ABORT;
2576 }
2577
2578 return ERROR_OK;
2579 }
2580
2581 static int dcc_count;
2582 static uint8_t *dcc_buffer;
2583
2584 static int arm7_9_dcc_completion(struct target *target, uint32_t exit_point, int timeout_ms, void *arch_info)
2585 {
2586 int retval = ERROR_OK;
2587 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2588
2589 if ((retval = target_wait_state(target, TARGET_DEBUG_RUNNING, 500)) != ERROR_OK)
2590 return retval;
2591
2592 int little = target->endianness == TARGET_LITTLE_ENDIAN;
2593 int count = dcc_count;
2594 uint8_t *buffer = dcc_buffer;
2595 if (count > 2)
2596 {
2597 /* Handle first & last using standard embeddedice_write_reg and the middle ones w/the
2598 * core function repeated. */
2599 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
2600 buffer += 4;
2601
2602 struct embeddedice_reg *ice_reg = arm7_9->eice_cache->reg_list[EICE_COMMS_DATA].arch_info;
2603 uint8_t reg_addr = ice_reg->addr & 0x1f;
2604 struct jtag_tap *tap;
2605 tap = ice_reg->jtag_info->tap;
2606
2607 embeddedice_write_dcc(tap, reg_addr, buffer, little, count-2);
2608 buffer += (count-2)*4;
2609
2610 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
2611 } else
2612 {
2613 int i;
2614 for (i = 0; i < count; i++)
2615 {
2616 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
2617 buffer += 4;
2618 }
2619 }
2620
2621 if ((retval = target_halt(target))!= ERROR_OK)
2622 {
2623 return retval;
2624 }
2625 return target_wait_state(target, TARGET_HALTED, 500);
2626 }
2627
2628 static const uint32_t dcc_code[] =
2629 {
2630 /* r0 == input, points to memory buffer
2631 * r1 == scratch
2632 */
2633
2634 /* spin until DCC control (c0) reports data arrived */
2635 0xee101e10, /* w: mrc p14, #0, r1, c0, c0 */
2636 0xe3110001, /* tst r1, #1 */
2637 0x0afffffc, /* bne w */
2638
2639 /* read word from DCC (c1), write to memory */
2640 0xee111e10, /* mrc p14, #0, r1, c1, c0 */
2641 0xe4801004, /* str r1, [r0], #4 */
2642
2643 /* repeat */
2644 0xeafffff9 /* b w */
2645 };
2646
2647 int armv4_5_run_algorithm_inner(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info, int (*run_it)(struct target *target, uint32_t exit_point, int timeout_ms, void *arch_info));
2648
2649 int arm7_9_bulk_write_memory(struct target *target, uint32_t address, uint32_t count, uint8_t *buffer)
2650 {
2651 int retval;
2652 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2653 int i;
2654
2655 if (!arm7_9->dcc_downloads)
2656 return target_write_memory(target, address, 4, count, buffer);
2657
2658 /* regrab previously allocated working_area, or allocate a new one */
2659 if (!arm7_9->dcc_working_area)
2660 {
2661 uint8_t dcc_code_buf[6 * 4];
2662
2663 /* make sure we have a working area */
2664 if (target_alloc_working_area(target, 24, &arm7_9->dcc_working_area) != ERROR_OK)
2665 {
2666 LOG_INFO("no working area available, falling back to memory writes");
2667 return target_write_memory(target, address, 4, count, buffer);
2668 }
2669
2670 /* copy target instructions to target endianness */
2671 for (i = 0; i < 6; i++)
2672 {
2673 target_buffer_set_u32(target, dcc_code_buf + i*4, dcc_code[i]);
2674 }
2675
2676 /* write DCC code to working area */
2677 if ((retval = target_write_memory(target, arm7_9->dcc_working_area->address, 4, 6, dcc_code_buf)) != ERROR_OK)
2678 {
2679 return retval;
2680 }
2681 }
2682
2683 struct armv4_5_algorithm armv4_5_info;
2684 struct reg_param reg_params[1];
2685
2686 armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
2687 armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
2688 armv4_5_info.core_state = ARMV4_5_STATE_ARM;
2689
2690 init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT);
2691
2692 buf_set_u32(reg_params[0].value, 0, 32, address);
2693
2694 dcc_count = count;
2695 dcc_buffer = buffer;
2696 retval = armv4_5_run_algorithm_inner(target, 0, NULL, 1, reg_params,
2697 arm7_9->dcc_working_area->address, arm7_9->dcc_working_area->address + 6*4, 20*1000, &armv4_5_info, arm7_9_dcc_completion);
2698
2699 if (retval == ERROR_OK)
2700 {
2701 uint32_t endaddress = buf_get_u32(reg_params[0].value, 0, 32);
2702 if (endaddress != (address + count*4))
2703 {
2704 LOG_ERROR("DCC write failed, expected end address 0x%08" PRIx32 " got 0x%0" PRIx32 "", (address + count*4), endaddress);
2705 retval = ERROR_FAIL;
2706 }
2707 }
2708
2709 destroy_reg_param(&reg_params[0]);
2710
2711 return retval;
2712 }
2713
2714 /**
2715 * Perform per-target setup that requires JTAG access.
2716 */
2717 int arm7_9_examine(struct target *target)
2718 {
2719 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2720 int retval;
2721
2722 if (!target_was_examined(target)) {
2723 struct reg_cache *t, **cache_p;
2724
2725 t = embeddedice_build_reg_cache(target, arm7_9);
2726 if (t == NULL)
2727 return ERROR_FAIL;
2728
2729 cache_p = register_get_last_cache_p(&target->reg_cache);
2730 (*cache_p) = t;
2731 arm7_9->eice_cache = (*cache_p);
2732
2733 if (arm7_9->armv4_5_common.etm)
2734 (*cache_p)->next = etm_build_reg_cache(target,
2735 &arm7_9->jtag_info,
2736 arm7_9->armv4_5_common.etm);
2737
2738 target_set_examined(target);
2739 }
2740
2741 retval = embeddedice_setup(target);
2742 if (retval == ERROR_OK)
2743 retval = arm7_9_setup(target);
2744 if (retval == ERROR_OK && arm7_9->armv4_5_common.etm)
2745 retval = etm_setup(target);
2746 return retval;
2747 }
2748
2749 COMMAND_HANDLER(handle_arm7_9_dbgrq_command)
2750 {
2751 struct target *target = get_current_target(CMD_CTX);
2752 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2753
2754 if (!is_arm7_9(arm7_9))
2755 {
2756 command_print(CMD_CTX, "current target isn't an ARM7/ARM9 target");
2757 return ERROR_TARGET_INVALID;
2758 }
2759
2760 if (CMD_ARGC > 0)
2761 COMMAND_PARSE_ENABLE(CMD_ARGV[0],arm7_9->use_dbgrq);
2762
2763 command_print(CMD_CTX, "use of EmbeddedICE dbgrq instead of breakpoint for target halt %s", (arm7_9->use_dbgrq) ? "enabled" : "disabled");
2764
2765 return ERROR_OK;
2766 }
2767
2768 COMMAND_HANDLER(handle_arm7_9_fast_memory_access_command)
2769 {
2770 struct target *target = get_current_target(CMD_CTX);
2771 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2772
2773 if (!is_arm7_9(arm7_9))
2774 {
2775 command_print(CMD_CTX, "current target isn't an ARM7/ARM9 target");
2776 return ERROR_TARGET_INVALID;
2777 }
2778
2779 if (CMD_ARGC > 0)
2780 COMMAND_PARSE_ENABLE(CMD_ARGV[0], arm7_9->fast_memory_access);
2781
2782 command_print(CMD_CTX, "fast memory access is %s", (arm7_9->fast_memory_access) ? "enabled" : "disabled");
2783
2784 return ERROR_OK;
2785 }
2786
2787 COMMAND_HANDLER(handle_arm7_9_dcc_downloads_command)
2788 {
2789 struct target *target = get_current_target(CMD_CTX);
2790 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2791
2792 if (!is_arm7_9(arm7_9))
2793 {
2794 command_print(CMD_CTX, "current target isn't an ARM7/ARM9 target");
2795 return ERROR_TARGET_INVALID;
2796 }
2797
2798 if (CMD_ARGC > 0)
2799 COMMAND_PARSE_ENABLE(CMD_ARGV[0], arm7_9->dcc_downloads);
2800
2801 command_print(CMD_CTX, "dcc downloads are %s", (arm7_9->dcc_downloads) ? "enabled" : "disabled");
2802
2803 return ERROR_OK;
2804 }
2805
2806 int arm7_9_init_arch_info(struct target *target, struct arm7_9_common *arm7_9)
2807 {
2808 int retval = ERROR_OK;
2809 struct arm *armv4_5 = &arm7_9->armv4_5_common;
2810
2811 arm7_9->common_magic = ARM7_9_COMMON_MAGIC;
2812
2813 if ((retval = arm_jtag_setup_connection(&arm7_9->jtag_info)) != ERROR_OK)
2814 return retval;
2815
2816 /* caller must have allocated via calloc(), so everything's zeroed */
2817
2818 arm7_9->wp_available_max = 2;
2819
2820 arm7_9->fast_memory_access = false;
2821 arm7_9->dcc_downloads = false;
2822
2823 armv4_5->arch_info = arm7_9;
2824 armv4_5->read_core_reg = arm7_9_read_core_reg;
2825 armv4_5->write_core_reg = arm7_9_write_core_reg;
2826 armv4_5->full_context = arm7_9_full_context;
2827
2828 if ((retval = armv4_5_init_arch_info(target, armv4_5)) != ERROR_OK)
2829 return retval;
2830
2831 return target_register_timer_callback(arm7_9_handle_target_request,
2832 1, 1, target);
2833 }
2834
2835 int arm7_9_register_commands(struct command_context *cmd_ctx)
2836 {
2837 struct command *arm7_9_cmd;
2838
2839 arm7_9_cmd = register_command(cmd_ctx, NULL, "arm7_9",
2840 NULL, COMMAND_ANY, "arm7/9 specific commands");
2841
2842 register_command(cmd_ctx, arm7_9_cmd, "dbgrq",
2843 handle_arm7_9_dbgrq_command, COMMAND_ANY,
2844 "use EmbeddedICE dbgrq instead of breakpoint "
2845 "for target halt requests <enable | disable>");
2846 register_command(cmd_ctx, arm7_9_cmd, "fast_memory_access",
2847 handle_arm7_9_fast_memory_access_command, COMMAND_ANY,
2848 "use fast memory accesses instead of slower "
2849 "but potentially safer accesses <enable | disable>");
2850 register_command(cmd_ctx, arm7_9_cmd, "dcc_downloads",
2851 handle_arm7_9_dcc_downloads_command, COMMAND_ANY,
2852 "use DCC downloads for larger memory writes <enable | disable>");
2853
2854 armv4_5_register_commands(cmd_ctx);
2855
2856 etm_register_commands(cmd_ctx);
2857
2858 return ERROR_OK;
2859 }