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- renamed M5960 USB JTAG to "flyswatter"
[openocd.git] / src / target / arm7_9_common.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
20 #ifdef HAVE_CONFIG_H
21 #include "config.h"
22 #endif
23
24 #include "replacements.h"
25
26 #include "embeddedice.h"
27 #include "target.h"
28 #include "target_request.h"
29 #include "armv4_5.h"
30 #include "arm_jtag.h"
31 #include "jtag.h"
32 #include "log.h"
33 #include "arm7_9_common.h"
34 #include "breakpoints.h"
35
36 #include <stdlib.h>
37 #include <string.h>
38 #include <unistd.h>
39
40 #include <sys/types.h>
41 #include <sys/stat.h>
42 #include <sys/time.h>
43 #include <errno.h>
44
45 int arm7_9_debug_entry(target_t *target);
46 int arm7_9_enable_sw_bkpts(struct target_s *target);
47
48 /* command handler forward declarations */
49 int handle_arm7_9_write_xpsr_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
50 int handle_arm7_9_write_xpsr_im8_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
51 int handle_arm7_9_read_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
52 int handle_arm7_9_write_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
53 int handle_arm7_9_sw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
54 int handle_arm7_9_force_hw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
55 int handle_arm7_9_dbgrq_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
56 int handle_arm7_9_fast_memory_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
57 int handle_arm7_9_dcc_downloads_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
58 int handle_arm7_9_etm_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
59
60 int arm7_9_reinit_embeddedice(target_t *target)
61 {
62 armv4_5_common_t *armv4_5 = target->arch_info;
63 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
64
65 breakpoint_t *breakpoint = target->breakpoints;
66
67 arm7_9->wp_available = 2;
68 arm7_9->wp0_used = 0;
69 arm7_9->wp1_used = 0;
70
71 /* mark all hardware breakpoints as unset */
72 while (breakpoint)
73 {
74 if (breakpoint->type == BKPT_HARD)
75 {
76 breakpoint->set = 0;
77 }
78 breakpoint = breakpoint->next;
79 }
80
81 if (arm7_9->sw_bkpts_enabled && arm7_9->sw_bkpts_use_wp)
82 {
83 arm7_9->sw_bkpts_enabled = 0;
84 arm7_9_enable_sw_bkpts(target);
85 }
86
87 arm7_9->reinit_embeddedice = 0;
88
89 return ERROR_OK;
90 }
91
92 int arm7_9_jtag_callback(enum jtag_event event, void *priv)
93 {
94 target_t *target = priv;
95 armv4_5_common_t *armv4_5 = target->arch_info;
96 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
97
98 /* a test-logic reset occured
99 * the EmbeddedICE registers have been reset
100 * hardware breakpoints have been cleared
101 */
102 if (event == JTAG_TRST_ASSERTED)
103 {
104 arm7_9->reinit_embeddedice = 1;
105 }
106
107 return ERROR_OK;
108 }
109
110 int arm7_9_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p)
111 {
112 armv4_5_common_t *armv4_5 = target->arch_info;
113 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
114
115 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
116 {
117 return -1;
118 }
119
120 if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
121 {
122 return -1;
123 }
124
125 *armv4_5_p = armv4_5;
126 *arm7_9_p = arm7_9;
127
128 return ERROR_OK;
129 }
130
131 int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
132 {
133 armv4_5_common_t *armv4_5 = target->arch_info;
134 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
135
136 if (target->state != TARGET_HALTED)
137 {
138 WARNING("target not halted");
139 return ERROR_TARGET_NOT_HALTED;
140 }
141
142 if (arm7_9->force_hw_bkpts)
143 breakpoint->type = BKPT_HARD;
144
145 if (breakpoint->set)
146 {
147 WARNING("breakpoint already set");
148 return ERROR_OK;
149 }
150
151 if (breakpoint->type == BKPT_HARD)
152 {
153 /* either an ARM (4 byte) or Thumb (2 byte) breakpoint */
154 u32 mask = (breakpoint->length == 4) ? 0x3u : 0x1u;
155 if (!arm7_9->wp0_used)
156 {
157 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], breakpoint->address);
158 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask);
159 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffffu);
160 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
161 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
162
163 jtag_execute_queue();
164 arm7_9->wp0_used = 1;
165 breakpoint->set = 1;
166 }
167 else if (!arm7_9->wp1_used)
168 {
169 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], breakpoint->address);
170 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask);
171 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffffu);
172 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
173 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
174
175 jtag_execute_queue();
176 arm7_9->wp1_used = 1;
177 breakpoint->set = 2;
178 }
179 else
180 {
181 ERROR("BUG: no hardware comparator available");
182 return ERROR_OK;
183 }
184 }
185 else if (breakpoint->type == BKPT_SOFT)
186 {
187 if (breakpoint->length == 4)
188 {
189 /* keep the original instruction in target endianness */
190 target->type->read_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr);
191 /* write the breakpoint instruction in target endianness (arm7_9->arm_bkpt is host endian) */
192 target_write_u32(target, breakpoint->address, arm7_9->arm_bkpt);
193 }
194 else
195 {
196 /* keep the original instruction in target endianness */
197 target->type->read_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr);
198 /* write the breakpoint instruction in target endianness (arm7_9->thumb_bkpt is host endian) */
199 target_write_u16(target, breakpoint->address, arm7_9->thumb_bkpt);
200 }
201 breakpoint->set = 1;
202 }
203
204 return ERROR_OK;
205
206 }
207
208 int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
209 {
210 armv4_5_common_t *armv4_5 = target->arch_info;
211 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
212
213 if (target->state != TARGET_HALTED)
214 {
215 WARNING("target not halted");
216 return ERROR_TARGET_NOT_HALTED;
217 }
218
219 if (!breakpoint->set)
220 {
221 WARNING("breakpoint not set");
222 return ERROR_OK;
223 }
224
225 if (breakpoint->type == BKPT_HARD)
226 {
227 if (breakpoint->set == 1)
228 {
229 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
230 jtag_execute_queue();
231 arm7_9->wp0_used = 0;
232 }
233 else if (breakpoint->set == 2)
234 {
235 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
236 jtag_execute_queue();
237 arm7_9->wp1_used = 0;
238 }
239 breakpoint->set = 0;
240 }
241 else
242 {
243 /* restore original instruction (kept in target endianness) */
244 if (breakpoint->length == 4)
245 {
246 target->type->write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr);
247 }
248 else
249 {
250 target->type->write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr);
251 }
252 breakpoint->set = 0;
253 }
254
255 return ERROR_OK;
256 }
257
258 int arm7_9_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
259 {
260 armv4_5_common_t *armv4_5 = target->arch_info;
261 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
262
263 if (target->state != TARGET_HALTED)
264 {
265 WARNING("target not halted");
266 return ERROR_TARGET_NOT_HALTED;
267 }
268
269 if (arm7_9->force_hw_bkpts)
270 {
271 DEBUG("forcing use of hardware breakpoint at address 0x%8.8x", breakpoint->address);
272 breakpoint->type = BKPT_HARD;
273 }
274
275 if ((breakpoint->type == BKPT_SOFT) && (arm7_9->sw_bkpts_enabled == 0))
276 {
277 INFO("sw breakpoint requested, but software breakpoints not enabled");
278 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
279 }
280
281 if ((breakpoint->type == BKPT_HARD) && (arm7_9->wp_available < 1))
282 {
283 INFO("no watchpoint unit available for hardware breakpoint");
284 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
285 }
286
287 if ((breakpoint->length != 2) && (breakpoint->length != 4))
288 {
289 INFO("only breakpoints of two (Thumb) or four (ARM) bytes length supported");
290 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
291 }
292
293 if (breakpoint->type == BKPT_HARD)
294 arm7_9->wp_available--;
295
296 return ERROR_OK;
297 }
298
299 int arm7_9_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
300 {
301 armv4_5_common_t *armv4_5 = target->arch_info;
302 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
303
304 if (target->state != TARGET_HALTED)
305 {
306 WARNING("target not halted");
307 return ERROR_TARGET_NOT_HALTED;
308 }
309
310 if (breakpoint->set)
311 {
312 arm7_9_unset_breakpoint(target, breakpoint);
313 }
314
315 if (breakpoint->type == BKPT_HARD)
316 arm7_9->wp_available++;
317
318 return ERROR_OK;
319 }
320
321 int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
322 {
323 armv4_5_common_t *armv4_5 = target->arch_info;
324 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
325 int rw_mask = 1;
326 u32 mask;
327
328 mask = watchpoint->length - 1;
329
330 if (target->state != TARGET_HALTED)
331 {
332 WARNING("target not halted");
333 return ERROR_TARGET_NOT_HALTED;
334 }
335
336 if (watchpoint->rw == WPT_ACCESS)
337 rw_mask = 0;
338 else
339 rw_mask = 1;
340
341 if (!arm7_9->wp0_used)
342 {
343 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], watchpoint->address);
344 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask);
345 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], watchpoint->mask);
346 if( watchpoint->mask != 0xffffffffu )
347 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], watchpoint->value);
348 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
349 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
350
351 jtag_execute_queue();
352 watchpoint->set = 1;
353 arm7_9->wp0_used = 2;
354 }
355 else if (!arm7_9->wp1_used)
356 {
357 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], watchpoint->address);
358 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask);
359 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], watchpoint->mask);
360 if( watchpoint->mask != 0xffffffffu )
361 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], watchpoint->value);
362 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
363 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
364
365 jtag_execute_queue();
366 watchpoint->set = 2;
367 arm7_9->wp1_used = 2;
368 }
369 else
370 {
371 ERROR("BUG: no hardware comparator available");
372 return ERROR_OK;
373 }
374
375 return ERROR_OK;
376 }
377
378 int arm7_9_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
379 {
380 armv4_5_common_t *armv4_5 = target->arch_info;
381 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
382
383 if (target->state != TARGET_HALTED)
384 {
385 WARNING("target not halted");
386 return ERROR_TARGET_NOT_HALTED;
387 }
388
389 if (!watchpoint->set)
390 {
391 WARNING("breakpoint not set");
392 return ERROR_OK;
393 }
394
395 if (watchpoint->set == 1)
396 {
397 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
398 jtag_execute_queue();
399 arm7_9->wp0_used = 0;
400 }
401 else if (watchpoint->set == 2)
402 {
403 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
404 jtag_execute_queue();
405 arm7_9->wp1_used = 0;
406 }
407 watchpoint->set = 0;
408
409 return ERROR_OK;
410 }
411
412 int arm7_9_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
413 {
414 armv4_5_common_t *armv4_5 = target->arch_info;
415 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
416
417 if (target->state != TARGET_HALTED)
418 {
419 WARNING("target not halted");
420 return ERROR_TARGET_NOT_HALTED;
421 }
422
423 if (arm7_9->wp_available < 1)
424 {
425 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
426 }
427
428 if ((watchpoint->length != 1) && (watchpoint->length != 2) && (watchpoint->length != 4))
429 {
430 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
431 }
432
433 arm7_9->wp_available--;
434
435 return ERROR_OK;
436 }
437
438 int arm7_9_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
439 {
440 armv4_5_common_t *armv4_5 = target->arch_info;
441 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
442
443 if (target->state != TARGET_HALTED)
444 {
445 WARNING("target not halted");
446 return ERROR_TARGET_NOT_HALTED;
447 }
448
449 if (watchpoint->set)
450 {
451 arm7_9_unset_watchpoint(target, watchpoint);
452 }
453
454 arm7_9->wp_available++;
455
456 return ERROR_OK;
457 }
458
459 int arm7_9_enable_sw_bkpts(struct target_s *target)
460 {
461 armv4_5_common_t *armv4_5 = target->arch_info;
462 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
463 int retval;
464
465 if (arm7_9->sw_bkpts_enabled)
466 return ERROR_OK;
467
468 if (arm7_9->wp_available < 1)
469 {
470 WARNING("can't enable sw breakpoints with no watchpoint unit available");
471 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
472 }
473 arm7_9->wp_available--;
474
475 if (!arm7_9->wp0_used)
476 {
477 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], arm7_9->arm_bkpt);
478 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0x0);
479 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffffu);
480 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
481 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
482 arm7_9->sw_bkpts_enabled = 1;
483 arm7_9->wp0_used = 3;
484 }
485 else if (!arm7_9->wp1_used)
486 {
487 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], arm7_9->arm_bkpt);
488 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0x0);
489 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0xffffffffu);
490 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
491 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
492 arm7_9->sw_bkpts_enabled = 2;
493 arm7_9->wp1_used = 3;
494 }
495 else
496 {
497 ERROR("BUG: both watchpoints used, but wp_available >= 1");
498 exit(-1);
499 }
500
501 if ((retval = jtag_execute_queue()) != ERROR_OK)
502 {
503 ERROR("error writing EmbeddedICE registers to enable sw breakpoints");
504 exit(-1);
505 };
506
507 return ERROR_OK;
508 }
509
510 int arm7_9_disable_sw_bkpts(struct target_s *target)
511 {
512 armv4_5_common_t *armv4_5 = target->arch_info;
513 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
514
515 if (!arm7_9->sw_bkpts_enabled)
516 return ERROR_OK;
517
518 if (arm7_9->sw_bkpts_enabled == 1)
519 {
520 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
521 arm7_9->sw_bkpts_enabled = 0;
522 arm7_9->wp0_used = 0;
523 arm7_9->wp_available++;
524 }
525 else if (arm7_9->sw_bkpts_enabled == 2)
526 {
527 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
528 arm7_9->sw_bkpts_enabled = 0;
529 arm7_9->wp1_used = 0;
530 arm7_9->wp_available++;
531 }
532
533 return ERROR_OK;
534 }
535
536 int arm7_9_execute_sys_speed(struct target_s *target)
537 {
538 int timeout;
539 int retval;
540
541 armv4_5_common_t *armv4_5 = target->arch_info;
542 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
543 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
544 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
545
546 /* set RESTART instruction */
547 jtag_add_end_state(TAP_RTI);
548 arm_jtag_set_instr(jtag_info, 0x4, NULL);
549
550 for (timeout=0; timeout<50; timeout++)
551 {
552 /* read debug status register */
553 embeddedice_read_reg(dbg_stat);
554 if ((retval = jtag_execute_queue()) != ERROR_OK)
555 return retval;
556 if ((buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))
557 && (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_SYSCOMP, 1)))
558 break;
559 usleep(100000);
560 }
561 if (timeout == 50)
562 {
563 ERROR("timeout waiting for SYSCOMP & DBGACK, last DBG_STATUS: %x", buf_get_u32(dbg_stat->value, 0, dbg_stat->size));
564 return ERROR_TARGET_TIMEOUT;
565 }
566
567 return ERROR_OK;
568 }
569
570 int arm7_9_execute_fast_sys_speed(struct target_s *target)
571 {
572 u8 check_value[4], check_mask[4];
573
574 armv4_5_common_t *armv4_5 = target->arch_info;
575 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
576 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
577 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
578
579 /* set RESTART instruction */
580 jtag_add_end_state(TAP_RTI);
581 arm_jtag_set_instr(jtag_info, 0x4, NULL);
582
583 /* check for DBGACK and SYSCOMP set (others don't care) */
584 buf_set_u32(check_value, 0, 32, 0x9);
585 buf_set_u32(check_mask, 0, 32, 0x9);
586
587 /* read debug status register */
588 embeddedice_read_reg_w_check(dbg_stat, check_value, check_value);
589
590 return ERROR_OK;
591 }
592
593 int arm7_9_target_request_data(target_t *target, u32 size, u8 *buffer)
594 {
595 armv4_5_common_t *armv4_5 = target->arch_info;
596 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
597 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
598 u32 *data;
599 int i;
600
601 data = malloc(size * (sizeof(u32)));
602
603 embeddedice_receive(jtag_info, data, size);
604
605 for (i = 0; i < size; i++)
606 {
607 h_u32_to_le(buffer + (i * 4), data[i]);
608 }
609
610 free(data);
611
612 return ERROR_OK;
613 }
614
615 int arm7_9_handle_target_request(void *priv)
616 {
617 target_t *target = priv;
618 armv4_5_common_t *armv4_5 = target->arch_info;
619 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
620 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
621 reg_t *dcc_control = &arm7_9->eice_cache->reg_list[EICE_COMMS_CTRL];
622
623 if (target->state == TARGET_RUNNING)
624 {
625 /* read DCC control register */
626 embeddedice_read_reg(dcc_control);
627 jtag_execute_queue();
628
629 /* check W bit */
630 if (buf_get_u32(dcc_control->value, 1, 1) == 1)
631 {
632 u32 request;
633
634 embeddedice_receive(jtag_info, &request, 1);
635 target_request(target, request);
636 }
637 }
638
639 return ERROR_OK;
640 }
641
642 enum target_state arm7_9_poll(target_t *target)
643 {
644 int retval;
645 armv4_5_common_t *armv4_5 = target->arch_info;
646 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
647 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
648
649 if (arm7_9->reinit_embeddedice)
650 {
651 arm7_9_reinit_embeddedice(target);
652 }
653
654 /* read debug status register */
655 embeddedice_read_reg(dbg_stat);
656 if ((retval = jtag_execute_queue()) != ERROR_OK)
657 {
658 switch (retval)
659 {
660 case ERROR_JTAG_QUEUE_FAILED:
661 ERROR("JTAG queue failed while reading EmbeddedICE status register");
662 exit(-1);
663 break;
664 default:
665 break;
666 }
667 }
668
669 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))
670 {
671 DEBUG("DBGACK set, dbg_state->value: 0x%x", buf_get_u32(dbg_stat->value, 0, 32));
672 if ((target->state == TARGET_UNKNOWN))
673 {
674 WARNING("DBGACK set while target was in unknown state. Reset or initialize target before resuming");
675 target->state = TARGET_RUNNING;
676 }
677 if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET))
678 {
679 target->state = TARGET_HALTED;
680 if ((retval = arm7_9_debug_entry(target)) != ERROR_OK)
681 return retval;
682
683 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
684 }
685 if (target->state == TARGET_DEBUG_RUNNING)
686 {
687 target->state = TARGET_HALTED;
688 if ((retval = arm7_9_debug_entry(target)) != ERROR_OK)
689 return retval;
690
691 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
692 }
693 }
694 else
695 {
696 if (target->state != TARGET_DEBUG_RUNNING)
697 target->state = TARGET_RUNNING;
698 }
699
700 return target->state;
701 }
702
703 int arm7_9_assert_reset(target_t *target)
704 {
705 int retval;
706
707 DEBUG("target->state: %s", target_state_strings[target->state]);
708
709 if (target->state == TARGET_HALTED || target->state == TARGET_UNKNOWN)
710 {
711 /* if the target wasn't running, there might be working areas allocated */
712 target_free_all_working_areas(target);
713
714 /* assert SRST and TRST */
715 /* system would get ouf sync if we didn't reset test-logic, too */
716 if ((retval = jtag_add_reset(1, 1)) != ERROR_OK)
717 {
718 if (retval == ERROR_JTAG_RESET_CANT_SRST)
719 {
720 WARNING("can't assert srst");
721 return retval;
722 }
723 else
724 {
725 ERROR("unknown error");
726 exit(-1);
727 }
728 }
729 jtag_add_sleep(5000);
730 if ((retval = jtag_add_reset(0, 1)) != ERROR_OK)
731 {
732 if (retval == ERROR_JTAG_RESET_WOULD_ASSERT_TRST)
733 {
734 WARNING("srst resets test logic, too");
735 retval = jtag_add_reset(1, 1);
736 }
737 }
738 }
739 else
740 {
741 if ((retval = jtag_add_reset(0, 1)) != ERROR_OK)
742 {
743 if (retval == ERROR_JTAG_RESET_WOULD_ASSERT_TRST)
744 {
745 WARNING("srst resets test logic, too");
746 retval = jtag_add_reset(1, 1);
747 }
748
749 if (retval == ERROR_JTAG_RESET_CANT_SRST)
750 {
751 WARNING("can't assert srst");
752 return retval;
753 }
754 else if (retval != ERROR_OK)
755 {
756 ERROR("unknown error");
757 exit(-1);
758 }
759 }
760 }
761
762 target->state = TARGET_RESET;
763 jtag_add_sleep(50000);
764
765 armv4_5_invalidate_core_regs(target);
766
767 return ERROR_OK;
768
769 }
770
771 int arm7_9_deassert_reset(target_t *target)
772 {
773 DEBUG("target->state: %s", target_state_strings[target->state]);
774
775 /* deassert reset lines */
776 jtag_add_reset(0, 0);
777
778 return ERROR_OK;
779 }
780
781 int arm7_9_clear_halt(target_t *target)
782 {
783 armv4_5_common_t *armv4_5 = target->arch_info;
784 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
785 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
786
787 /* we used DBGRQ only if we didn't come out of reset */
788 if (!arm7_9->debug_entry_from_reset && arm7_9->use_dbgrq)
789 {
790 /* program EmbeddedICE Debug Control Register to deassert DBGRQ
791 */
792 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
793 embeddedice_store_reg(dbg_ctrl);
794 }
795 else
796 {
797 if (arm7_9->debug_entry_from_reset && arm7_9->has_vector_catch)
798 {
799 /* if we came out of reset, and vector catch is supported, we used
800 * vector catch to enter debug state
801 * restore the register in that case
802 */
803 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH]);
804 }
805 else
806 {
807 /* restore registers if watchpoint unit 0 was in use
808 */
809 if (arm7_9->wp0_used)
810 {
811 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
812 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);
813 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK]);
814 }
815 /* control value always has to be restored, as it was either disabled,
816 * or enabled with possibly different bits
817 */
818 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]);
819 }
820 }
821
822 return ERROR_OK;
823 }
824
825 int arm7_9_soft_reset_halt(struct target_s *target)
826 {
827 armv4_5_common_t *armv4_5 = target->arch_info;
828 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
829 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
830 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
831 int i;
832
833 if (target->state == TARGET_RUNNING)
834 {
835 target->type->halt(target);
836 }
837
838 while (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
839 {
840 embeddedice_read_reg(dbg_stat);
841 jtag_execute_queue();
842 }
843 target->state = TARGET_HALTED;
844
845 /* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS
846 * ensure that DBGRQ is cleared
847 */
848 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
849 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
850 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 1);
851 embeddedice_store_reg(dbg_ctrl);
852
853 arm7_9_clear_halt(target);
854
855 /* if the target is in Thumb state, change to ARM state */
856 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_ITBIT, 1))
857 {
858 u32 r0_thumb, pc_thumb;
859 DEBUG("target entered debug from Thumb state, changing to ARM");
860 /* Entered debug from Thumb mode */
861 armv4_5->core_state = ARMV4_5_STATE_THUMB;
862 arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb);
863 }
864
865 /* all register content is now invalid */
866 armv4_5_invalidate_core_regs(target);
867
868 /* SVC, ARM state, IRQ and FIQ disabled */
869 buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
870 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
871 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
872
873 /* start fetching from 0x0 */
874 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
875 armv4_5->core_cache->reg_list[15].dirty = 1;
876 armv4_5->core_cache->reg_list[15].valid = 1;
877
878 armv4_5->core_mode = ARMV4_5_MODE_SVC;
879 armv4_5->core_state = ARMV4_5_STATE_ARM;
880
881 /* reset registers */
882 for (i = 0; i <= 14; i++)
883 {
884 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32, 0xffffffff);
885 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 1;
886 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid = 1;
887 }
888
889 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
890
891 return ERROR_OK;
892 }
893
894 int arm7_9_prepare_reset_halt(target_t *target)
895 {
896 armv4_5_common_t *armv4_5 = target->arch_info;
897 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
898
899 /* poll the target, and resume if it was currently halted */
900 arm7_9_poll(target);
901 if (target->state == TARGET_HALTED)
902 {
903 arm7_9_resume(target, 1, 0x0, 0, 1);
904 }
905
906 if (arm7_9->has_vector_catch)
907 {
908 /* program vector catch register to catch reset vector */
909 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH], 0x1);
910 }
911 else
912 {
913 /* program watchpoint unit to match on reset vector address */
914 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0x3);
915 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0x0);
916 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x100);
917 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xf7);
918 }
919
920 return ERROR_OK;
921 }
922
923 int arm7_9_halt(target_t *target)
924 {
925 armv4_5_common_t *armv4_5 = target->arch_info;
926 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
927 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
928
929 DEBUG("target->state: %s", target_state_strings[target->state]);
930
931 if (target->state == TARGET_HALTED)
932 {
933 WARNING("target was already halted");
934 return ERROR_TARGET_ALREADY_HALTED;
935 }
936
937 if (target->state == TARGET_UNKNOWN)
938 {
939 WARNING("target was in unknown state when halt was requested");
940 }
941
942 if (target->state == TARGET_RESET)
943 {
944 if ((jtag_reset_config & RESET_SRST_PULLS_TRST) && jtag_srst)
945 {
946 ERROR("can't request a halt while in reset if nSRST pulls nTRST");
947 return ERROR_TARGET_FAILURE;
948 }
949 else
950 {
951 /* we came here in a reset_halt or reset_init sequence
952 * debug entry was already prepared in arm7_9_prepare_reset_halt()
953 */
954 target->debug_reason = DBG_REASON_DBGRQ;
955
956 return ERROR_OK;
957 }
958 }
959
960 if (arm7_9->use_dbgrq)
961 {
962 /* program EmbeddedICE Debug Control Register to assert DBGRQ
963 */
964 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 1);
965 embeddedice_store_reg(dbg_ctrl);
966 }
967 else
968 {
969 /* program watchpoint unit to match on any address
970 */
971 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
972 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
973 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x100);
974 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xf7);
975 }
976
977 target->debug_reason = DBG_REASON_DBGRQ;
978
979 return ERROR_OK;
980 }
981
982 int arm7_9_debug_entry(target_t *target)
983 {
984 int i;
985 u32 context[16];
986 u32* context_p[16];
987 u32 r0_thumb, pc_thumb;
988 u32 cpsr;
989 int retval;
990 /* get pointers to arch-specific information */
991 armv4_5_common_t *armv4_5 = target->arch_info;
992 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
993 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
994 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
995
996 #ifdef _DEBUG_ARM7_9_
997 DEBUG("-");
998 #endif
999
1000 if (arm7_9->pre_debug_entry)
1001 arm7_9->pre_debug_entry(target);
1002
1003 /* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS
1004 * ensure that DBGRQ is cleared
1005 */
1006 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
1007 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
1008 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 1);
1009 embeddedice_store_reg(dbg_ctrl);
1010
1011 arm7_9_clear_halt(target);
1012
1013 if ((retval = jtag_execute_queue()) != ERROR_OK)
1014 {
1015 switch (retval)
1016 {
1017 case ERROR_JTAG_QUEUE_FAILED:
1018 ERROR("JTAG queue failed while writing EmbeddedICE control register");
1019 exit(-1);
1020 break;
1021 default:
1022 break;
1023 }
1024 }
1025
1026 if ((retval = arm7_9->examine_debug_reason(target)) != ERROR_OK)
1027 return retval;
1028
1029
1030 if (target->state != TARGET_HALTED)
1031 {
1032 WARNING("target not halted");
1033 return ERROR_TARGET_NOT_HALTED;
1034 }
1035
1036 /* if the target is in Thumb state, change to ARM state */
1037 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_ITBIT, 1))
1038 {
1039 DEBUG("target entered debug from Thumb state");
1040 /* Entered debug from Thumb mode */
1041 armv4_5->core_state = ARMV4_5_STATE_THUMB;
1042 arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb);
1043 DEBUG("r0_thumb: 0x%8.8x, pc_thumb: 0x%8.8x", r0_thumb, pc_thumb);
1044 }
1045 else
1046 {
1047 DEBUG("target entered debug from ARM state");
1048 /* Entered debug from ARM mode */
1049 armv4_5->core_state = ARMV4_5_STATE_ARM;
1050 }
1051
1052 for (i = 0; i < 16; i++)
1053 context_p[i] = &context[i];
1054 /* save core registers (r0 - r15 of current core mode) */
1055 arm7_9->read_core_regs(target, 0xffff, context_p);
1056
1057 arm7_9->read_xpsr(target, &cpsr, 0);
1058
1059 if ((retval = jtag_execute_queue()) != ERROR_OK)
1060 return retval;
1061
1062 /* if the core has been executing in Thumb state, set the T bit */
1063 if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1064 cpsr |= 0x20;
1065
1066 buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32, cpsr);
1067 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 0;
1068 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
1069
1070 armv4_5->core_mode = cpsr & 0x1f;
1071
1072 if (armv4_5_mode_to_number(armv4_5->core_mode) == -1)
1073 {
1074 target->state = TARGET_UNKNOWN;
1075 ERROR("cpsr contains invalid mode value - communication failure");
1076 return ERROR_TARGET_FAILURE;
1077 }
1078
1079 DEBUG("target entered debug state in %s mode", armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)]);
1080
1081 if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1082 {
1083 DEBUG("thumb state, applying fixups");
1084 context[0] = r0_thumb;
1085 context[15] = pc_thumb;
1086 } else if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1087 {
1088 /* adjust value stored by STM */
1089 context[15] -= 3 * 4;
1090 }
1091
1092 if ((target->debug_reason == DBG_REASON_BREAKPOINT)
1093 || (target->debug_reason == DBG_REASON_SINGLESTEP)
1094 || (target->debug_reason == DBG_REASON_WATCHPOINT)
1095 || (target->debug_reason == DBG_REASON_WPTANDBKPT)
1096 || ((target->debug_reason == DBG_REASON_DBGRQ) && (arm7_9->use_dbgrq == 0)))
1097 context[15] -= 3 * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2);
1098 else if (target->debug_reason == DBG_REASON_DBGRQ)
1099 context[15] -= arm7_9->dbgreq_adjust_pc * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2);
1100 else
1101 {
1102 ERROR("unknown debug reason: %i", target->debug_reason);
1103 }
1104
1105
1106 for (i=0; i<=15; i++)
1107 {
1108 DEBUG("r%i: 0x%8.8x", i, context[i]);
1109 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32, context[i]);
1110 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 0;
1111 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid = 1;
1112 }
1113
1114 DEBUG("entered debug state at PC 0x%x", context[15]);
1115
1116 /* exceptions other than USR & SYS have a saved program status register */
1117 if ((armv4_5_mode_to_number(armv4_5->core_mode) != ARMV4_5_MODE_USR) && (armv4_5_mode_to_number(armv4_5->core_mode) != ARMV4_5_MODE_SYS))
1118 {
1119 u32 spsr;
1120 arm7_9->read_xpsr(target, &spsr, 1);
1121 jtag_execute_queue();
1122 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).value, 0, 32, spsr);
1123 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).dirty = 0;
1124 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).valid = 1;
1125 }
1126
1127 /* r0 and r15 (pc) have to be restored later */
1128 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = 1;
1129 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15).dirty = 1;
1130
1131 if ((retval = jtag->execute_queue()) != ERROR_OK)
1132 return retval;
1133
1134 if (arm7_9->post_debug_entry)
1135 arm7_9->post_debug_entry(target);
1136
1137 return ERROR_OK;
1138 }
1139
1140 int arm7_9_full_context(target_t *target)
1141 {
1142 int i;
1143 int retval;
1144 armv4_5_common_t *armv4_5 = target->arch_info;
1145 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1146
1147 DEBUG("-");
1148
1149 if (target->state != TARGET_HALTED)
1150 {
1151 WARNING("target not halted");
1152 return ERROR_TARGET_NOT_HALTED;
1153 }
1154
1155 /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
1156 * SYS shares registers with User, so we don't touch SYS
1157 */
1158 for(i = 0; i < 6; i++)
1159 {
1160 u32 mask = 0;
1161 u32* reg_p[16];
1162 int j;
1163 int valid = 1;
1164
1165 /* check if there are invalid registers in the current mode
1166 */
1167 for (j = 0; j <= 16; j++)
1168 {
1169 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid == 0)
1170 valid = 0;
1171 }
1172
1173 if (!valid)
1174 {
1175 u32 tmp_cpsr;
1176
1177 /* change processor mode (and mask T bit) */
1178 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1179 tmp_cpsr |= armv4_5_number_to_mode(i);
1180 tmp_cpsr &= ~0x20;
1181 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1182
1183 for (j = 0; j < 15; j++)
1184 {
1185 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid == 0)
1186 {
1187 reg_p[j] = (u32*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).value;
1188 mask |= 1 << j;
1189 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid = 1;
1190 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).dirty = 0;
1191 }
1192 }
1193
1194 /* if only the PSR is invalid, mask is all zeroes */
1195 if (mask)
1196 arm7_9->read_core_regs(target, mask, reg_p);
1197
1198 /* check if the PSR has to be read */
1199 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).valid == 0)
1200 {
1201 arm7_9->read_xpsr(target, (u32*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).value, 1);
1202 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).valid = 1;
1203 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).dirty = 0;
1204 }
1205 }
1206 }
1207
1208 /* restore processor mode (mask T bit) */
1209 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
1210
1211 if ((retval = jtag_execute_queue()) != ERROR_OK)
1212 {
1213 ERROR("JTAG failure");
1214 exit(-1);
1215 }
1216 return ERROR_OK;
1217 }
1218
1219 int arm7_9_restore_context(target_t *target)
1220 {
1221 armv4_5_common_t *armv4_5 = target->arch_info;
1222 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1223 reg_t *reg;
1224 armv4_5_core_reg_t *reg_arch_info;
1225 enum armv4_5_mode current_mode = armv4_5->core_mode;
1226 int i, j;
1227 int dirty;
1228 int mode_change;
1229
1230 DEBUG("-");
1231
1232 if (target->state != TARGET_HALTED)
1233 {
1234 WARNING("target not halted");
1235 return ERROR_TARGET_NOT_HALTED;
1236 }
1237
1238 if (arm7_9->pre_restore_context)
1239 arm7_9->pre_restore_context(target);
1240
1241 /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
1242 * SYS shares registers with User, so we don't touch SYS
1243 */
1244 for (i = 0; i < 6; i++)
1245 {
1246 DEBUG("examining %s mode", armv4_5_mode_strings[i]);
1247 dirty = 0;
1248 mode_change = 0;
1249 /* check if there are dirty registers in the current mode
1250 */
1251 for (j = 0; j <= 16; j++)
1252 {
1253 reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j);
1254 reg_arch_info = reg->arch_info;
1255 if (reg->dirty == 1)
1256 {
1257 if (reg->valid == 1)
1258 {
1259 dirty = 1;
1260 DEBUG("examining dirty reg: %s", reg->name);
1261 if ((reg_arch_info->mode != ARMV4_5_MODE_ANY)
1262 && (reg_arch_info->mode != current_mode)
1263 && !((reg_arch_info->mode == ARMV4_5_MODE_USR) && (armv4_5->core_mode == ARMV4_5_MODE_SYS))
1264 && !((reg_arch_info->mode == ARMV4_5_MODE_SYS) && (armv4_5->core_mode == ARMV4_5_MODE_USR)))
1265 {
1266 mode_change = 1;
1267 DEBUG("require mode change");
1268 }
1269 }
1270 else
1271 {
1272 ERROR("BUG: dirty register '%s', but no valid data", reg->name);
1273 exit(-1);
1274 }
1275 }
1276 }
1277
1278 if (dirty)
1279 {
1280 u32 mask = 0x0;
1281 int num_regs = 0;
1282 u32 regs[16];
1283
1284 if (mode_change)
1285 {
1286 u32 tmp_cpsr;
1287
1288 /* change processor mode (mask T bit) */
1289 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1290 tmp_cpsr |= armv4_5_number_to_mode(i);
1291 tmp_cpsr &= ~0x20;
1292 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1293 current_mode = armv4_5_number_to_mode(i);
1294 }
1295
1296 for (j = 0; j <= 14; j++)
1297 {
1298 reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j);
1299 reg_arch_info = reg->arch_info;
1300
1301
1302 if (reg->dirty == 1)
1303 {
1304 regs[j] = buf_get_u32(reg->value, 0, 32);
1305 mask |= 1 << j;
1306 num_regs++;
1307 reg->dirty = 0;
1308 reg->valid = 1;
1309 DEBUG("writing register %i of mode %s with value 0x%8.8x", j, armv4_5_mode_strings[i], regs[j]);
1310 }
1311 }
1312
1313 if (mask)
1314 {
1315 arm7_9->write_core_regs(target, mask, regs);
1316 }
1317
1318 reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16);
1319 reg_arch_info = reg->arch_info;
1320 if ((reg->dirty) && (reg_arch_info->mode != ARMV4_5_MODE_ANY))
1321 {
1322 DEBUG("writing SPSR of mode %i with value 0x%8.8x", i, buf_get_u32(reg->value, 0, 32));
1323 arm7_9->write_xpsr(target, buf_get_u32(reg->value, 0, 32), 1);
1324 }
1325 }
1326 }
1327
1328 if ((armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty == 0) && (armv4_5->core_mode != current_mode))
1329 {
1330 /* restore processor mode (mask T bit) */
1331 u32 tmp_cpsr;
1332
1333 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1334 tmp_cpsr |= armv4_5_number_to_mode(i);
1335 tmp_cpsr &= ~0x20;
1336 DEBUG("writing lower 8 bit of cpsr with value 0x%2.2x", tmp_cpsr);
1337 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1338 }
1339 else if (armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty == 1)
1340 {
1341 /* CPSR has been changed, full restore necessary (mask T bit) */
1342 DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
1343 arm7_9->write_xpsr(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32) & ~0x20, 0);
1344 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 0;
1345 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
1346 }
1347
1348 /* restore PC */
1349 DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1350 arm7_9->write_pc(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1351 armv4_5->core_cache->reg_list[15].dirty = 0;
1352
1353 if (arm7_9->post_restore_context)
1354 arm7_9->post_restore_context(target);
1355
1356 return ERROR_OK;
1357 }
1358
1359 int arm7_9_restart_core(struct target_s *target)
1360 {
1361 armv4_5_common_t *armv4_5 = target->arch_info;
1362 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1363 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
1364
1365 /* set RESTART instruction */
1366 jtag_add_end_state(TAP_RTI);
1367 arm_jtag_set_instr(jtag_info, 0x4, NULL);
1368
1369 jtag_add_runtest(1, TAP_RTI);
1370 if ((jtag_execute_queue()) != ERROR_OK)
1371 {
1372 exit(-1);
1373 }
1374
1375 return ERROR_OK;
1376 }
1377
1378 void arm7_9_enable_watchpoints(struct target_s *target)
1379 {
1380 watchpoint_t *watchpoint = target->watchpoints;
1381
1382 while (watchpoint)
1383 {
1384 if (watchpoint->set == 0)
1385 arm7_9_set_watchpoint(target, watchpoint);
1386 watchpoint = watchpoint->next;
1387 }
1388 }
1389
1390 void arm7_9_enable_breakpoints(struct target_s *target)
1391 {
1392 breakpoint_t *breakpoint = target->breakpoints;
1393
1394 /* set any pending breakpoints */
1395 while (breakpoint)
1396 {
1397 if (breakpoint->set == 0)
1398 arm7_9_set_breakpoint(target, breakpoint);
1399 breakpoint = breakpoint->next;
1400 }
1401 }
1402
1403 void arm7_9_disable_bkpts_and_wpts(struct target_s *target)
1404 {
1405 breakpoint_t *breakpoint = target->breakpoints;
1406 watchpoint_t *watchpoint = target->watchpoints;
1407
1408 /* set any pending breakpoints */
1409 while (breakpoint)
1410 {
1411 if (breakpoint->set != 0)
1412 arm7_9_unset_breakpoint(target, breakpoint);
1413 breakpoint = breakpoint->next;
1414 }
1415
1416 while (watchpoint)
1417 {
1418 if (watchpoint->set != 0)
1419 arm7_9_unset_watchpoint(target, watchpoint);
1420 watchpoint = watchpoint->next;
1421 }
1422 }
1423
1424 int arm7_9_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution)
1425 {
1426 armv4_5_common_t *armv4_5 = target->arch_info;
1427 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1428 breakpoint_t *breakpoint = target->breakpoints;
1429 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1430
1431 DEBUG("-");
1432
1433 if (target->state != TARGET_HALTED)
1434 {
1435 WARNING("target not halted");
1436 return ERROR_TARGET_NOT_HALTED;
1437 }
1438
1439 if (!debug_execution)
1440 {
1441 target_free_all_working_areas(target);
1442 }
1443
1444 /* current = 1: continue on current pc, otherwise continue at <address> */
1445 if (!current)
1446 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
1447
1448 /* the front-end may request us not to handle breakpoints */
1449 if (handle_breakpoints)
1450 {
1451 if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
1452 {
1453 DEBUG("unset breakpoint at 0x%8.8x", breakpoint->address);
1454 arm7_9_unset_breakpoint(target, breakpoint);
1455
1456 DEBUG("enable single-step");
1457 arm7_9->enable_single_step(target);
1458
1459 target->debug_reason = DBG_REASON_SINGLESTEP;
1460
1461 arm7_9_restore_context(target);
1462
1463 if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1464 arm7_9->branch_resume(target);
1465 else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1466 {
1467 arm7_9->branch_resume_thumb(target);
1468 }
1469 else
1470 {
1471 ERROR("unhandled core state");
1472 exit(-1);
1473 }
1474
1475 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
1476 embeddedice_write_reg(dbg_ctrl, buf_get_u32(dbg_ctrl->value, 0, dbg_ctrl->size));
1477 arm7_9_execute_sys_speed(target);
1478
1479 DEBUG("disable single-step");
1480 arm7_9->disable_single_step(target);
1481
1482 arm7_9_debug_entry(target);
1483 DEBUG("new PC after step: 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1484
1485 DEBUG("set breakpoint at 0x%8.8x", breakpoint->address);
1486 arm7_9_set_breakpoint(target, breakpoint);
1487 }
1488 }
1489
1490 /* enable any pending breakpoints and watchpoints */
1491 arm7_9_enable_breakpoints(target);
1492 arm7_9_enable_watchpoints(target);
1493
1494 arm7_9_restore_context(target);
1495
1496 if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1497 {
1498 arm7_9->branch_resume(target);
1499 }
1500 else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1501 {
1502 arm7_9->branch_resume_thumb(target);
1503 }
1504 else
1505 {
1506 ERROR("unhandled core state");
1507 exit(-1);
1508 }
1509
1510 /* deassert DBGACK and INTDIS */
1511 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
1512 /* INTDIS only when we really resume, not during debug execution */
1513 if (!debug_execution)
1514 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 0);
1515 embeddedice_write_reg(dbg_ctrl, buf_get_u32(dbg_ctrl->value, 0, dbg_ctrl->size));
1516
1517 arm7_9_restart_core(target);
1518
1519 target->debug_reason = DBG_REASON_NOTHALTED;
1520
1521 if (!debug_execution)
1522 {
1523 /* registers are now invalid */
1524 armv4_5_invalidate_core_regs(target);
1525 target->state = TARGET_RUNNING;
1526 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1527 }
1528 else
1529 {
1530 target->state = TARGET_DEBUG_RUNNING;
1531 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
1532 }
1533
1534 DEBUG("target resumed");
1535
1536 return ERROR_OK;
1537 }
1538
1539 void arm7_9_enable_eice_step(target_t *target)
1540 {
1541 armv4_5_common_t *armv4_5 = target->arch_info;
1542 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1543
1544 /* setup an inverse breakpoint on the current PC
1545 * - comparator 1 matches the current address
1546 * - rangeout from comparator 1 is connected to comparator 0 rangein
1547 * - comparator 0 matches any address, as long as rangein is low */
1548 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
1549 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
1550 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x100);
1551 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0x77);
1552 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1553 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0);
1554 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffff);
1555 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
1556 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], 0xf7);
1557 }
1558
1559 void arm7_9_disable_eice_step(target_t *target)
1560 {
1561 armv4_5_common_t *armv4_5 = target->arch_info;
1562 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1563
1564 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
1565 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);
1566 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]);
1567 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK]);
1568 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE]);
1569 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK]);
1570 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK]);
1571 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK]);
1572 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE]);
1573 }
1574
1575 int arm7_9_step(struct target_s *target, int current, u32 address, int handle_breakpoints)
1576 {
1577 armv4_5_common_t *armv4_5 = target->arch_info;
1578 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1579 breakpoint_t *breakpoint = NULL;
1580
1581 if (target->state != TARGET_HALTED)
1582 {
1583 WARNING("target not halted");
1584 return ERROR_TARGET_NOT_HALTED;
1585 }
1586
1587 /* current = 1: continue on current pc, otherwise continue at <address> */
1588 if (!current)
1589 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
1590
1591 /* the front-end may request us not to handle breakpoints */
1592 if (handle_breakpoints)
1593 if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
1594 arm7_9_unset_breakpoint(target, breakpoint);
1595
1596 target->debug_reason = DBG_REASON_SINGLESTEP;
1597
1598 arm7_9_restore_context(target);
1599
1600 arm7_9->enable_single_step(target);
1601
1602 if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1603 {
1604 arm7_9->branch_resume(target);
1605 }
1606 else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1607 {
1608 arm7_9->branch_resume_thumb(target);
1609 }
1610 else
1611 {
1612 ERROR("unhandled core state");
1613 exit(-1);
1614 }
1615
1616 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1617
1618 arm7_9_execute_sys_speed(target);
1619 arm7_9->disable_single_step(target);
1620
1621 /* registers are now invalid */
1622 armv4_5_invalidate_core_regs(target);
1623
1624 arm7_9_debug_entry(target);
1625
1626 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
1627
1628 if (breakpoint)
1629 arm7_9_set_breakpoint(target, breakpoint);
1630
1631 DEBUG("target stepped");
1632
1633 return ERROR_OK;
1634
1635 }
1636
1637 int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mode)
1638 {
1639 u32* reg_p[16];
1640 u32 value;
1641 int retval;
1642 armv4_5_common_t *armv4_5 = target->arch_info;
1643 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1644 enum armv4_5_mode reg_mode = ((armv4_5_core_reg_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode;
1645
1646 if ((num < 0) || (num > 16))
1647 return ERROR_INVALID_ARGUMENTS;
1648
1649 if ((mode != ARMV4_5_MODE_ANY)
1650 && (mode != armv4_5->core_mode)
1651 && (reg_mode != ARMV4_5_MODE_ANY))
1652 {
1653 u32 tmp_cpsr;
1654
1655 /* change processor mode (mask T bit) */
1656 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1657 tmp_cpsr |= mode;
1658 tmp_cpsr &= ~0x20;
1659 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1660 }
1661
1662 if ((num >= 0) && (num <= 15))
1663 {
1664 /* read a normal core register */
1665 reg_p[num] = &value;
1666
1667 arm7_9->read_core_regs(target, 1 << num, reg_p);
1668 }
1669 else
1670 {
1671 /* read a program status register
1672 * if the register mode is MODE_ANY, we read the cpsr, otherwise a spsr
1673 */
1674 armv4_5_core_reg_t *arch_info = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info;
1675 int spsr = (arch_info->mode == ARMV4_5_MODE_ANY) ? 0 : 1;
1676
1677 arm7_9->read_xpsr(target, &value, spsr);
1678 }
1679
1680 if ((retval = jtag_execute_queue()) != ERROR_OK)
1681 {
1682 ERROR("JTAG failure");
1683 exit(-1);
1684 }
1685
1686 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
1687 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
1688 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).value, 0, 32, value);
1689
1690 if ((mode != ARMV4_5_MODE_ANY)
1691 && (mode != armv4_5->core_mode)
1692 && (reg_mode != ARMV4_5_MODE_ANY)) {
1693 /* restore processor mode (mask T bit) */
1694 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
1695 }
1696
1697 return ERROR_OK;
1698
1699 }
1700
1701 int arm7_9_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mode, u32 value)
1702 {
1703 u32 reg[16];
1704 int retval;
1705 armv4_5_common_t *armv4_5 = target->arch_info;
1706 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1707 enum armv4_5_mode reg_mode = ((armv4_5_core_reg_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode;
1708
1709 if ((num < 0) || (num > 16))
1710 return ERROR_INVALID_ARGUMENTS;
1711
1712 if ((mode != ARMV4_5_MODE_ANY)
1713 && (mode != armv4_5->core_mode)
1714 && (reg_mode != ARMV4_5_MODE_ANY)) {
1715 u32 tmp_cpsr;
1716
1717 /* change processor mode (mask T bit) */
1718 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1719 tmp_cpsr |= mode;
1720 tmp_cpsr &= ~0x20;
1721 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1722 }
1723
1724 if ((num >= 0) && (num <= 15))
1725 {
1726 /* write a normal core register */
1727 reg[num] = value;
1728
1729 arm7_9->write_core_regs(target, 1 << num, reg);
1730 }
1731 else
1732 {
1733 /* write a program status register
1734 * if the register mode is MODE_ANY, we write the cpsr, otherwise a spsr
1735 */
1736 armv4_5_core_reg_t *arch_info = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info;
1737 int spsr = (arch_info->mode == ARMV4_5_MODE_ANY) ? 0 : 1;
1738
1739 /* if we're writing the CPSR, mask the T bit */
1740 if (!spsr)
1741 value &= ~0x20;
1742
1743 arm7_9->write_xpsr(target, value, spsr);
1744 }
1745
1746 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
1747 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
1748
1749 if ((mode != ARMV4_5_MODE_ANY)
1750 && (mode != armv4_5->core_mode)
1751 && (reg_mode != ARMV4_5_MODE_ANY)) {
1752 /* restore processor mode (mask T bit) */
1753 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
1754 }
1755
1756 if ((retval = jtag_execute_queue()) != ERROR_OK)
1757 {
1758 ERROR("JTAG failure");
1759 exit(-1);
1760 }
1761
1762 return ERROR_OK;
1763
1764 }
1765
1766 int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1767 {
1768 armv4_5_common_t *armv4_5 = target->arch_info;
1769 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1770
1771 u32 reg[16];
1772 int num_accesses = 0;
1773 int thisrun_accesses;
1774 int i;
1775 u32 cpsr;
1776 int retval;
1777 int last_reg = 0;
1778
1779 DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
1780
1781 if (target->state != TARGET_HALTED)
1782 {
1783 WARNING("target not halted");
1784 return ERROR_TARGET_NOT_HALTED;
1785 }
1786
1787 /* sanitize arguments */
1788 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
1789 return ERROR_INVALID_ARGUMENTS;
1790
1791 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1792 return ERROR_TARGET_UNALIGNED_ACCESS;
1793
1794 /* load the base register with the address of the first word */
1795 reg[0] = address;
1796 arm7_9->write_core_regs(target, 0x1, reg);
1797
1798 switch (size)
1799 {
1800 case 4:
1801 while (num_accesses < count)
1802 {
1803 u32 reg_list;
1804 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1805 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1806
1807 if (last_reg <= thisrun_accesses)
1808 last_reg = thisrun_accesses;
1809
1810 arm7_9->load_word_regs(target, reg_list);
1811
1812 /* fast memory reads are only safe when the target is running
1813 * from a sufficiently high clock (32 kHz is usually too slow)
1814 */
1815 if (arm7_9->fast_memory_access)
1816 arm7_9_execute_fast_sys_speed(target);
1817 else
1818 arm7_9_execute_sys_speed(target);
1819
1820 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 4);
1821
1822 /* advance buffer, count number of accesses */
1823 buffer += thisrun_accesses * 4;
1824 num_accesses += thisrun_accesses;
1825 }
1826 break;
1827 case 2:
1828 while (num_accesses < count)
1829 {
1830 u32 reg_list;
1831 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1832 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1833
1834 for (i = 1; i <= thisrun_accesses; i++)
1835 {
1836 if (i > last_reg)
1837 last_reg = i;
1838 arm7_9->load_hword_reg(target, i);
1839 /* fast memory reads are only safe when the target is running
1840 * from a sufficiently high clock (32 kHz is usually too slow)
1841 */
1842 if (arm7_9->fast_memory_access)
1843 arm7_9_execute_fast_sys_speed(target);
1844 else
1845 arm7_9_execute_sys_speed(target);
1846 }
1847
1848 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 2);
1849
1850 /* advance buffer, count number of accesses */
1851 buffer += thisrun_accesses * 2;
1852 num_accesses += thisrun_accesses;
1853 }
1854 break;
1855 case 1:
1856 while (num_accesses < count)
1857 {
1858 u32 reg_list;
1859 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1860 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1861
1862 for (i = 1; i <= thisrun_accesses; i++)
1863 {
1864 if (i > last_reg)
1865 last_reg = i;
1866 arm7_9->load_byte_reg(target, i);
1867 /* fast memory reads are only safe when the target is running
1868 * from a sufficiently high clock (32 kHz is usually too slow)
1869 */
1870 if (arm7_9->fast_memory_access)
1871 arm7_9_execute_fast_sys_speed(target);
1872 else
1873 arm7_9_execute_sys_speed(target);
1874 }
1875
1876 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 1);
1877
1878 /* advance buffer, count number of accesses */
1879 buffer += thisrun_accesses * 1;
1880 num_accesses += thisrun_accesses;
1881 }
1882 break;
1883 default:
1884 ERROR("BUG: we shouldn't get here");
1885 exit(-1);
1886 break;
1887 }
1888
1889 for (i=0; i<=last_reg; i++)
1890 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 1;
1891
1892 arm7_9->read_xpsr(target, &cpsr, 0);
1893 if ((retval = jtag_execute_queue()) != ERROR_OK)
1894 {
1895 ERROR("JTAG error while reading cpsr");
1896 exit(-1);
1897 }
1898
1899 if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))
1900 {
1901 WARNING("memory read caused data abort (address: 0x%8.8x, size: 0x%x, count: 0x%x)", address, size, count);
1902
1903 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
1904
1905 return ERROR_TARGET_DATA_ABORT;
1906 }
1907
1908 return ERROR_OK;
1909 }
1910
1911 int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1912 {
1913 armv4_5_common_t *armv4_5 = target->arch_info;
1914 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1915 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1916
1917 u32 reg[16];
1918 int num_accesses = 0;
1919 int thisrun_accesses;
1920 int i;
1921 u32 cpsr;
1922 int retval;
1923 int last_reg = 0;
1924
1925 DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
1926
1927 if (target->state != TARGET_HALTED)
1928 {
1929 WARNING("target not halted");
1930 return ERROR_TARGET_NOT_HALTED;
1931 }
1932
1933 /* sanitize arguments */
1934 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
1935 return ERROR_INVALID_ARGUMENTS;
1936
1937 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1938 return ERROR_TARGET_UNALIGNED_ACCESS;
1939
1940 /* load the base register with the address of the first word */
1941 reg[0] = address;
1942 arm7_9->write_core_regs(target, 0x1, reg);
1943
1944 /* Clear DBGACK, to make sure memory fetches work as expected */
1945 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
1946 embeddedice_store_reg(dbg_ctrl);
1947
1948 switch (size)
1949 {
1950 case 4:
1951 while (num_accesses < count)
1952 {
1953 u32 reg_list;
1954 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1955 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1956
1957 for (i = 1; i <= thisrun_accesses; i++)
1958 {
1959 if (i > last_reg)
1960 last_reg = i;
1961 reg[i] = target_buffer_get_u32(target, buffer);
1962 buffer += 4;
1963 }
1964
1965 arm7_9->write_core_regs(target, reg_list, reg);
1966
1967 arm7_9->store_word_regs(target, reg_list);
1968
1969 /* fast memory writes are only safe when the target is running
1970 * from a sufficiently high clock (32 kHz is usually too slow)
1971 */
1972 if (arm7_9->fast_memory_access)
1973 arm7_9_execute_fast_sys_speed(target);
1974 else
1975 arm7_9_execute_sys_speed(target);
1976
1977 num_accesses += thisrun_accesses;
1978 }
1979 break;
1980 case 2:
1981 while (num_accesses < count)
1982 {
1983 u32 reg_list;
1984 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1985 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1986
1987 for (i = 1; i <= thisrun_accesses; i++)
1988 {
1989 if (i > last_reg)
1990 last_reg = i;
1991 reg[i] = target_buffer_get_u16(target, buffer) & 0xffff;
1992 buffer += 2;
1993 }
1994
1995 arm7_9->write_core_regs(target, reg_list, reg);
1996
1997 for (i = 1; i <= thisrun_accesses; i++)
1998 {
1999 arm7_9->store_hword_reg(target, i);
2000
2001 /* fast memory writes are only safe when the target is running
2002 * from a sufficiently high clock (32 kHz is usually too slow)
2003 */
2004 if (arm7_9->fast_memory_access)
2005 arm7_9_execute_fast_sys_speed(target);
2006 else
2007 arm7_9_execute_sys_speed(target);
2008 }
2009
2010 num_accesses += thisrun_accesses;
2011 }
2012 break;
2013 case 1:
2014 while (num_accesses < count)
2015 {
2016 u32 reg_list;
2017 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
2018 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2019
2020 for (i = 1; i <= thisrun_accesses; i++)
2021 {
2022 if (i > last_reg)
2023 last_reg = i;
2024 reg[i] = *buffer++ & 0xff;
2025 }
2026
2027 arm7_9->write_core_regs(target, reg_list, reg);
2028
2029 for (i = 1; i <= thisrun_accesses; i++)
2030 {
2031 arm7_9->store_byte_reg(target, i);
2032 /* fast memory writes are only safe when the target is running
2033 * from a sufficiently high clock (32 kHz is usually too slow)
2034 */
2035 if (arm7_9->fast_memory_access)
2036 arm7_9_execute_fast_sys_speed(target);
2037 else
2038 arm7_9_execute_sys_speed(target);
2039 }
2040
2041 num_accesses += thisrun_accesses;
2042 }
2043 break;
2044 default:
2045 ERROR("BUG: we shouldn't get here");
2046 exit(-1);
2047 break;
2048 }
2049
2050 /* Re-Set DBGACK */
2051 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
2052 embeddedice_store_reg(dbg_ctrl);
2053
2054 for (i=0; i<=last_reg; i++)
2055 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 1;
2056
2057 arm7_9->read_xpsr(target, &cpsr, 0);
2058 if ((retval = jtag_execute_queue()) != ERROR_OK)
2059 {
2060 ERROR("JTAG error while reading cpsr");
2061 exit(-1);
2062 }
2063
2064 if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))
2065 {
2066 WARNING("memory write caused data abort (address: 0x%8.8x, size: 0x%x, count: 0x%x)", address, size, count);
2067
2068 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
2069
2070 return ERROR_TARGET_DATA_ABORT;
2071 }
2072
2073 return ERROR_OK;
2074 }
2075
2076 int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer)
2077 {
2078 armv4_5_common_t *armv4_5 = target->arch_info;
2079 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
2080 enum armv4_5_state core_state = armv4_5->core_state;
2081 u32 r0 = buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32);
2082 u32 r1 = buf_get_u32(armv4_5->core_cache->reg_list[1].value, 0, 32);
2083 u32 pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
2084 int i;
2085
2086 u32 dcc_code[] =
2087 {
2088 /* MRC TST BNE MRC STR B */
2089 0xee101e10, 0xe3110001, 0x0afffffc, 0xee111e10, 0xe4801004, 0xeafffff9
2090 };
2091
2092 if (!arm7_9->dcc_downloads)
2093 return target->type->write_memory(target, address, 4, count, buffer);
2094
2095 /* regrab previously allocated working_area, or allocate a new one */
2096 if (!arm7_9->dcc_working_area)
2097 {
2098 u8 dcc_code_buf[6 * 4];
2099
2100 /* make sure we have a working area */
2101 if (target_alloc_working_area(target, 24, &arm7_9->dcc_working_area) != ERROR_OK)
2102 {
2103 INFO("no working area available, falling back to memory writes");
2104 return target->type->write_memory(target, address, 4, count, buffer);
2105 }
2106
2107 /* copy target instructions to target endianness */
2108 for (i = 0; i < 6; i++)
2109 {
2110 target_buffer_set_u32(target, dcc_code_buf + i*4, dcc_code[i]);
2111 }
2112
2113 /* write DCC code to working area */
2114 target->type->write_memory(target, arm7_9->dcc_working_area->address, 4, 6, dcc_code_buf);
2115 }
2116
2117 buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, address);
2118 armv4_5->core_cache->reg_list[0].valid = 1;
2119 armv4_5->core_cache->reg_list[0].dirty = 1;
2120 armv4_5->core_state = ARMV4_5_STATE_ARM;
2121
2122 arm7_9_resume(target, 0, arm7_9->dcc_working_area->address, 1, 1);
2123
2124 for (i = 0; i < count; i++)
2125 {
2126 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], target_buffer_get_u32(target, buffer));
2127 buffer += 4;
2128 }
2129
2130 target->type->halt(target);
2131
2132 while (target->state != TARGET_HALTED)
2133 target->type->poll(target);
2134
2135 /* restore target state */
2136 buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, r0);
2137 armv4_5->core_cache->reg_list[0].valid = 1;
2138 armv4_5->core_cache->reg_list[0].dirty = 1;
2139 buf_set_u32(armv4_5->core_cache->reg_list[1].value, 0, 32, r1);
2140 armv4_5->core_cache->reg_list[1].valid = 1;
2141 armv4_5->core_cache->reg_list[1].dirty = 1;
2142 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, pc);
2143 armv4_5->core_cache->reg_list[15].valid = 1;
2144 armv4_5->core_cache->reg_list[15].dirty = 1;
2145 armv4_5->core_state = core_state;
2146
2147 return ERROR_OK;
2148 }
2149
2150 int arm7_9_register_commands(struct command_context_s *cmd_ctx)
2151 {
2152 command_t *arm7_9_cmd;
2153
2154 arm7_9_cmd = register_command(cmd_ctx, NULL, "arm7_9", NULL, COMMAND_ANY, "arm7/9 specific commands");
2155
2156 register_command(cmd_ctx, arm7_9_cmd, "write_xpsr", handle_arm7_9_write_xpsr_command, COMMAND_EXEC, "write program status register <value> <not cpsr|spsr>");
2157 register_command(cmd_ctx, arm7_9_cmd, "write_xpsr_im8", handle_arm7_9_write_xpsr_im8_command, COMMAND_EXEC, "write program status register <8bit immediate> <rotate> <not cpsr|spsr>");
2158
2159 register_command(cmd_ctx, arm7_9_cmd, "write_core_reg", handle_arm7_9_write_core_reg_command, COMMAND_EXEC, "write core register <num> <mode> <value>");
2160
2161 register_command(cmd_ctx, arm7_9_cmd, "sw_bkpts", handle_arm7_9_sw_bkpts_command, COMMAND_EXEC, "support for software breakpoints <enable|disable>");
2162 register_command(cmd_ctx, arm7_9_cmd, "force_hw_bkpts", handle_arm7_9_force_hw_bkpts_command, COMMAND_EXEC, "use hardware breakpoints for all breakpoints (disables sw breakpoint support) <enable|disable>");
2163 register_command(cmd_ctx, arm7_9_cmd, "dbgrq", handle_arm7_9_dbgrq_command,
2164 COMMAND_ANY, "use EmbeddedICE dbgrq instead of breakpoint for target halt requests <enable|disable>");
2165 register_command(cmd_ctx, arm7_9_cmd, "fast_writes", handle_arm7_9_fast_memory_access_command,
2166 COMMAND_ANY, "(deprecated, see: arm7_9 fast_memory_access)");
2167 register_command(cmd_ctx, arm7_9_cmd, "fast_memory_access", handle_arm7_9_fast_memory_access_command,
2168 COMMAND_ANY, "use fast memory accesses instead of slower but potentially unsafe slow accesses <enable|disable>");
2169 register_command(cmd_ctx, arm7_9_cmd, "dcc_downloads", handle_arm7_9_dcc_downloads_command,
2170 COMMAND_ANY, "use DCC downloads for larger memory writes <enable|disable>");
2171
2172 armv4_5_register_commands(cmd_ctx);
2173
2174 etm_register_commands(cmd_ctx);
2175
2176 return ERROR_OK;
2177 }
2178
2179 int handle_arm7_9_write_xpsr_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2180 {
2181 u32 value;
2182 int spsr;
2183 int retval;
2184 target_t *target = get_current_target(cmd_ctx);
2185 armv4_5_common_t *armv4_5;
2186 arm7_9_common_t *arm7_9;
2187
2188 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2189 {
2190 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2191 return ERROR_OK;
2192 }
2193
2194 if (target->state != TARGET_HALTED)
2195 {
2196 command_print(cmd_ctx, "can't write registers while running");
2197 return ERROR_OK;
2198 }
2199
2200 if (argc < 2)
2201 {
2202 command_print(cmd_ctx, "usage: write_xpsr <value> <not cpsr|spsr>");
2203 return ERROR_OK;
2204 }
2205
2206 value = strtoul(args[0], NULL, 0);
2207 spsr = strtol(args[1], NULL, 0);
2208
2209 /* if we're writing the CPSR, mask the T bit */
2210 if (!spsr)
2211 value &= ~0x20;
2212
2213 arm7_9->write_xpsr(target, value, spsr);
2214 if ((retval = jtag_execute_queue()) != ERROR_OK)
2215 {
2216 ERROR("JTAG error while writing to xpsr");
2217 exit(-1);
2218 }
2219
2220 return ERROR_OK;
2221 }
2222
2223 int handle_arm7_9_write_xpsr_im8_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2224 {
2225 u32 value;
2226 int rotate;
2227 int spsr;
2228 int retval;
2229 target_t *target = get_current_target(cmd_ctx);
2230 armv4_5_common_t *armv4_5;
2231 arm7_9_common_t *arm7_9;
2232
2233 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2234 {
2235 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2236 return ERROR_OK;
2237 }
2238
2239 if (target->state != TARGET_HALTED)
2240 {
2241 command_print(cmd_ctx, "can't write registers while running");
2242 return ERROR_OK;
2243 }
2244
2245 if (argc < 3)
2246 {
2247 command_print(cmd_ctx, "usage: write_xpsr_im8 <im8> <rotate> <not cpsr|spsr>");
2248 return ERROR_OK;
2249 }
2250
2251 value = strtoul(args[0], NULL, 0);
2252 rotate = strtol(args[1], NULL, 0);
2253 spsr = strtol(args[2], NULL, 0);
2254
2255 arm7_9->write_xpsr_im8(target, value, rotate, spsr);
2256 if ((retval = jtag_execute_queue()) != ERROR_OK)
2257 {
2258 ERROR("JTAG error while writing 8-bit immediate to xpsr");
2259 exit(-1);
2260 }
2261
2262 return ERROR_OK;
2263 }
2264
2265 int handle_arm7_9_write_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2266 {
2267 u32 value;
2268 u32 mode;
2269 int num;
2270 target_t *target = get_current_target(cmd_ctx);
2271 armv4_5_common_t *armv4_5;
2272 arm7_9_common_t *arm7_9;
2273
2274 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2275 {
2276 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2277 return ERROR_OK;
2278 }
2279
2280 if (target->state != TARGET_HALTED)
2281 {
2282 command_print(cmd_ctx, "can't write registers while running");
2283 return ERROR_OK;
2284 }
2285
2286 if (argc < 3)
2287 {
2288 command_print(cmd_ctx, "usage: write_core_reg <num> <mode> <value>");
2289 return ERROR_OK;
2290 }
2291
2292 num = strtol(args[0], NULL, 0);
2293 mode = strtoul(args[1], NULL, 0);
2294 value = strtoul(args[2], NULL, 0);
2295
2296 arm7_9_write_core_reg(target, num, mode, value);
2297
2298 return ERROR_OK;
2299 }
2300
2301 int handle_arm7_9_sw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2302 {
2303 target_t *target = get_current_target(cmd_ctx);
2304 armv4_5_common_t *armv4_5;
2305 arm7_9_common_t *arm7_9;
2306
2307 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2308 {
2309 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2310 return ERROR_OK;
2311 }
2312
2313 if (argc == 0)
2314 {
2315 command_print(cmd_ctx, "software breakpoints %s", (arm7_9->sw_bkpts_enabled) ? "enabled" : "disabled");
2316 return ERROR_OK;
2317 }
2318
2319 if (strcmp("enable", args[0]) == 0)
2320 {
2321 if (arm7_9->sw_bkpts_use_wp)
2322 {
2323 arm7_9_enable_sw_bkpts(target);
2324 }
2325 else
2326 {
2327 arm7_9->sw_bkpts_enabled = 1;
2328 }
2329 }
2330 else if (strcmp("disable", args[0]) == 0)
2331 {
2332 if (arm7_9->sw_bkpts_use_wp)
2333 {
2334 arm7_9_disable_sw_bkpts(target);
2335 }
2336 else
2337 {
2338 arm7_9->sw_bkpts_enabled = 0;
2339 }
2340 }
2341 else
2342 {
2343 command_print(cmd_ctx, "usage: arm7_9 sw_bkpts <enable|disable>");
2344 }
2345
2346 command_print(cmd_ctx, "software breakpoints %s", (arm7_9->sw_bkpts_enabled) ? "enabled" : "disabled");
2347
2348 return ERROR_OK;
2349 }
2350
2351 int handle_arm7_9_force_hw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2352 {
2353 target_t *target = get_current_target(cmd_ctx);
2354 armv4_5_common_t *armv4_5;
2355 arm7_9_common_t *arm7_9;
2356
2357 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2358 {
2359 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2360 return ERROR_OK;
2361 }
2362
2363 if ((argc >= 1) && (strcmp("enable", args[0]) == 0))
2364 {
2365 arm7_9->force_hw_bkpts = 1;
2366 if (arm7_9->sw_bkpts_use_wp)
2367 {
2368 arm7_9_disable_sw_bkpts(target);
2369 }
2370 }
2371 else if ((argc >= 1) && (strcmp("disable", args[0]) == 0))
2372 {
2373 arm7_9->force_hw_bkpts = 0;
2374 }
2375 else
2376 {
2377 command_print(cmd_ctx, "usage: arm7_9 force_hw_bkpts <enable|disable>");
2378 }
2379
2380 command_print(cmd_ctx, "force hardware breakpoints %s", (arm7_9->force_hw_bkpts) ? "enabled" : "disabled");
2381
2382 return ERROR_OK;
2383 }
2384
2385 int handle_arm7_9_dbgrq_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2386 {
2387 target_t *target = get_current_target(cmd_ctx);
2388 armv4_5_common_t *armv4_5;
2389 arm7_9_common_t *arm7_9;
2390
2391 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2392 {
2393 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2394 return ERROR_OK;
2395 }
2396
2397 if (argc > 0)
2398 {
2399 if (strcmp("enable", args[0]) == 0)
2400 {
2401 arm7_9->use_dbgrq = 1;
2402 }
2403 else if (strcmp("disable", args[0]) == 0)
2404 {
2405 arm7_9->use_dbgrq = 0;
2406 }
2407 else
2408 {
2409 command_print(cmd_ctx, "usage: arm7_9 dbgrq <enable|disable>");
2410 }
2411 }
2412
2413 command_print(cmd_ctx, "use of EmbeddedICE dbgrq instead of breakpoint for target halt %s", (arm7_9->use_dbgrq) ? "enabled" : "disabled");
2414
2415 return ERROR_OK;
2416 }
2417
2418 int handle_arm7_9_fast_memory_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2419 {
2420 target_t *target = get_current_target(cmd_ctx);
2421 armv4_5_common_t *armv4_5;
2422 arm7_9_common_t *arm7_9;
2423
2424 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2425 {
2426 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2427 return ERROR_OK;
2428 }
2429
2430 if (argc > 0)
2431 {
2432 if (strcmp("enable", args[0]) == 0)
2433 {
2434 arm7_9->fast_memory_access = 1;
2435 }
2436 else if (strcmp("disable", args[0]) == 0)
2437 {
2438 arm7_9->fast_memory_access = 0;
2439 }
2440 else
2441 {
2442 command_print(cmd_ctx, "usage: arm7_9 fast_memory_access <enable|disable>");
2443 }
2444 }
2445
2446 command_print(cmd_ctx, "fast memory access is %s", (arm7_9->fast_memory_access) ? "enabled" : "disabled");
2447
2448 return ERROR_OK;
2449 }
2450
2451 int handle_arm7_9_dcc_downloads_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2452 {
2453 target_t *target = get_current_target(cmd_ctx);
2454 armv4_5_common_t *armv4_5;
2455 arm7_9_common_t *arm7_9;
2456
2457 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2458 {
2459 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2460 return ERROR_OK;
2461 }
2462
2463 if (argc > 0)
2464 {
2465 if (strcmp("enable", args[0]) == 0)
2466 {
2467 arm7_9->dcc_downloads = 1;
2468 }
2469 else if (strcmp("disable", args[0]) == 0)
2470 {
2471 arm7_9->dcc_downloads = 0;
2472 }
2473 else
2474 {
2475 command_print(cmd_ctx, "usage: arm7_9 dcc_downloads <enable|disable>");
2476 }
2477 }
2478
2479 command_print(cmd_ctx, "dcc downloads are %s", (arm7_9->dcc_downloads) ? "enabled" : "disabled");
2480
2481 return ERROR_OK;
2482 }
2483
2484 int arm7_9_init_arch_info(target_t *target, arm7_9_common_t *arm7_9)
2485 {
2486 armv4_5_common_t *armv4_5 = &arm7_9->armv4_5_common;
2487
2488 arm7_9->common_magic = ARM7_9_COMMON_MAGIC;
2489
2490 arm_jtag_setup_connection(&arm7_9->jtag_info);
2491 arm7_9->wp_available = 2;
2492 arm7_9->wp0_used = 0;
2493 arm7_9->wp1_used = 0;
2494 arm7_9->force_hw_bkpts = 0;
2495 arm7_9->use_dbgrq = 0;
2496
2497 arm7_9->etm_ctx = NULL;
2498 arm7_9->has_single_step = 0;
2499 arm7_9->has_monitor_mode = 0;
2500 arm7_9->has_vector_catch = 0;
2501
2502 arm7_9->reinit_embeddedice = 0;
2503
2504 arm7_9->debug_entry_from_reset = 0;
2505
2506 arm7_9->dcc_working_area = NULL;
2507
2508 arm7_9->fast_memory_access = 0;
2509 arm7_9->dcc_downloads = 0;
2510
2511 jtag_register_event_callback(arm7_9_jtag_callback, target);
2512
2513 armv4_5->arch_info = arm7_9;
2514 armv4_5->read_core_reg = arm7_9_read_core_reg;
2515 armv4_5->write_core_reg = arm7_9_write_core_reg;
2516 armv4_5->full_context = arm7_9_full_context;
2517
2518 armv4_5_init_arch_info(target, armv4_5);
2519
2520 target_register_timer_callback(arm7_9_handle_target_request, 1, 1, target);
2521
2522 return ERROR_OK;
2523 }
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