1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
24 #include "replacements.h"
26 #include "embeddedice.h"
32 #include "arm7_9_common.h"
33 #include "breakpoints.h"
39 #include <sys/types.h>
44 int arm7_9_debug_entry(target_t
*target
);
45 int arm7_9_enable_sw_bkpts(struct target_s
*target
);
47 /* command handler forward declarations */
48 int handle_arm7_9_write_xpsr_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
49 int handle_arm7_9_write_xpsr_im8_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
50 int handle_arm7_9_read_core_reg_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
51 int handle_arm7_9_write_core_reg_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
52 int handle_arm7_9_sw_bkpts_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
53 int handle_arm7_9_force_hw_bkpts_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
54 int handle_arm7_9_dbgrq_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
55 int handle_arm7_9_fast_memory_access_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
56 int handle_arm7_9_dcc_downloads_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
58 int arm7_9_reinit_embeddedice(target_t
*target
)
60 armv4_5_common_t
*armv4_5
= target
->arch_info
;
61 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
63 breakpoint_t
*breakpoint
= target
->breakpoints
;
65 arm7_9
->wp_available
= 2;
69 /* mark all hardware breakpoints as unset */
72 if (breakpoint
->type
== BKPT_HARD
)
76 breakpoint
= breakpoint
->next
;
79 if (arm7_9
->sw_bkpts_enabled
&& arm7_9
->sw_bkpts_use_wp
)
81 arm7_9
->sw_bkpts_enabled
= 0;
82 arm7_9_enable_sw_bkpts(target
);
85 arm7_9
->reinit_embeddedice
= 0;
90 int arm7_9_jtag_callback(enum jtag_event event
, void *priv
)
92 target_t
*target
= priv
;
93 armv4_5_common_t
*armv4_5
= target
->arch_info
;
94 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
96 /* a test-logic reset occured
97 * the EmbeddedICE registers have been reset
98 * hardware breakpoints have been cleared
100 if (event
== JTAG_TRST_ASSERTED
)
102 arm7_9
->reinit_embeddedice
= 1;
108 int arm7_9_get_arch_pointers(target_t
*target
, armv4_5_common_t
**armv4_5_p
, arm7_9_common_t
**arm7_9_p
)
110 armv4_5_common_t
*armv4_5
= target
->arch_info
;
111 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
113 if (armv4_5
->common_magic
!= ARMV4_5_COMMON_MAGIC
)
118 if (arm7_9
->common_magic
!= ARM7_9_COMMON_MAGIC
)
123 *armv4_5_p
= armv4_5
;
129 int arm7_9_set_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
)
131 armv4_5_common_t
*armv4_5
= target
->arch_info
;
132 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
134 if (target
->state
!= TARGET_HALTED
)
136 WARNING("target not halted");
137 return ERROR_TARGET_NOT_HALTED
;
140 if (arm7_9
->force_hw_bkpts
)
141 breakpoint
->type
= BKPT_HARD
;
145 WARNING("breakpoint already set");
149 if (breakpoint
->type
== BKPT_HARD
)
151 /* either an ARM (4 byte) or Thumb (2 byte) breakpoint */
152 u32 mask
= (breakpoint
->length
== 4) ? 0x3u
: 0x1u
;
153 if (!arm7_9
->wp0_used
)
155 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_VALUE
], breakpoint
->address
);
156 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_MASK
], mask
);
157 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_DATA_MASK
], 0xffffffffu
);
158 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_MASK
], ~EICE_W_CTRL_nOPC
& 0xff);
159 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
], EICE_W_CTRL_ENABLE
);
161 jtag_execute_queue();
162 arm7_9
->wp0_used
= 1;
165 else if (!arm7_9
->wp1_used
)
167 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_ADDR_VALUE
], breakpoint
->address
);
168 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_ADDR_MASK
], mask
);
169 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_DATA_MASK
], 0xffffffffu
);
170 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_MASK
], ~EICE_W_CTRL_nOPC
& 0xff);
171 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_VALUE
], EICE_W_CTRL_ENABLE
);
173 jtag_execute_queue();
174 arm7_9
->wp1_used
= 1;
179 ERROR("BUG: no hardware comparator available");
183 else if (breakpoint
->type
== BKPT_SOFT
)
185 if (breakpoint
->length
== 4)
187 /* keep the original instruction in target endianness */
188 target
->type
->read_memory(target
, breakpoint
->address
, 4, 1, breakpoint
->orig_instr
);
189 /* write the original instruction in target endianness (arm7_9->arm_bkpt is host endian) */
190 target_write_u32(target
, breakpoint
->address
, arm7_9
->arm_bkpt
);
194 /* keep the original instruction in target endianness */
195 target
->type
->read_memory(target
, breakpoint
->address
, 2, 1, breakpoint
->orig_instr
);
196 /* write the original instruction in target endianness (arm7_9->arm_bkpt is host endian) */
197 target_write_u32(target
, breakpoint
->address
, arm7_9
->thumb_bkpt
);
206 int arm7_9_unset_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
)
208 armv4_5_common_t
*armv4_5
= target
->arch_info
;
209 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
211 if (target
->state
!= TARGET_HALTED
)
213 WARNING("target not halted");
214 return ERROR_TARGET_NOT_HALTED
;
217 if (!breakpoint
->set
)
219 WARNING("breakpoint not set");
223 if (breakpoint
->type
== BKPT_HARD
)
225 if (breakpoint
->set
== 1)
227 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
], 0x0);
228 jtag_execute_queue();
229 arm7_9
->wp0_used
= 0;
231 else if (breakpoint
->set
== 2)
233 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_VALUE
], 0x0);
234 jtag_execute_queue();
235 arm7_9
->wp1_used
= 0;
241 /* restore original instruction (kept in target endianness) */
242 if (breakpoint
->length
== 4)
244 target
->type
->write_memory(target
, breakpoint
->address
, 4, 1, breakpoint
->orig_instr
);
248 target
->type
->write_memory(target
, breakpoint
->address
, 2, 1, breakpoint
->orig_instr
);
256 int arm7_9_add_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
)
258 armv4_5_common_t
*armv4_5
= target
->arch_info
;
259 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
261 if (target
->state
!= TARGET_HALTED
)
263 WARNING("target not halted");
264 return ERROR_TARGET_NOT_HALTED
;
267 if (arm7_9
->force_hw_bkpts
)
269 DEBUG("forcing use of hardware breakpoint at address 0x%8.8x", breakpoint
->address
);
270 breakpoint
->type
= BKPT_HARD
;
273 if ((breakpoint
->type
== BKPT_SOFT
) && (arm7_9
->sw_bkpts_enabled
== 0))
275 INFO("sw breakpoint requested, but software breakpoints not enabled");
276 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
279 if ((breakpoint
->type
== BKPT_HARD
) && (arm7_9
->wp_available
< 1))
281 INFO("no watchpoint unit available for hardware breakpoint");
282 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
285 if ((breakpoint
->length
!= 2) && (breakpoint
->length
!= 4))
287 INFO("only breakpoints of two (Thumb) or four (ARM) bytes length supported");
288 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
291 if (breakpoint
->type
== BKPT_HARD
)
292 arm7_9
->wp_available
--;
297 int arm7_9_remove_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
)
299 armv4_5_common_t
*armv4_5
= target
->arch_info
;
300 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
302 if (target
->state
!= TARGET_HALTED
)
304 WARNING("target not halted");
305 return ERROR_TARGET_NOT_HALTED
;
310 arm7_9_unset_breakpoint(target
, breakpoint
);
313 if (breakpoint
->type
== BKPT_HARD
)
314 arm7_9
->wp_available
++;
319 int arm7_9_set_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
)
321 armv4_5_common_t
*armv4_5
= target
->arch_info
;
322 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
326 mask
= watchpoint
->length
- 1;
328 if (target
->state
!= TARGET_HALTED
)
330 WARNING("target not halted");
331 return ERROR_TARGET_NOT_HALTED
;
334 if (watchpoint
->rw
== WPT_ACCESS
)
339 if (!arm7_9
->wp0_used
)
341 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_VALUE
], watchpoint
->address
);
342 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_MASK
], mask
);
343 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_DATA_MASK
], watchpoint
->mask
);
344 if( watchpoint
->mask
!= 0xffffffffu
)
345 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_DATA_VALUE
], watchpoint
->value
);
346 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_MASK
], 0xff & ~EICE_W_CTRL_nOPC
& ~rw_mask
);
347 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
], EICE_W_CTRL_ENABLE
| EICE_W_CTRL_nOPC
| (watchpoint
->rw
& 1));
349 jtag_execute_queue();
351 arm7_9
->wp0_used
= 2;
353 else if (!arm7_9
->wp1_used
)
355 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_ADDR_VALUE
], watchpoint
->address
);
356 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_ADDR_MASK
], mask
);
357 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_DATA_MASK
], watchpoint
->mask
);
358 if( watchpoint
->mask
!= 0xffffffffu
)
359 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_DATA_VALUE
], watchpoint
->value
);
360 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_MASK
], 0xff & ~EICE_W_CTRL_nOPC
& ~rw_mask
);
361 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_VALUE
], EICE_W_CTRL_ENABLE
| EICE_W_CTRL_nOPC
| (watchpoint
->rw
& 1));
363 jtag_execute_queue();
365 arm7_9
->wp1_used
= 2;
369 ERROR("BUG: no hardware comparator available");
376 int arm7_9_unset_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
)
378 armv4_5_common_t
*armv4_5
= target
->arch_info
;
379 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
381 if (target
->state
!= TARGET_HALTED
)
383 WARNING("target not halted");
384 return ERROR_TARGET_NOT_HALTED
;
387 if (!watchpoint
->set
)
389 WARNING("breakpoint not set");
393 if (watchpoint
->set
== 1)
395 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
], 0x0);
396 jtag_execute_queue();
397 arm7_9
->wp0_used
= 0;
399 else if (watchpoint
->set
== 2)
401 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_VALUE
], 0x0);
402 jtag_execute_queue();
403 arm7_9
->wp1_used
= 0;
410 int arm7_9_add_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
)
412 armv4_5_common_t
*armv4_5
= target
->arch_info
;
413 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
415 if (target
->state
!= TARGET_HALTED
)
417 WARNING("target not halted");
418 return ERROR_TARGET_NOT_HALTED
;
421 if (arm7_9
->wp_available
< 1)
423 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
426 if ((watchpoint
->length
!= 1) && (watchpoint
->length
!= 2) && (watchpoint
->length
!= 4))
428 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
431 arm7_9
->wp_available
--;
436 int arm7_9_remove_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
)
438 armv4_5_common_t
*armv4_5
= target
->arch_info
;
439 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
441 if (target
->state
!= TARGET_HALTED
)
443 WARNING("target not halted");
444 return ERROR_TARGET_NOT_HALTED
;
449 arm7_9_unset_watchpoint(target
, watchpoint
);
452 arm7_9
->wp_available
++;
457 int arm7_9_enable_sw_bkpts(struct target_s
*target
)
459 armv4_5_common_t
*armv4_5
= target
->arch_info
;
460 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
463 if (arm7_9
->sw_bkpts_enabled
)
466 if (arm7_9
->wp_available
< 1)
468 WARNING("can't enable sw breakpoints with no watchpoint unit available");
469 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
471 arm7_9
->wp_available
--;
473 if (!arm7_9
->wp0_used
)
475 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_DATA_VALUE
], arm7_9
->arm_bkpt
);
476 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_DATA_MASK
], 0x0);
477 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_MASK
], 0xffffffffu
);
478 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_MASK
], ~EICE_W_CTRL_nOPC
& 0xff);
479 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
], EICE_W_CTRL_ENABLE
);
480 arm7_9
->sw_bkpts_enabled
= 1;
481 arm7_9
->wp0_used
= 3;
483 else if (!arm7_9
->wp1_used
)
485 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_DATA_VALUE
], arm7_9
->arm_bkpt
);
486 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_DATA_MASK
], 0x0);
487 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_ADDR_MASK
], 0xffffffffu
);
488 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_MASK
], ~EICE_W_CTRL_nOPC
& 0xff);
489 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_VALUE
], EICE_W_CTRL_ENABLE
);
490 arm7_9
->sw_bkpts_enabled
= 2;
491 arm7_9
->wp1_used
= 3;
495 ERROR("BUG: both watchpoints used, but wp_available >= 1");
499 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
501 ERROR("error writing EmbeddedICE registers to enable sw breakpoints");
508 int arm7_9_disable_sw_bkpts(struct target_s
*target
)
510 armv4_5_common_t
*armv4_5
= target
->arch_info
;
511 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
513 if (!arm7_9
->sw_bkpts_enabled
)
516 if (arm7_9
->sw_bkpts_enabled
== 1)
518 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
], 0x0);
519 arm7_9
->sw_bkpts_enabled
= 0;
520 arm7_9
->wp0_used
= 0;
521 arm7_9
->wp_available
++;
523 else if (arm7_9
->sw_bkpts_enabled
== 2)
525 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_VALUE
], 0x0);
526 arm7_9
->sw_bkpts_enabled
= 0;
527 arm7_9
->wp1_used
= 0;
528 arm7_9
->wp_available
++;
534 int arm7_9_execute_sys_speed(struct target_s
*target
)
539 armv4_5_common_t
*armv4_5
= target
->arch_info
;
540 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
541 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
542 reg_t
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
544 /* set RESTART instruction */
545 jtag_add_end_state(TAP_RTI
);
546 arm_jtag_set_instr(jtag_info
, 0x4);
548 for (timeout
=0; timeout
<50; timeout
++)
550 /* read debug status register */
551 embeddedice_read_reg(dbg_stat
);
552 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
554 if ((buf_get_u32(dbg_stat
->value
, EICE_DBG_STATUS_DBGACK
, 1))
555 && (buf_get_u32(dbg_stat
->value
, EICE_DBG_STATUS_SYSCOMP
, 1)))
561 ERROR("timeout waiting for SYSCOMP & DBGACK, last DBG_STATUS: %x", buf_get_u32(dbg_stat
->value
, 0, dbg_stat
->size
));
562 return ERROR_TARGET_TIMEOUT
;
568 int arm7_9_execute_fast_sys_speed(struct target_s
*target
)
570 u8 check_value
[4], check_mask
[4];
572 armv4_5_common_t
*armv4_5
= target
->arch_info
;
573 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
574 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
575 reg_t
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
577 /* set RESTART instruction */
578 jtag_add_end_state(TAP_RTI
);
579 arm_jtag_set_instr(jtag_info
, 0x4);
581 /* check for DBGACK and SYSCOMP set (others don't care) */
582 buf_set_u32(check_value
, 0, 32, 0x9);
583 buf_set_u32(check_mask
, 0, 32, 0x9);
585 /* read debug status register */
586 embeddedice_read_reg_w_check(dbg_stat
, check_value
, check_value
);
591 enum target_state
arm7_9_poll(target_t
*target
)
594 armv4_5_common_t
*armv4_5
= target
->arch_info
;
595 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
596 reg_t
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
598 if (arm7_9
->reinit_embeddedice
)
600 arm7_9_reinit_embeddedice(target
);
603 /* read debug status register */
604 embeddedice_read_reg(dbg_stat
);
605 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
609 case ERROR_JTAG_QUEUE_FAILED
:
610 ERROR("JTAG queue failed while reading EmbeddedICE status register");
618 if (buf_get_u32(dbg_stat
->value
, EICE_DBG_STATUS_DBGACK
, 1))
620 DEBUG("DBGACK set, dbg_state->value: 0x%x", buf_get_u32(dbg_stat
->value
, 0, 32));
621 if ((target
->state
== TARGET_UNKNOWN
))
623 WARNING("DBGACK set while target was in unknown state. Reset or initialize target before resuming");
624 target
->state
= TARGET_RUNNING
;
626 if ((target
->state
== TARGET_RUNNING
) || (target
->state
== TARGET_RESET
))
628 target
->state
= TARGET_HALTED
;
629 if ((retval
= arm7_9_debug_entry(target
)) != ERROR_OK
)
632 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
634 if (target
->state
== TARGET_DEBUG_RUNNING
)
636 target
->state
= TARGET_HALTED
;
637 if ((retval
= arm7_9_debug_entry(target
)) != ERROR_OK
)
640 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_HALTED
);
645 if (target
->state
!= TARGET_DEBUG_RUNNING
)
646 target
->state
= TARGET_RUNNING
;
649 return target
->state
;
652 int arm7_9_assert_reset(target_t
*target
)
656 DEBUG("target->state: %s", target_state_strings
[target
->state
]);
658 if (target
->state
== TARGET_HALTED
|| target
->state
== TARGET_UNKNOWN
)
660 /* if the target wasn't running, there might be working areas allocated */
661 target_free_all_working_areas(target
);
663 /* assert SRST and TRST */
664 /* system would get ouf sync if we didn't reset test-logic, too */
665 if ((retval
= jtag_add_reset(1, 1)) != ERROR_OK
)
667 if (retval
== ERROR_JTAG_RESET_CANT_SRST
)
669 WARNING("can't assert srst");
674 ERROR("unknown error");
678 jtag_add_sleep(5000);
679 if ((retval
= jtag_add_reset(0, 1)) != ERROR_OK
)
681 if (retval
== ERROR_JTAG_RESET_WOULD_ASSERT_TRST
)
683 WARNING("srst resets test logic, too");
684 retval
= jtag_add_reset(1, 1);
690 if ((retval
= jtag_add_reset(0, 1)) != ERROR_OK
)
692 if (retval
== ERROR_JTAG_RESET_WOULD_ASSERT_TRST
)
694 WARNING("srst resets test logic, too");
695 retval
= jtag_add_reset(1, 1);
698 if (retval
== ERROR_JTAG_RESET_CANT_SRST
)
700 WARNING("can't assert srst");
703 else if (retval
!= ERROR_OK
)
705 ERROR("unknown error");
711 target
->state
= TARGET_RESET
;
712 jtag_add_sleep(50000);
714 armv4_5_invalidate_core_regs(target
);
720 int arm7_9_deassert_reset(target_t
*target
)
722 DEBUG("target->state: %s", target_state_strings
[target
->state
]);
724 /* deassert reset lines */
725 jtag_add_reset(0, 0);
731 int arm7_9_clear_halt(target_t
*target
)
733 armv4_5_common_t
*armv4_5
= target
->arch_info
;
734 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
735 reg_t
*dbg_ctrl
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_CTRL
];
737 if (arm7_9
->use_dbgrq
)
739 /* program EmbeddedICE Debug Control Register to deassert DBGRQ
741 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_DBGRQ
, 1, 0);
742 embeddedice_store_reg(dbg_ctrl
);
746 /* restore registers if watchpoint unit 0 was in use
748 if (arm7_9
->wp0_used
)
750 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_MASK
]);
751 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_DATA_MASK
]);
752 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_MASK
]);
754 /* control value always has to be restored, as it was either disabled,
755 * or enabled with possibly different bits
757 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
]);
763 int arm7_9_soft_reset_halt(struct target_s
*target
)
765 armv4_5_common_t
*armv4_5
= target
->arch_info
;
766 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
767 reg_t
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
768 reg_t
*dbg_ctrl
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_CTRL
];
771 if (target
->state
== TARGET_RUNNING
)
773 target
->type
->halt(target
);
776 while (buf_get_u32(dbg_stat
->value
, EICE_DBG_CONTROL_DBGACK
, 1) == 0)
778 embeddedice_read_reg(dbg_stat
);
779 jtag_execute_queue();
781 target
->state
= TARGET_HALTED
;
783 /* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS
784 * ensure that DBGRQ is cleared
786 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_DBGACK
, 1, 1);
787 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_DBGRQ
, 1, 0);
788 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_INTDIS
, 1, 1);
789 embeddedice_store_reg(dbg_ctrl
);
791 arm7_9_clear_halt(target
);
793 /* if the target is in Thumb state, change to ARM state */
794 if (buf_get_u32(dbg_stat
->value
, EICE_DBG_STATUS_ITBIT
, 1))
796 u32 r0_thumb
, pc_thumb
;
797 DEBUG("target entered debug from Thumb state, changing to ARM");
798 /* Entered debug from Thumb mode */
799 armv4_5
->core_state
= ARMV4_5_STATE_THUMB
;
800 arm7_9
->change_to_arm(target
, &r0_thumb
, &pc_thumb
);
803 /* all register content is now invalid */
804 armv4_5_invalidate_core_regs(target
);
806 /* SVC, ARM state, IRQ and FIQ disabled */
807 buf_set_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8, 0xd3);
808 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].dirty
= 1;
809 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].valid
= 1;
811 /* start fetching from 0x0 */
812 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, 0x0);
813 armv4_5
->core_cache
->reg_list
[15].dirty
= 1;
814 armv4_5
->core_cache
->reg_list
[15].valid
= 1;
816 armv4_5
->core_mode
= ARMV4_5_MODE_SVC
;
817 armv4_5
->core_state
= ARMV4_5_STATE_ARM
;
819 /* reset registers */
820 for (i
= 0; i
<= 14; i
++)
822 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).value
, 0, 32, 0xffffffff);
823 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).dirty
= 1;
824 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).valid
= 1;
827 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
832 int arm7_9_halt(target_t
*target
)
834 armv4_5_common_t
*armv4_5
= target
->arch_info
;
835 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
836 reg_t
*dbg_ctrl
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_CTRL
];
838 DEBUG("target->state: %s", target_state_strings
[target
->state
]);
840 if (target
->state
== TARGET_HALTED
)
842 WARNING("target was already halted");
843 return ERROR_TARGET_ALREADY_HALTED
;
846 if (target
->state
== TARGET_UNKNOWN
)
848 WARNING("target was in unknown state when halt was requested");
851 if ((target
->state
== TARGET_RESET
) && (jtag_reset_config
& RESET_SRST_PULLS_TRST
) && (jtag_srst
))
853 ERROR("can't request a halt while in reset if nSRST pulls nTRST");
854 return ERROR_TARGET_FAILURE
;
857 if (arm7_9
->use_dbgrq
)
859 /* program EmbeddedICE Debug Control Register to assert DBGRQ
861 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_DBGRQ
, 1, 1);
862 embeddedice_store_reg(dbg_ctrl
);
866 /* program watchpoint unit to match on any address
868 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_MASK
], 0xffffffff);
869 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_DATA_MASK
], 0xffffffff);
870 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
], 0x100);
871 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_MASK
], 0xf7);
874 target
->debug_reason
= DBG_REASON_DBGRQ
;
879 int arm7_9_debug_entry(target_t
*target
)
884 u32 r0_thumb
, pc_thumb
;
887 /* get pointers to arch-specific information */
888 armv4_5_common_t
*armv4_5
= target
->arch_info
;
889 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
890 reg_t
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
891 reg_t
*dbg_ctrl
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_CTRL
];
893 #ifdef _DEBUG_ARM7_9_
897 if (arm7_9
->pre_debug_entry
)
898 arm7_9
->pre_debug_entry(target
);
900 /* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS
901 * ensure that DBGRQ is cleared
903 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_DBGACK
, 1, 1);
904 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_DBGRQ
, 1, 0);
905 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_INTDIS
, 1, 1);
906 embeddedice_store_reg(dbg_ctrl
);
908 arm7_9_clear_halt(target
);
910 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
914 case ERROR_JTAG_QUEUE_FAILED
:
915 ERROR("JTAG queue failed while writing EmbeddedICE control register");
923 if ((retval
= arm7_9
->examine_debug_reason(target
)) != ERROR_OK
)
927 if (target
->state
!= TARGET_HALTED
)
929 WARNING("target not halted");
930 return ERROR_TARGET_NOT_HALTED
;
933 /* if the target is in Thumb state, change to ARM state */
934 if (buf_get_u32(dbg_stat
->value
, EICE_DBG_STATUS_ITBIT
, 1))
936 DEBUG("target entered debug from Thumb state");
937 /* Entered debug from Thumb mode */
938 armv4_5
->core_state
= ARMV4_5_STATE_THUMB
;
939 arm7_9
->change_to_arm(target
, &r0_thumb
, &pc_thumb
);
940 DEBUG("r0_thumb: 0x%8.8x, pc_thumb: 0x%8.8x", r0_thumb
, pc_thumb
);
944 DEBUG("target entered debug from ARM state");
945 /* Entered debug from ARM mode */
946 armv4_5
->core_state
= ARMV4_5_STATE_ARM
;
949 for (i
= 0; i
< 16; i
++)
950 context_p
[i
] = &context
[i
];
951 /* save core registers (r0 - r15 of current core mode) */
952 arm7_9
->read_core_regs(target
, 0xffff, context_p
);
954 arm7_9
->read_xpsr(target
, &cpsr
, 0);
956 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
959 /* if the core has been executing in Thumb state, set the T bit */
960 if (armv4_5
->core_state
== ARMV4_5_STATE_THUMB
)
963 buf_set_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32, cpsr
);
964 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].dirty
= 0;
965 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].valid
= 1;
967 armv4_5
->core_mode
= cpsr
& 0x1f;
969 if (armv4_5_mode_to_number(armv4_5
->core_mode
) == -1)
971 target
->state
= TARGET_UNKNOWN
;
972 ERROR("cpsr contains invalid mode value - communication failure");
973 return ERROR_TARGET_FAILURE
;
976 DEBUG("target entered debug state in %s mode", armv4_5_mode_strings
[armv4_5_mode_to_number(armv4_5
->core_mode
)]);
978 if (armv4_5
->core_state
== ARMV4_5_STATE_THUMB
)
980 DEBUG("thumb state, applying fixups");
981 context
[0] = r0_thumb
;
982 context
[15] = pc_thumb
;
983 } else if (armv4_5
->core_state
== ARMV4_5_STATE_ARM
)
985 /* adjust value stored by STM */
986 context
[15] -= 3 * 4;
989 if ((target
->debug_reason
== DBG_REASON_BREAKPOINT
)
990 || (target
->debug_reason
== DBG_REASON_SINGLESTEP
)
991 || (target
->debug_reason
== DBG_REASON_WATCHPOINT
)
992 || (target
->debug_reason
== DBG_REASON_WPTANDBKPT
)
993 || ((target
->debug_reason
== DBG_REASON_DBGRQ
) && (arm7_9
->use_dbgrq
== 0)))
994 context
[15] -= 3 * ((armv4_5
->core_state
== ARMV4_5_STATE_ARM
) ? 4 : 2);
995 else if (target
->debug_reason
== DBG_REASON_DBGRQ
)
996 context
[15] -= arm7_9
->dbgreq_adjust_pc
* ((armv4_5
->core_state
== ARMV4_5_STATE_ARM
) ? 4 : 2);
999 ERROR("unknown debug reason: %i", target
->debug_reason
);
1003 for (i
=0; i
<=15; i
++)
1005 DEBUG("r%i: 0x%8.8x", i
, context
[i
]);
1006 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).value
, 0, 32, context
[i
]);
1007 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).dirty
= 0;
1008 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).valid
= 1;
1011 DEBUG("entered debug state at PC 0x%x", context
[15]);
1013 /* exceptions other than USR & SYS have a saved program status register */
1014 if ((armv4_5_mode_to_number(armv4_5
->core_mode
) != ARMV4_5_MODE_USR
) && (armv4_5_mode_to_number(armv4_5
->core_mode
) != ARMV4_5_MODE_SYS
))
1017 arm7_9
->read_xpsr(target
, &spsr
, 1);
1018 jtag_execute_queue();
1019 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 16).value
, 0, 32, spsr
);
1020 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 16).dirty
= 0;
1021 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 16).valid
= 1;
1024 /* r0 and r15 (pc) have to be restored later */
1025 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 0).dirty
= 1;
1026 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 15).dirty
= 1;
1028 if ((retval
= jtag
->execute_queue()) != ERROR_OK
)
1031 if (arm7_9
->post_debug_entry
)
1032 arm7_9
->post_debug_entry(target
);
1037 int arm7_9_full_context(target_t
*target
)
1041 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1042 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
1046 if (target
->state
!= TARGET_HALTED
)
1048 WARNING("target not halted");
1049 return ERROR_TARGET_NOT_HALTED
;
1052 /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
1053 * SYS shares registers with User, so we don't touch SYS
1055 for(i
= 0; i
< 6; i
++)
1062 /* check if there are invalid registers in the current mode
1064 for (j
= 0; j
<= 16; j
++)
1066 if (ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).valid
== 0)
1074 /* change processor mode (and mask T bit) */
1075 tmp_cpsr
= buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8) & 0xE0;
1076 tmp_cpsr
|= armv4_5_number_to_mode(i
);
1078 arm7_9
->write_xpsr_im8(target
, tmp_cpsr
& 0xff, 0, 0);
1080 for (j
= 0; j
< 15; j
++)
1082 if (ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).valid
== 0)
1084 reg_p
[j
] = (u32
*)ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).value
;
1086 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).valid
= 1;
1087 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).dirty
= 0;
1091 /* if only the PSR is invalid, mask is all zeroes */
1093 arm7_9
->read_core_regs(target
, mask
, reg_p
);
1095 /* check if the PSR has to be read */
1096 if (ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), 16).valid
== 0)
1098 arm7_9
->read_xpsr(target
, (u32
*)ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), 16).value
, 1);
1099 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), 16).valid
= 1;
1100 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), 16).dirty
= 0;
1105 /* restore processor mode (mask T bit) */
1106 arm7_9
->write_xpsr_im8(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8) & ~0x20, 0, 0);
1108 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1110 ERROR("JTAG failure");
1116 int arm7_9_restore_context(target_t
*target
)
1118 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1119 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
1121 armv4_5_core_reg_t
*reg_arch_info
;
1122 enum armv4_5_mode current_mode
= armv4_5
->core_mode
;
1129 if (target
->state
!= TARGET_HALTED
)
1131 WARNING("target not halted");
1132 return ERROR_TARGET_NOT_HALTED
;
1135 if (arm7_9
->pre_restore_context
)
1136 arm7_9
->pre_restore_context(target
);
1138 /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
1139 * SYS shares registers with User, so we don't touch SYS
1141 for (i
= 0; i
< 6; i
++)
1143 DEBUG("examining %s mode", armv4_5_mode_strings
[i
]);
1146 /* check if there are dirty registers in the current mode
1148 for (j
= 0; j
<= 16; j
++)
1150 reg
= &ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
);
1151 reg_arch_info
= reg
->arch_info
;
1152 if (reg
->dirty
== 1)
1154 if (reg
->valid
== 1)
1157 DEBUG("examining dirty reg: %s", reg
->name
);
1158 if ((reg_arch_info
->mode
!= ARMV4_5_MODE_ANY
)
1159 && (reg_arch_info
->mode
!= current_mode
)
1160 && !((reg_arch_info
->mode
== ARMV4_5_MODE_USR
) && (armv4_5
->core_mode
== ARMV4_5_MODE_SYS
))
1161 && !((reg_arch_info
->mode
== ARMV4_5_MODE_SYS
) && (armv4_5
->core_mode
== ARMV4_5_MODE_USR
)))
1164 DEBUG("require mode change");
1169 ERROR("BUG: dirty register '%s', but no valid data", reg
->name
);
1185 /* change processor mode (mask T bit) */
1186 tmp_cpsr
= buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8) & 0xE0;
1187 tmp_cpsr
|= armv4_5_number_to_mode(i
);
1189 arm7_9
->write_xpsr_im8(target
, tmp_cpsr
& 0xff, 0, 0);
1190 current_mode
= armv4_5_number_to_mode(i
);
1193 for (j
= 0; j
<= 14; j
++)
1195 reg
= &ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
);
1196 reg_arch_info
= reg
->arch_info
;
1199 if (reg
->dirty
== 1)
1201 regs
[j
] = buf_get_u32(reg
->value
, 0, 32);
1206 DEBUG("writing register %i of mode %s with value 0x%8.8x", j
, armv4_5_mode_strings
[i
], regs
[j
]);
1212 arm7_9
->write_core_regs(target
, mask
, regs
);
1215 reg
= &ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), 16);
1216 reg_arch_info
= reg
->arch_info
;
1217 if ((reg
->dirty
) && (reg_arch_info
->mode
!= ARMV4_5_MODE_ANY
))
1219 DEBUG("writing SPSR of mode %i with value 0x%8.8x", i
, buf_get_u32(reg
->value
, 0, 32));
1220 arm7_9
->write_xpsr(target
, buf_get_u32(reg
->value
, 0, 32), 1);
1225 if ((armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].dirty
== 0) && (armv4_5
->core_mode
!= current_mode
))
1227 /* restore processor mode (mask T bit) */
1230 tmp_cpsr
= buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8) & 0xE0;
1231 tmp_cpsr
|= armv4_5_number_to_mode(i
);
1233 DEBUG("writing lower 8 bit of cpsr with value 0x%2.2x", tmp_cpsr
);
1234 arm7_9
->write_xpsr_im8(target
, tmp_cpsr
& 0xff, 0, 0);
1236 else if (armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].dirty
== 1)
1238 /* CPSR has been changed, full restore necessary (mask T bit) */
1239 DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32));
1240 arm7_9
->write_xpsr(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32) & ~0x20, 0);
1241 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].dirty
= 0;
1242 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].valid
= 1;
1246 DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32));
1247 arm7_9
->write_pc(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32));
1248 armv4_5
->core_cache
->reg_list
[15].dirty
= 0;
1250 if (arm7_9
->post_restore_context
)
1251 arm7_9
->post_restore_context(target
);
1256 int arm7_9_restart_core(struct target_s
*target
)
1258 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1259 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
1260 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
1262 /* set RESTART instruction */
1263 jtag_add_end_state(TAP_RTI
);
1264 arm_jtag_set_instr(jtag_info
, 0x4);
1266 jtag_add_runtest(1, TAP_RTI
);
1267 if ((jtag_execute_queue()) != ERROR_OK
)
1275 void arm7_9_enable_watchpoints(struct target_s
*target
)
1277 watchpoint_t
*watchpoint
= target
->watchpoints
;
1281 if (watchpoint
->set
== 0)
1282 arm7_9_set_watchpoint(target
, watchpoint
);
1283 watchpoint
= watchpoint
->next
;
1287 void arm7_9_enable_breakpoints(struct target_s
*target
)
1289 breakpoint_t
*breakpoint
= target
->breakpoints
;
1291 /* set any pending breakpoints */
1294 if (breakpoint
->set
== 0)
1295 arm7_9_set_breakpoint(target
, breakpoint
);
1296 breakpoint
= breakpoint
->next
;
1300 void arm7_9_disable_bkpts_and_wpts(struct target_s
*target
)
1302 breakpoint_t
*breakpoint
= target
->breakpoints
;
1303 watchpoint_t
*watchpoint
= target
->watchpoints
;
1305 /* set any pending breakpoints */
1308 if (breakpoint
->set
!= 0)
1309 arm7_9_unset_breakpoint(target
, breakpoint
);
1310 breakpoint
= breakpoint
->next
;
1315 if (watchpoint
->set
!= 0)
1316 arm7_9_unset_watchpoint(target
, watchpoint
);
1317 watchpoint
= watchpoint
->next
;
1321 int arm7_9_resume(struct target_s
*target
, int current
, u32 address
, int handle_breakpoints
, int debug_execution
)
1323 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1324 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
1325 breakpoint_t
*breakpoint
= target
->breakpoints
;
1326 reg_t
*dbg_ctrl
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_CTRL
];
1330 if (target
->state
!= TARGET_HALTED
)
1332 WARNING("target not halted");
1333 return ERROR_TARGET_NOT_HALTED
;
1336 if (!debug_execution
)
1338 target_free_all_working_areas(target
);
1341 /* current = 1: continue on current pc, otherwise continue at <address> */
1343 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, address
);
1345 /* the front-end may request us not to handle breakpoints */
1346 if (handle_breakpoints
)
1348 if ((breakpoint
= breakpoint_find(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32))))
1350 DEBUG("unset breakpoint at 0x%8.8x", breakpoint
->address
);
1351 arm7_9_unset_breakpoint(target
, breakpoint
);
1353 DEBUG("enable single-step");
1354 arm7_9
->enable_single_step(target
);
1356 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
1358 arm7_9_restore_context(target
);
1360 if (armv4_5
->core_state
== ARMV4_5_STATE_ARM
)
1361 arm7_9
->branch_resume(target
);
1362 else if (armv4_5
->core_state
== ARMV4_5_STATE_THUMB
)
1364 arm7_9
->branch_resume_thumb(target
);
1368 ERROR("unhandled core state");
1372 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_DBGACK
, 1, 0);
1373 embeddedice_write_reg(dbg_ctrl
, buf_get_u32(dbg_ctrl
->value
, 0, dbg_ctrl
->size
));
1374 arm7_9_execute_sys_speed(target
);
1376 DEBUG("disable single-step");
1377 arm7_9
->disable_single_step(target
);
1379 arm7_9_debug_entry(target
);
1380 DEBUG("new PC after step: 0x%8.8x", buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32));
1382 DEBUG("set breakpoint at 0x%8.8x", breakpoint
->address
);
1383 arm7_9_set_breakpoint(target
, breakpoint
);
1387 /* enable any pending breakpoints and watchpoints */
1388 arm7_9_enable_breakpoints(target
);
1389 arm7_9_enable_watchpoints(target
);
1391 arm7_9_restore_context(target
);
1393 if (armv4_5
->core_state
== ARMV4_5_STATE_ARM
)
1395 arm7_9
->branch_resume(target
);
1397 else if (armv4_5
->core_state
== ARMV4_5_STATE_THUMB
)
1399 arm7_9
->branch_resume_thumb(target
);
1403 ERROR("unhandled core state");
1407 /* deassert DBGACK and INTDIS */
1408 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_DBGACK
, 1, 0);
1409 /* INTDIS only when we really resume, not during debug execution */
1410 if (!debug_execution
)
1411 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_INTDIS
, 1, 0);
1412 embeddedice_write_reg(dbg_ctrl
, buf_get_u32(dbg_ctrl
->value
, 0, dbg_ctrl
->size
));
1414 arm7_9_restart_core(target
);
1416 target
->debug_reason
= DBG_REASON_NOTHALTED
;
1418 if (!debug_execution
)
1420 /* registers are now invalid */
1421 armv4_5_invalidate_core_regs(target
);
1422 target
->state
= TARGET_RUNNING
;
1423 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
1427 target
->state
= TARGET_DEBUG_RUNNING
;
1428 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_RESUMED
);
1431 DEBUG("target resumed");
1436 void arm7_9_enable_eice_step(target_t
*target
)
1438 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1439 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
1441 /* setup an inverse breakpoint on the current PC
1442 * - comparator 1 matches the current address
1443 * - rangeout from comparator 1 is connected to comparator 0 rangein
1444 * - comparator 0 matches any address, as long as rangein is low */
1445 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_MASK
], 0xffffffff);
1446 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_DATA_MASK
], 0xffffffff);
1447 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
], 0x100);
1448 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_MASK
], 0x77);
1449 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_ADDR_VALUE
], buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32));
1450 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_ADDR_MASK
], 0);
1451 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_DATA_MASK
], 0xffffffff);
1452 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_VALUE
], 0x0);
1453 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_MASK
], 0xf7);
1456 void arm7_9_disable_eice_step(target_t
*target
)
1458 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1459 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
1461 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_MASK
]);
1462 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_DATA_MASK
]);
1463 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
]);
1464 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_MASK
]);
1465 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_ADDR_VALUE
]);
1466 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_ADDR_MASK
]);
1467 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_DATA_MASK
]);
1468 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_MASK
]);
1469 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_VALUE
]);
1472 int arm7_9_step(struct target_s
*target
, int current
, u32 address
, int handle_breakpoints
)
1474 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1475 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
1476 breakpoint_t
*breakpoint
= NULL
;
1478 if (target
->state
!= TARGET_HALTED
)
1480 WARNING("target not halted");
1481 return ERROR_TARGET_NOT_HALTED
;
1484 /* current = 1: continue on current pc, otherwise continue at <address> */
1486 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, address
);
1488 /* the front-end may request us not to handle breakpoints */
1489 if (handle_breakpoints
)
1490 if ((breakpoint
= breakpoint_find(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32))))
1491 arm7_9_unset_breakpoint(target
, breakpoint
);
1493 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
1495 arm7_9_restore_context(target
);
1497 arm7_9
->enable_single_step(target
);
1499 if (armv4_5
->core_state
== ARMV4_5_STATE_ARM
)
1501 arm7_9
->branch_resume(target
);
1503 else if (armv4_5
->core_state
== ARMV4_5_STATE_THUMB
)
1505 arm7_9
->branch_resume_thumb(target
);
1509 ERROR("unhandled core state");
1513 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
1515 arm7_9_execute_sys_speed(target
);
1516 arm7_9
->disable_single_step(target
);
1518 /* registers are now invalid */
1519 armv4_5_invalidate_core_regs(target
);
1521 arm7_9_debug_entry(target
);
1523 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
1526 arm7_9_set_breakpoint(target
, breakpoint
);
1528 DEBUG("target stepped");
1534 int arm7_9_read_core_reg(struct target_s
*target
, int num
, enum armv4_5_mode mode
)
1539 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1540 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
1541 enum armv4_5_mode reg_mode
= ((armv4_5_core_reg_t
*)ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, mode
, num
).arch_info
)->mode
;
1543 if ((num
< 0) || (num
> 16))
1544 return ERROR_INVALID_ARGUMENTS
;
1546 if ((mode
!= ARMV4_5_MODE_ANY
)
1547 && (mode
!= armv4_5
->core_mode
)
1548 && (reg_mode
!= ARMV4_5_MODE_ANY
))
1552 /* change processor mode (mask T bit) */
1553 tmp_cpsr
= buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8) & 0xE0;
1556 arm7_9
->write_xpsr_im8(target
, tmp_cpsr
& 0xff, 0, 0);
1559 if ((num
>= 0) && (num
<= 15))
1561 /* read a normal core register */
1562 reg_p
[num
] = &value
;
1564 arm7_9
->read_core_regs(target
, 1 << num
, reg_p
);
1568 /* read a program status register
1569 * if the register mode is MODE_ANY, we read the cpsr, otherwise a spsr
1571 armv4_5_core_reg_t
*arch_info
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, mode
, num
).arch_info
;
1572 int spsr
= (arch_info
->mode
== ARMV4_5_MODE_ANY
) ? 0 : 1;
1574 arm7_9
->read_xpsr(target
, &value
, spsr
);
1577 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1579 ERROR("JTAG failure");
1583 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, mode
, num
).valid
= 1;
1584 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, mode
, num
).dirty
= 0;
1585 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, mode
, num
).value
, 0, 32, value
);
1587 if ((mode
!= ARMV4_5_MODE_ANY
)
1588 && (mode
!= armv4_5
->core_mode
)
1589 && (reg_mode
!= ARMV4_5_MODE_ANY
)) {
1590 /* restore processor mode (mask T bit) */
1591 arm7_9
->write_xpsr_im8(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8) & ~0x20, 0, 0);
1598 int arm7_9_write_core_reg(struct target_s
*target
, int num
, enum armv4_5_mode mode
, u32 value
)
1602 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1603 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
1604 enum armv4_5_mode reg_mode
= ((armv4_5_core_reg_t
*)ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, mode
, num
).arch_info
)->mode
;
1606 if ((num
< 0) || (num
> 16))
1607 return ERROR_INVALID_ARGUMENTS
;
1609 if ((mode
!= ARMV4_5_MODE_ANY
)
1610 && (mode
!= armv4_5
->core_mode
)
1611 && (reg_mode
!= ARMV4_5_MODE_ANY
)) {
1614 /* change processor mode (mask T bit) */
1615 tmp_cpsr
= buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8) & 0xE0;
1618 arm7_9
->write_xpsr_im8(target
, tmp_cpsr
& 0xff, 0, 0);
1621 if ((num
>= 0) && (num
<= 15))
1623 /* write a normal core register */
1626 arm7_9
->write_core_regs(target
, 1 << num
, reg
);
1630 /* write a program status register
1631 * if the register mode is MODE_ANY, we write the cpsr, otherwise a spsr
1633 armv4_5_core_reg_t
*arch_info
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, mode
, num
).arch_info
;
1634 int spsr
= (arch_info
->mode
== ARMV4_5_MODE_ANY
) ? 0 : 1;
1636 /* if we're writing the CPSR, mask the T bit */
1640 arm7_9
->write_xpsr(target
, value
, spsr
);
1643 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, mode
, num
).valid
= 1;
1644 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, mode
, num
).dirty
= 0;
1646 if ((mode
!= ARMV4_5_MODE_ANY
)
1647 && (mode
!= armv4_5
->core_mode
)
1648 && (reg_mode
!= ARMV4_5_MODE_ANY
)) {
1649 /* restore processor mode (mask T bit) */
1650 arm7_9
->write_xpsr_im8(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8) & ~0x20, 0, 0);
1653 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1655 ERROR("JTAG failure");
1663 int arm7_9_read_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
)
1665 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1666 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
1669 int num_accesses
= 0;
1670 int thisrun_accesses
;
1676 DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address
, size
, count
);
1678 if (target
->state
!= TARGET_HALTED
)
1680 WARNING("target not halted");
1681 return ERROR_TARGET_NOT_HALTED
;
1684 /* sanitize arguments */
1685 if (((size
!= 4) && (size
!= 2) && (size
!= 1)) || (count
== 0) || !(buffer
))
1686 return ERROR_INVALID_ARGUMENTS
;
1688 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
1689 return ERROR_TARGET_UNALIGNED_ACCESS
;
1691 /* load the base register with the address of the first word */
1693 arm7_9
->write_core_regs(target
, 0x1, reg
);
1698 while (num_accesses
< count
)
1701 thisrun_accesses
= ((count
- num_accesses
) >= 14) ? 14 : (count
- num_accesses
);
1702 reg_list
= (0xffff >> (15 - thisrun_accesses
)) & 0xfffe;
1704 if (last_reg
<= thisrun_accesses
)
1705 last_reg
= thisrun_accesses
;
1707 arm7_9
->load_word_regs(target
, reg_list
);
1709 /* fast memory reads are only safe when the target is running
1710 * from a sufficiently high clock (32 kHz is usually too slow)
1712 if (arm7_9
->fast_memory_access
)
1713 arm7_9_execute_fast_sys_speed(target
);
1715 arm7_9_execute_sys_speed(target
);
1717 arm7_9
->read_core_regs_target_buffer(target
, reg_list
, buffer
, 4);
1719 /* advance buffer, count number of accesses */
1720 buffer
+= thisrun_accesses
* 4;
1721 num_accesses
+= thisrun_accesses
;
1725 while (num_accesses
< count
)
1728 thisrun_accesses
= ((count
- num_accesses
) >= 14) ? 14 : (count
- num_accesses
);
1729 reg_list
= (0xffff >> (15 - thisrun_accesses
)) & 0xfffe;
1731 for (i
= 1; i
<= thisrun_accesses
; i
++)
1735 arm7_9
->load_hword_reg(target
, i
);
1736 /* fast memory reads are only safe when the target is running
1737 * from a sufficiently high clock (32 kHz is usually too slow)
1739 if (arm7_9
->fast_memory_access
)
1740 arm7_9_execute_fast_sys_speed(target
);
1742 arm7_9_execute_sys_speed(target
);
1745 arm7_9
->read_core_regs_target_buffer(target
, reg_list
, buffer
, 2);
1747 /* advance buffer, count number of accesses */
1748 buffer
+= thisrun_accesses
* 2;
1749 num_accesses
+= thisrun_accesses
;
1753 while (num_accesses
< count
)
1756 thisrun_accesses
= ((count
- num_accesses
) >= 14) ? 14 : (count
- num_accesses
);
1757 reg_list
= (0xffff >> (15 - thisrun_accesses
)) & 0xfffe;
1759 for (i
= 1; i
<= thisrun_accesses
; i
++)
1763 arm7_9
->load_byte_reg(target
, i
);
1764 /* fast memory reads are only safe when the target is running
1765 * from a sufficiently high clock (32 kHz is usually too slow)
1767 if (arm7_9
->fast_memory_access
)
1768 arm7_9_execute_fast_sys_speed(target
);
1770 arm7_9_execute_sys_speed(target
);
1773 arm7_9
->read_core_regs_target_buffer(target
, reg_list
, buffer
, 1);
1775 /* advance buffer, count number of accesses */
1776 buffer
+= thisrun_accesses
* 1;
1777 num_accesses
+= thisrun_accesses
;
1781 ERROR("BUG: we shouldn't get here");
1786 for (i
=0; i
<=last_reg
; i
++)
1787 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).dirty
= 1;
1789 arm7_9
->read_xpsr(target
, &cpsr
, 0);
1790 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1792 ERROR("JTAG error while reading cpsr");
1796 if (((cpsr
& 0x1f) == ARMV4_5_MODE_ABT
) && (armv4_5
->core_mode
!= ARMV4_5_MODE_ABT
))
1798 WARNING("memory read caused data abort (address: 0x%8.8x, size: 0x%x, count: 0x%x)", address
, size
, count
);
1800 arm7_9
->write_xpsr_im8(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8) & ~0x20, 0, 0);
1802 return ERROR_TARGET_DATA_ABORT
;
1808 int arm7_9_write_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
)
1810 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1811 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
1812 reg_t
*dbg_ctrl
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_CTRL
];
1815 int num_accesses
= 0;
1816 int thisrun_accesses
;
1822 DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address
, size
, count
);
1824 if (target
->state
!= TARGET_HALTED
)
1826 WARNING("target not halted");
1827 return ERROR_TARGET_NOT_HALTED
;
1830 /* sanitize arguments */
1831 if (((size
!= 4) && (size
!= 2) && (size
!= 1)) || (count
== 0) || !(buffer
))
1832 return ERROR_INVALID_ARGUMENTS
;
1834 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
1835 return ERROR_TARGET_UNALIGNED_ACCESS
;
1837 /* load the base register with the address of the first word */
1839 arm7_9
->write_core_regs(target
, 0x1, reg
);
1841 /* Clear DBGACK, to make sure memory fetches work as expected */
1842 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_DBGACK
, 1, 0);
1843 embeddedice_store_reg(dbg_ctrl
);
1848 while (num_accesses
< count
)
1851 thisrun_accesses
= ((count
- num_accesses
) >= 14) ? 14 : (count
- num_accesses
);
1852 reg_list
= (0xffff >> (15 - thisrun_accesses
)) & 0xfffe;
1854 for (i
= 1; i
<= thisrun_accesses
; i
++)
1858 reg
[i
] = target_buffer_get_u32(target
, buffer
);
1862 arm7_9
->write_core_regs(target
, reg_list
, reg
);
1864 arm7_9
->store_word_regs(target
, reg_list
);
1866 /* fast memory writes are only safe when the target is running
1867 * from a sufficiently high clock (32 kHz is usually too slow)
1869 if (arm7_9
->fast_memory_access
)
1870 arm7_9_execute_fast_sys_speed(target
);
1872 arm7_9_execute_sys_speed(target
);
1874 num_accesses
+= thisrun_accesses
;
1878 while (num_accesses
< count
)
1881 thisrun_accesses
= ((count
- num_accesses
) >= 14) ? 14 : (count
- num_accesses
);
1882 reg_list
= (0xffff >> (15 - thisrun_accesses
)) & 0xfffe;
1884 for (i
= 1; i
<= thisrun_accesses
; i
++)
1888 reg
[i
] = target_buffer_get_u16(target
, buffer
) & 0xffff;
1892 arm7_9
->write_core_regs(target
, reg_list
, reg
);
1894 for (i
= 1; i
<= thisrun_accesses
; i
++)
1896 arm7_9
->store_hword_reg(target
, i
);
1898 /* fast memory writes are only safe when the target is running
1899 * from a sufficiently high clock (32 kHz is usually too slow)
1901 if (arm7_9
->fast_memory_access
)
1902 arm7_9_execute_fast_sys_speed(target
);
1904 arm7_9_execute_sys_speed(target
);
1907 num_accesses
+= thisrun_accesses
;
1911 while (num_accesses
< count
)
1914 thisrun_accesses
= ((count
- num_accesses
) >= 14) ? 14 : (count
- num_accesses
);
1915 reg_list
= (0xffff >> (15 - thisrun_accesses
)) & 0xfffe;
1917 for (i
= 1; i
<= thisrun_accesses
; i
++)
1921 reg
[i
] = *buffer
++ & 0xff;
1924 arm7_9
->write_core_regs(target
, reg_list
, reg
);
1926 for (i
= 1; i
<= thisrun_accesses
; i
++)
1928 arm7_9
->store_byte_reg(target
, i
);
1929 /* fast memory writes are only safe when the target is running
1930 * from a sufficiently high clock (32 kHz is usually too slow)
1932 if (arm7_9
->fast_memory_access
)
1933 arm7_9_execute_fast_sys_speed(target
);
1935 arm7_9_execute_sys_speed(target
);
1938 num_accesses
+= thisrun_accesses
;
1942 ERROR("BUG: we shouldn't get here");
1948 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_DBGACK
, 1, 1);
1949 embeddedice_store_reg(dbg_ctrl
);
1951 for (i
=0; i
<=last_reg
; i
++)
1952 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).dirty
= 1;
1954 arm7_9
->read_xpsr(target
, &cpsr
, 0);
1955 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1957 ERROR("JTAG error while reading cpsr");
1961 if (((cpsr
& 0x1f) == ARMV4_5_MODE_ABT
) && (armv4_5
->core_mode
!= ARMV4_5_MODE_ABT
))
1963 WARNING("memory write caused data abort (address: 0x%8.8x, size: 0x%x, count: 0x%x)", address
, size
, count
);
1965 arm7_9
->write_xpsr_im8(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8) & ~0x20, 0, 0);
1967 return ERROR_TARGET_DATA_ABORT
;
1973 int arm7_9_bulk_write_memory(target_t
*target
, u32 address
, u32 count
, u8
*buffer
)
1975 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1976 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
1977 enum armv4_5_state core_state
= armv4_5
->core_state
;
1978 u32 r0
= buf_get_u32(armv4_5
->core_cache
->reg_list
[0].value
, 0, 32);
1979 u32 r1
= buf_get_u32(armv4_5
->core_cache
->reg_list
[1].value
, 0, 32);
1980 u32 pc
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
1985 /* MRC TST BNE MRC STR B */
1986 0xee101e10, 0xe3110001, 0x0afffffc, 0xee111e10, 0xe4801004, 0xeafffff9
1989 if (!arm7_9
->dcc_downloads
)
1990 return target
->type
->write_memory(target
, address
, 4, count
, buffer
);
1992 /* regrab previously allocated working_area, or allocate a new one */
1993 if (!arm7_9
->dcc_working_area
)
1995 u8 dcc_code_buf
[6 * 4];
1997 /* make sure we have a working area */
1998 if (target_alloc_working_area(target
, 24, &arm7_9
->dcc_working_area
) != ERROR_OK
)
2000 INFO("no working area available, falling back to memory writes");
2001 return target
->type
->write_memory(target
, address
, 4, count
, buffer
);
2004 /* copy target instructions to target endianness */
2005 for (i
= 0; i
< 6; i
++)
2007 target_buffer_set_u32(target
, dcc_code_buf
+ i
*4, dcc_code
[i
]);
2010 /* write DCC code to working area */
2011 target
->type
->write_memory(target
, arm7_9
->dcc_working_area
->address
, 4, 6, dcc_code_buf
);
2014 buf_set_u32(armv4_5
->core_cache
->reg_list
[0].value
, 0, 32, address
);
2015 armv4_5
->core_cache
->reg_list
[0].valid
= 1;
2016 armv4_5
->core_cache
->reg_list
[0].dirty
= 1;
2017 armv4_5
->core_state
= ARMV4_5_STATE_ARM
;
2019 arm7_9_resume(target
, 0, arm7_9
->dcc_working_area
->address
, 1, 1);
2021 for (i
= 0; i
< count
; i
++)
2023 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_COMMS_DATA
], target_buffer_get_u32(target
, buffer
));
2027 target
->type
->halt(target
);
2029 while (target
->state
!= TARGET_HALTED
)
2030 target
->type
->poll(target
);
2032 /* restore target state */
2033 buf_set_u32(armv4_5
->core_cache
->reg_list
[0].value
, 0, 32, r0
);
2034 armv4_5
->core_cache
->reg_list
[0].valid
= 1;
2035 armv4_5
->core_cache
->reg_list
[0].dirty
= 1;
2036 buf_set_u32(armv4_5
->core_cache
->reg_list
[1].value
, 0, 32, r1
);
2037 armv4_5
->core_cache
->reg_list
[1].valid
= 1;
2038 armv4_5
->core_cache
->reg_list
[1].dirty
= 1;
2039 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, pc
);
2040 armv4_5
->core_cache
->reg_list
[15].valid
= 1;
2041 armv4_5
->core_cache
->reg_list
[15].dirty
= 1;
2042 armv4_5
->core_state
= core_state
;
2047 int arm7_9_register_commands(struct command_context_s
*cmd_ctx
)
2049 command_t
*arm7_9_cmd
;
2051 arm7_9_cmd
= register_command(cmd_ctx
, NULL
, "arm7_9", NULL
, COMMAND_ANY
, "arm7/9 specific commands");
2053 register_command(cmd_ctx
, arm7_9_cmd
, "write_xpsr", handle_arm7_9_write_xpsr_command
, COMMAND_EXEC
, "write program status register <value> <not cpsr|spsr>");
2054 register_command(cmd_ctx
, arm7_9_cmd
, "write_xpsr_im8", handle_arm7_9_write_xpsr_im8_command
, COMMAND_EXEC
, "write program status register <8bit immediate> <rotate> <not cpsr|spsr>");
2056 register_command(cmd_ctx
, arm7_9_cmd
, "write_core_reg", handle_arm7_9_write_core_reg_command
, COMMAND_EXEC
, "write core register <num> <mode> <value>");
2058 register_command(cmd_ctx
, arm7_9_cmd
, "sw_bkpts", handle_arm7_9_sw_bkpts_command
, COMMAND_EXEC
, "support for software breakpoints <enable|disable>");
2059 register_command(cmd_ctx
, arm7_9_cmd
, "force_hw_bkpts", handle_arm7_9_force_hw_bkpts_command
, COMMAND_EXEC
, "use hardware breakpoints for all breakpoints (disables sw breakpoint support) <enable|disable>");
2060 register_command(cmd_ctx
, arm7_9_cmd
, "dbgrq", handle_arm7_9_dbgrq_command
,
2061 COMMAND_ANY
, "use EmbeddedICE dbgrq instead of breakpoint for target halt requests <enable|disable>");
2062 register_command(cmd_ctx
, arm7_9_cmd
, "fast_writes", handle_arm7_9_fast_memory_access_command
,
2063 COMMAND_ANY
, "(deprecated, see: arm7_9 fast_memory_access)");
2064 register_command(cmd_ctx
, arm7_9_cmd
, "fast_memory_access", handle_arm7_9_fast_memory_access_command
,
2065 COMMAND_ANY
, "use fast memory accesses instead of slower but potentially unsafe slow accesses <enable|disable>");
2066 register_command(cmd_ctx
, arm7_9_cmd
, "dcc_downloads", handle_arm7_9_dcc_downloads_command
,
2067 COMMAND_ANY
, "use DCC downloads for larger memory writes <enable|disable>");
2069 armv4_5_register_commands(cmd_ctx
);
2074 int handle_arm7_9_write_xpsr_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
2079 target_t
*target
= get_current_target(cmd_ctx
);
2080 armv4_5_common_t
*armv4_5
;
2081 arm7_9_common_t
*arm7_9
;
2083 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
2085 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
2089 if (target
->state
!= TARGET_HALTED
)
2091 command_print(cmd_ctx
, "can't write registers while running");
2097 command_print(cmd_ctx
, "usage: write_xpsr <value> <not cpsr|spsr>");
2101 value
= strtoul(args
[0], NULL
, 0);
2102 spsr
= strtol(args
[1], NULL
, 0);
2104 /* if we're writing the CPSR, mask the T bit */
2108 arm7_9
->write_xpsr(target
, value
, spsr
);
2109 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
2111 ERROR("JTAG error while writing to xpsr");
2118 int handle_arm7_9_write_xpsr_im8_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
2124 target_t
*target
= get_current_target(cmd_ctx
);
2125 armv4_5_common_t
*armv4_5
;
2126 arm7_9_common_t
*arm7_9
;
2128 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
2130 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
2134 if (target
->state
!= TARGET_HALTED
)
2136 command_print(cmd_ctx
, "can't write registers while running");
2142 command_print(cmd_ctx
, "usage: write_xpsr_im8 <im8> <rotate> <not cpsr|spsr>");
2146 value
= strtoul(args
[0], NULL
, 0);
2147 rotate
= strtol(args
[1], NULL
, 0);
2148 spsr
= strtol(args
[2], NULL
, 0);
2150 arm7_9
->write_xpsr_im8(target
, value
, rotate
, spsr
);
2151 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
2153 ERROR("JTAG error while writing 8-bit immediate to xpsr");
2160 int handle_arm7_9_write_core_reg_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
2165 target_t
*target
= get_current_target(cmd_ctx
);
2166 armv4_5_common_t
*armv4_5
;
2167 arm7_9_common_t
*arm7_9
;
2169 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
2171 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
2175 if (target
->state
!= TARGET_HALTED
)
2177 command_print(cmd_ctx
, "can't write registers while running");
2183 command_print(cmd_ctx
, "usage: write_core_reg <num> <mode> <value>");
2187 num
= strtol(args
[0], NULL
, 0);
2188 mode
= strtoul(args
[1], NULL
, 0);
2189 value
= strtoul(args
[2], NULL
, 0);
2191 arm7_9_write_core_reg(target
, num
, mode
, value
);
2196 int handle_arm7_9_sw_bkpts_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
2198 target_t
*target
= get_current_target(cmd_ctx
);
2199 armv4_5_common_t
*armv4_5
;
2200 arm7_9_common_t
*arm7_9
;
2202 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
2204 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
2210 command_print(cmd_ctx
, "software breakpoints %s", (arm7_9
->sw_bkpts_enabled
) ? "enabled" : "disabled");
2214 if (strcmp("enable", args
[0]) == 0)
2216 if (arm7_9
->sw_bkpts_use_wp
)
2218 arm7_9_enable_sw_bkpts(target
);
2222 arm7_9
->sw_bkpts_enabled
= 1;
2225 else if (strcmp("disable", args
[0]) == 0)
2227 if (arm7_9
->sw_bkpts_use_wp
)
2229 arm7_9_disable_sw_bkpts(target
);
2233 arm7_9
->sw_bkpts_enabled
= 0;
2238 command_print(cmd_ctx
, "usage: arm7_9 sw_bkpts <enable|disable>");
2241 command_print(cmd_ctx
, "software breakpoints %s", (arm7_9
->sw_bkpts_enabled
) ? "enabled" : "disabled");
2246 int handle_arm7_9_force_hw_bkpts_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
2248 target_t
*target
= get_current_target(cmd_ctx
);
2249 armv4_5_common_t
*armv4_5
;
2250 arm7_9_common_t
*arm7_9
;
2252 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
2254 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
2258 if ((argc
>= 1) && (strcmp("enable", args
[0]) == 0))
2260 arm7_9
->force_hw_bkpts
= 1;
2261 if (arm7_9
->sw_bkpts_use_wp
)
2263 arm7_9_disable_sw_bkpts(target
);
2266 else if ((argc
>= 1) && (strcmp("disable", args
[0]) == 0))
2268 arm7_9
->force_hw_bkpts
= 0;
2272 command_print(cmd_ctx
, "usage: arm7_9 force_hw_bkpts <enable|disable>");
2275 command_print(cmd_ctx
, "force hardware breakpoints %s", (arm7_9
->force_hw_bkpts
) ? "enabled" : "disabled");
2280 int handle_arm7_9_dbgrq_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
2282 target_t
*target
= get_current_target(cmd_ctx
);
2283 armv4_5_common_t
*armv4_5
;
2284 arm7_9_common_t
*arm7_9
;
2286 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
2288 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
2294 if (strcmp("enable", args
[0]) == 0)
2296 arm7_9
->use_dbgrq
= 1;
2298 else if (strcmp("disable", args
[0]) == 0)
2300 arm7_9
->use_dbgrq
= 0;
2304 command_print(cmd_ctx
, "usage: arm7_9 dbgrq <enable|disable>");
2308 command_print(cmd_ctx
, "use of EmbeddedICE dbgrq instead of breakpoint for target halt %s", (arm7_9
->use_dbgrq
) ? "enabled" : "disabled");
2313 int handle_arm7_9_fast_memory_access_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
2315 target_t
*target
= get_current_target(cmd_ctx
);
2316 armv4_5_common_t
*armv4_5
;
2317 arm7_9_common_t
*arm7_9
;
2319 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
2321 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
2327 if (strcmp("enable", args
[0]) == 0)
2329 arm7_9
->fast_memory_access
= 1;
2331 else if (strcmp("disable", args
[0]) == 0)
2333 arm7_9
->fast_memory_access
= 0;
2337 command_print(cmd_ctx
, "usage: arm7_9 fast_memory_access <enable|disable>");
2341 command_print(cmd_ctx
, "fast memory access is %s", (arm7_9
->fast_memory_access
) ? "enabled" : "disabled");
2346 int handle_arm7_9_dcc_downloads_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
2348 target_t
*target
= get_current_target(cmd_ctx
);
2349 armv4_5_common_t
*armv4_5
;
2350 arm7_9_common_t
*arm7_9
;
2352 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
2354 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
2360 if (strcmp("enable", args
[0]) == 0)
2362 arm7_9
->dcc_downloads
= 1;
2364 else if (strcmp("disable", args
[0]) == 0)
2366 arm7_9
->dcc_downloads
= 0;
2370 command_print(cmd_ctx
, "usage: arm7_9 dcc_downloads <enable|disable>");
2374 command_print(cmd_ctx
, "dcc downloads are %s", (arm7_9
->dcc_downloads
) ? "enabled" : "disabled");
2379 int arm7_9_init_arch_info(target_t
*target
, arm7_9_common_t
*arm7_9
)
2381 armv4_5_common_t
*armv4_5
= &arm7_9
->armv4_5_common
;
2383 arm7_9
->common_magic
= ARM7_9_COMMON_MAGIC
;
2385 arm_jtag_setup_connection(&arm7_9
->jtag_info
);
2386 arm7_9
->wp_available
= 2;
2387 arm7_9
->wp0_used
= 0;
2388 arm7_9
->wp1_used
= 0;
2389 arm7_9
->force_hw_bkpts
= 0;
2390 arm7_9
->use_dbgrq
= 0;
2391 arm7_9
->has_etm
= 0;
2393 arm7_9
->reinit_embeddedice
= 0;
2395 arm7_9
->dcc_working_area
= NULL
;
2397 arm7_9
->fast_memory_access
= 0;
2398 arm7_9
->dcc_downloads
= 0;
2400 jtag_register_event_callback(arm7_9_jtag_callback
, target
);
2402 armv4_5
->arch_info
= arm7_9
;
2403 armv4_5
->read_core_reg
= arm7_9_read_core_reg
;
2404 armv4_5
->write_core_reg
= arm7_9_write_core_reg
;
2405 armv4_5
->full_context
= arm7_9_full_context
;
2407 armv4_5_init_arch_info(target
, armv4_5
);
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