ed913024dbfb1f1d90a13cd3b213f8d262febb97
[openocd.git] / src / target / arm7_9_common.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2007-2010 √ėyvind Harboe *
6 * oyvind.harboe@zylin.com *
7 * *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
10 * *
11 * Copyright (C) 2008 by Hongtao Zheng *
12 * hontor@126.com *
13 * *
14 * Copyright (C) 2009 by David Brownell *
15 * *
16 * This program is free software; you can redistribute it and/or modify *
17 * it under the terms of the GNU General Public License as published by *
18 * the Free Software Foundation; either version 2 of the License, or *
19 * (at your option) any later version. *
20 * *
21 * This program is distributed in the hope that it will be useful, *
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
24 * GNU General Public License for more details. *
25 * *
26 * You should have received a copy of the GNU General Public License *
27 * along with this program; if not, write to the *
28 * Free Software Foundation, Inc., *
29 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
30 ***************************************************************************/
31 #ifdef HAVE_CONFIG_H
32 #include "config.h"
33 #endif
34
35 #include "breakpoints.h"
36 #include "embeddedice.h"
37 #include "target_request.h"
38 #include "etm.h"
39 #include <helper/time_support.h>
40 #include "arm_simulator.h"
41 #include "arm_semihosting.h"
42 #include "algorithm.h"
43 #include "register.h"
44 #include "armv4_5.h"
45
46
47 /**
48 * @file
49 * Hold common code supporting the ARM7 and ARM9 core generations.
50 *
51 * While the ARM core implementations evolved substantially during these
52 * two generations, they look quite similar from the JTAG perspective.
53 * Both have similar debug facilities, based on the same two scan chains
54 * providing access to the core and to an EmbeddedICE module. Both can
55 * support similar ETM and ETB modules, for tracing. And both expose
56 * what could be viewed as "ARM Classic", with multiple processor modes,
57 * shadowed registers, and support for the Thumb instruction set.
58 *
59 * Processor differences include things like presence or absence of MMU
60 * and cache, pipeline sizes, use of a modified Harvard Architecure
61 * (with separate instruction and data busses from the CPU), support
62 * for cpu clock gating during idle, and more.
63 */
64
65 static int arm7_9_debug_entry(struct target *target);
66
67 /**
68 * Clear watchpoints for an ARM7/9 target.
69 *
70 * @param arm7_9 Pointer to the common struct for an ARM7/9 target
71 * @return JTAG error status after executing queue
72 */
73 static int arm7_9_clear_watchpoints(struct arm7_9_common *arm7_9)
74 {
75 LOG_DEBUG("-");
76 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
77 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
78 arm7_9->sw_breakpoint_count = 0;
79 arm7_9->sw_breakpoints_added = 0;
80 arm7_9->wp0_used = 0;
81 arm7_9->wp1_used = arm7_9->wp1_used_default;
82 arm7_9->wp_available = arm7_9->wp_available_max;
83
84 return jtag_execute_queue();
85 }
86
87 /**
88 * Assign a watchpoint to one of the two available hardware comparators in an
89 * ARM7 or ARM9 target.
90 *
91 * @param arm7_9 Pointer to the common struct for an ARM7/9 target
92 * @param breakpoint Pointer to the breakpoint to be used as a watchpoint
93 */
94 static void arm7_9_assign_wp(struct arm7_9_common *arm7_9, struct breakpoint *breakpoint)
95 {
96 if (!arm7_9->wp0_used)
97 {
98 arm7_9->wp0_used = 1;
99 breakpoint->set = 1;
100 arm7_9->wp_available--;
101 }
102 else if (!arm7_9->wp1_used)
103 {
104 arm7_9->wp1_used = 1;
105 breakpoint->set = 2;
106 arm7_9->wp_available--;
107 }
108 else
109 {
110 LOG_ERROR("BUG: no hardware comparator available");
111 }
112 LOG_DEBUG("BPID: %d (0x%08" PRIx32 ") using hw wp: %d",
113 breakpoint->unique_id,
114 breakpoint->address,
115 breakpoint->set );
116 }
117
118 /**
119 * Setup an ARM7/9 target's embedded ICE registers for software breakpoints.
120 *
121 * @param arm7_9 Pointer to common struct for ARM7/9 targets
122 * @return Error codes if there is a problem finding a watchpoint or the result
123 * of executing the JTAG queue
124 */
125 static int arm7_9_set_software_breakpoints(struct arm7_9_common *arm7_9)
126 {
127 if (arm7_9->sw_breakpoints_added)
128 {
129 return ERROR_OK;
130 }
131 if (arm7_9->wp_available < 1)
132 {
133 LOG_WARNING("can't enable sw breakpoints with no watchpoint unit available");
134 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
135 }
136 arm7_9->wp_available--;
137
138 /* pick a breakpoint unit */
139 if (!arm7_9->wp0_used)
140 {
141 arm7_9->sw_breakpoints_added = 1;
142 arm7_9->wp0_used = 3;
143 } else if (!arm7_9->wp1_used)
144 {
145 arm7_9->sw_breakpoints_added = 2;
146 arm7_9->wp1_used = 3;
147 }
148 else
149 {
150 LOG_ERROR("BUG: both watchpoints used, but wp_available >= 1");
151 return ERROR_FAIL;
152 }
153
154 if (arm7_9->sw_breakpoints_added == 1)
155 {
156 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], arm7_9->arm_bkpt);
157 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0x0);
158 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffffu);
159 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
160 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
161 }
162 else if (arm7_9->sw_breakpoints_added == 2)
163 {
164 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], arm7_9->arm_bkpt);
165 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0x0);
166 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0xffffffffu);
167 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
168 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
169 }
170 else
171 {
172 LOG_ERROR("BUG: both watchpoints used, but wp_available >= 1");
173 return ERROR_FAIL;
174 }
175 LOG_DEBUG("SW BP using hw wp: %d",
176 arm7_9->sw_breakpoints_added );
177
178 return jtag_execute_queue();
179 }
180
181 /**
182 * Setup the common pieces for an ARM7/9 target after reset or on startup.
183 *
184 * @param target Pointer to an ARM7/9 target to setup
185 * @return Result of clearing the watchpoints on the target
186 */
187 static int arm7_9_setup(struct target *target)
188 {
189 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
190
191 return arm7_9_clear_watchpoints(arm7_9);
192 }
193
194 /**
195 * Set either a hardware or software breakpoint on an ARM7/9 target. The
196 * breakpoint is set up even if it is already set. Some actions, e.g. reset,
197 * might have erased the values in Embedded ICE.
198 *
199 * @param target Pointer to the target device to set the breakpoints on
200 * @param breakpoint Pointer to the breakpoint to be set
201 * @return For hardware breakpoints, this is the result of executing the JTAG
202 * queue. For software breakpoints, this will be the status of the
203 * required memory reads and writes
204 */
205 static int arm7_9_set_breakpoint(struct target *target, struct breakpoint *breakpoint)
206 {
207 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
208 int retval = ERROR_OK;
209
210 LOG_DEBUG("BPID: %d, Address: 0x%08" PRIx32 ", Type: %d" ,
211 breakpoint->unique_id,
212 breakpoint->address,
213 breakpoint->type);
214
215 if (target->state != TARGET_HALTED)
216 {
217 LOG_WARNING("target not halted");
218 return ERROR_TARGET_NOT_HALTED;
219 }
220
221 if (breakpoint->type == BKPT_HARD)
222 {
223 /* either an ARM (4 byte) or Thumb (2 byte) breakpoint */
224 uint32_t mask = (breakpoint->length == 4) ? 0x3u : 0x1u;
225
226 /* reassign a hw breakpoint */
227 if (breakpoint->set == 0)
228 {
229 arm7_9_assign_wp(arm7_9, breakpoint);
230 }
231
232 if (breakpoint->set == 1)
233 {
234 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], breakpoint->address);
235 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask);
236 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffffu);
237 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
238 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
239 }
240 else if (breakpoint->set == 2)
241 {
242 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], breakpoint->address);
243 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask);
244 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffffu);
245 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
246 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
247 }
248 else
249 {
250 LOG_ERROR("BUG: no hardware comparator available");
251 return ERROR_OK;
252 }
253
254 retval = jtag_execute_queue();
255 }
256 else if (breakpoint->type == BKPT_SOFT)
257 {
258 /* did we already set this breakpoint? */
259 if (breakpoint->set)
260 return ERROR_OK;
261
262 if (breakpoint->length == 4)
263 {
264 uint32_t verify = 0xffffffff;
265 /* keep the original instruction in target endianness */
266 if ((retval = target_read_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
267 {
268 return retval;
269 }
270 /* write the breakpoint instruction in target endianness (arm7_9->arm_bkpt is host endian) */
271 if ((retval = target_write_u32(target, breakpoint->address, arm7_9->arm_bkpt)) != ERROR_OK)
272 {
273 return retval;
274 }
275
276 if ((retval = target_read_u32(target, breakpoint->address, &verify)) != ERROR_OK)
277 {
278 return retval;
279 }
280 if (verify != arm7_9->arm_bkpt)
281 {
282 LOG_ERROR("Unable to set 32 bit software breakpoint at address %08" PRIx32 " - check that memory is read/writable", breakpoint->address);
283 return ERROR_OK;
284 }
285 }
286 else
287 {
288 uint16_t verify = 0xffff;
289 /* keep the original instruction in target endianness */
290 if ((retval = target_read_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
291 {
292 return retval;
293 }
294 /* write the breakpoint instruction in target endianness (arm7_9->thumb_bkpt is host endian) */
295 if ((retval = target_write_u16(target, breakpoint->address, arm7_9->thumb_bkpt)) != ERROR_OK)
296 {
297 return retval;
298 }
299
300 if ((retval = target_read_u16(target, breakpoint->address, &verify)) != ERROR_OK)
301 {
302 return retval;
303 }
304 if (verify != arm7_9->thumb_bkpt)
305 {
306 LOG_ERROR("Unable to set thumb software breakpoint at address %08" PRIx32 " - check that memory is read/writable", breakpoint->address);
307 return ERROR_OK;
308 }
309 }
310
311 if ((retval = arm7_9_set_software_breakpoints(arm7_9)) != ERROR_OK)
312 return retval;
313
314 arm7_9->sw_breakpoint_count++;
315
316 breakpoint->set = 1;
317 }
318
319 return retval;
320 }
321
322 /**
323 * Unsets an existing breakpoint on an ARM7/9 target. If it is a hardware
324 * breakpoint, the watchpoint used will be freed and the Embedded ICE registers
325 * will be updated. Otherwise, the software breakpoint will be restored to its
326 * original instruction if it hasn't already been modified.
327 *
328 * @param target Pointer to ARM7/9 target to unset the breakpoint from
329 * @param breakpoint Pointer to breakpoint to be unset
330 * @return For hardware breakpoints, this is the result of executing the JTAG
331 * queue. For software breakpoints, this will be the status of the
332 * required memory reads and writes
333 */
334 static int arm7_9_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
335 {
336 int retval = ERROR_OK;
337 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
338
339 LOG_DEBUG("BPID: %d, Address: 0x%08" PRIx32,
340 breakpoint->unique_id,
341 breakpoint->address );
342
343 if (!breakpoint->set)
344 {
345 LOG_WARNING("breakpoint not set");
346 return ERROR_OK;
347 }
348
349 if (breakpoint->type == BKPT_HARD)
350 {
351 LOG_DEBUG("BPID: %d Releasing hw wp: %d",
352 breakpoint->unique_id,
353 breakpoint->set );
354 if (breakpoint->set == 1)
355 {
356 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
357 arm7_9->wp0_used = 0;
358 arm7_9->wp_available++;
359 }
360 else if (breakpoint->set == 2)
361 {
362 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
363 arm7_9->wp1_used = 0;
364 arm7_9->wp_available++;
365 }
366 retval = jtag_execute_queue();
367 breakpoint->set = 0;
368 }
369 else
370 {
371 /* restore original instruction (kept in target endianness) */
372 if (breakpoint->length == 4)
373 {
374 uint32_t current_instr;
375 /* check that user program as not modified breakpoint instruction */
376 if ((retval = target_read_memory(target, breakpoint->address, 4, 1, (uint8_t*)&current_instr)) != ERROR_OK)
377 {
378 return retval;
379 }
380 current_instr = target_buffer_get_u32(target, (uint8_t *)&current_instr);
381 if (current_instr == arm7_9->arm_bkpt)
382 if ((retval = target_write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
383 {
384 return retval;
385 }
386 }
387 else
388 {
389 uint16_t current_instr;
390 /* check that user program as not modified breakpoint instruction */
391 if ((retval = target_read_memory(target, breakpoint->address, 2, 1, (uint8_t*)&current_instr)) != ERROR_OK)
392 {
393 return retval;
394 }
395 current_instr = target_buffer_get_u16(target, (uint8_t *)&current_instr);
396 if (current_instr == arm7_9->thumb_bkpt)
397 if ((retval = target_write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
398 {
399 return retval;
400 }
401 }
402
403 if (--arm7_9->sw_breakpoint_count==0)
404 {
405 /* We have removed the last sw breakpoint, clear the hw breakpoint we used to implement it */
406 if (arm7_9->sw_breakpoints_added == 1)
407 {
408 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0);
409 }
410 else if (arm7_9->sw_breakpoints_added == 2)
411 {
412 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0);
413 }
414 }
415
416 breakpoint->set = 0;
417 }
418
419 return retval;
420 }
421
422 /**
423 * Add a breakpoint to an ARM7/9 target. This makes sure that there are no
424 * dangling breakpoints and that the desired breakpoint can be added.
425 *
426 * @param target Pointer to the target ARM7/9 device to add a breakpoint to
427 * @param breakpoint Pointer to the breakpoint to be added
428 * @return An error status if there is a problem adding the breakpoint or the
429 * result of setting the breakpoint
430 */
431 int arm7_9_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
432 {
433 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
434
435 if (arm7_9->breakpoint_count == 0)
436 {
437 /* make sure we don't have any dangling breakpoints. This is vital upon
438 * GDB connect/disconnect
439 */
440 arm7_9_clear_watchpoints(arm7_9);
441 }
442
443 if ((breakpoint->type == BKPT_HARD) && (arm7_9->wp_available < 1))
444 {
445 LOG_INFO("no watchpoint unit available for hardware breakpoint");
446 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
447 }
448
449 if ((breakpoint->length != 2) && (breakpoint->length != 4))
450 {
451 LOG_INFO("only breakpoints of two (Thumb) or four (ARM) bytes length supported");
452 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
453 }
454
455 if (breakpoint->type == BKPT_HARD)
456 {
457 arm7_9_assign_wp(arm7_9, breakpoint);
458 }
459
460 arm7_9->breakpoint_count++;
461
462 return arm7_9_set_breakpoint(target, breakpoint);
463 }
464
465 /**
466 * Removes a breakpoint from an ARM7/9 target. This will make sure there are no
467 * dangling breakpoints and updates available watchpoints if it is a hardware
468 * breakpoint.
469 *
470 * @param target Pointer to the target to have a breakpoint removed
471 * @param breakpoint Pointer to the breakpoint to be removed
472 * @return Error status if there was a problem unsetting the breakpoint or the
473 * watchpoints could not be cleared
474 */
475 int arm7_9_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
476 {
477 int retval = ERROR_OK;
478 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
479
480 if ((retval = arm7_9_unset_breakpoint(target, breakpoint)) != ERROR_OK)
481 {
482 return retval;
483 }
484
485 if (breakpoint->type == BKPT_HARD)
486 arm7_9->wp_available++;
487
488 arm7_9->breakpoint_count--;
489 if (arm7_9->breakpoint_count == 0)
490 {
491 /* make sure we don't have any dangling breakpoints */
492 if ((retval = arm7_9_clear_watchpoints(arm7_9)) != ERROR_OK)
493 {
494 return retval;
495 }
496 }
497
498 return ERROR_OK;
499 }
500
501 /**
502 * Sets a watchpoint for an ARM7/9 target in one of the watchpoint units. It is
503 * considered a bug to call this function when there are no available watchpoint
504 * units.
505 *
506 * @param target Pointer to an ARM7/9 target to set a watchpoint on
507 * @param watchpoint Pointer to the watchpoint to be set
508 * @return Error status if watchpoint set fails or the result of executing the
509 * JTAG queue
510 */
511 static int arm7_9_set_watchpoint(struct target *target, struct watchpoint *watchpoint)
512 {
513 int retval = ERROR_OK;
514 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
515 int rw_mask = 1;
516 uint32_t mask;
517
518 mask = watchpoint->length - 1;
519
520 if (target->state != TARGET_HALTED)
521 {
522 LOG_WARNING("target not halted");
523 return ERROR_TARGET_NOT_HALTED;
524 }
525
526 if (watchpoint->rw == WPT_ACCESS)
527 rw_mask = 0;
528 else
529 rw_mask = 1;
530
531 if (!arm7_9->wp0_used)
532 {
533 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], watchpoint->address);
534 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask);
535 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], watchpoint->mask);
536 if (watchpoint->mask != 0xffffffffu)
537 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], watchpoint->value);
538 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
539 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
540
541 if ((retval = jtag_execute_queue()) != ERROR_OK)
542 {
543 return retval;
544 }
545 watchpoint->set = 1;
546 arm7_9->wp0_used = 2;
547 }
548 else if (!arm7_9->wp1_used)
549 {
550 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], watchpoint->address);
551 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask);
552 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], watchpoint->mask);
553 if (watchpoint->mask != 0xffffffffu)
554 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], watchpoint->value);
555 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
556 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
557
558 if ((retval = jtag_execute_queue()) != ERROR_OK)
559 {
560 return retval;
561 }
562 watchpoint->set = 2;
563 arm7_9->wp1_used = 2;
564 }
565 else
566 {
567 LOG_ERROR("BUG: no hardware comparator available");
568 return ERROR_OK;
569 }
570
571 return ERROR_OK;
572 }
573
574 /**
575 * Unset an existing watchpoint and clear the used watchpoint unit.
576 *
577 * @param target Pointer to the target to have the watchpoint removed
578 * @param watchpoint Pointer to the watchpoint to be removed
579 * @return Error status while trying to unset the watchpoint or the result of
580 * executing the JTAG queue
581 */
582 static int arm7_9_unset_watchpoint(struct target *target, struct watchpoint *watchpoint)
583 {
584 int retval = ERROR_OK;
585 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
586
587 if (target->state != TARGET_HALTED)
588 {
589 LOG_WARNING("target not halted");
590 return ERROR_TARGET_NOT_HALTED;
591 }
592
593 if (!watchpoint->set)
594 {
595 LOG_WARNING("breakpoint not set");
596 return ERROR_OK;
597 }
598
599 if (watchpoint->set == 1)
600 {
601 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
602 if ((retval = jtag_execute_queue()) != ERROR_OK)
603 {
604 return retval;
605 }
606 arm7_9->wp0_used = 0;
607 }
608 else if (watchpoint->set == 2)
609 {
610 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
611 if ((retval = jtag_execute_queue()) != ERROR_OK)
612 {
613 return retval;
614 }
615 arm7_9->wp1_used = 0;
616 }
617 watchpoint->set = 0;
618
619 return ERROR_OK;
620 }
621
622 /**
623 * Add a watchpoint to an ARM7/9 target. If there are no watchpoint units
624 * available, an error response is returned.
625 *
626 * @param target Pointer to the ARM7/9 target to add a watchpoint to
627 * @param watchpoint Pointer to the watchpoint to be added
628 * @return Error status while trying to add the watchpoint
629 */
630 int arm7_9_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
631 {
632 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
633
634 if (arm7_9->wp_available < 1)
635 {
636 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
637 }
638
639 if ((watchpoint->length != 1) && (watchpoint->length != 2) && (watchpoint->length != 4))
640 {
641 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
642 }
643
644 arm7_9->wp_available--;
645
646 return ERROR_OK;
647 }
648
649 /**
650 * Remove a watchpoint from an ARM7/9 target. The watchpoint will be unset and
651 * the used watchpoint unit will be reopened.
652 *
653 * @param target Pointer to the target to remove a watchpoint from
654 * @param watchpoint Pointer to the watchpoint to be removed
655 * @return Result of trying to unset the watchpoint
656 */
657 int arm7_9_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
658 {
659 int retval = ERROR_OK;
660 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
661
662 if (watchpoint->set)
663 {
664 if ((retval = arm7_9_unset_watchpoint(target, watchpoint)) != ERROR_OK)
665 {
666 return retval;
667 }
668 }
669
670 arm7_9->wp_available++;
671
672 return ERROR_OK;
673 }
674
675 /**
676 * Restarts the target by sending a RESTART instruction and moving the JTAG
677 * state to IDLE. This includes a timeout waiting for DBGACK and SYSCOMP to be
678 * asserted by the processor.
679 *
680 * @param target Pointer to target to issue commands to
681 * @return Error status if there is a timeout or a problem while executing the
682 * JTAG queue
683 */
684 int arm7_9_execute_sys_speed(struct target *target)
685 {
686 int retval;
687 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
688 struct arm_jtag *jtag_info = &arm7_9->jtag_info;
689 struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
690
691 /* set RESTART instruction */
692 if (arm7_9->need_bypass_before_restart) {
693 arm7_9->need_bypass_before_restart = 0;
694 retval = arm_jtag_set_instr(jtag_info, 0xf, NULL, TAP_IDLE);
695 if (retval != ERROR_OK)
696 return retval;
697 }
698 retval = arm_jtag_set_instr(jtag_info, 0x4, NULL, TAP_IDLE);
699 if (retval != ERROR_OK)
700 return retval;
701
702 long long then = timeval_ms();
703 int timeout;
704 while (!(timeout = ((timeval_ms()-then) > 1000)))
705 {
706 /* read debug status register */
707 embeddedice_read_reg(dbg_stat);
708 if ((retval = jtag_execute_queue()) != ERROR_OK)
709 return retval;
710 if ((buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))
711 && (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_SYSCOMP, 1)))
712 break;
713 if (debug_level >= 3)
714 {
715 alive_sleep(100);
716 } else
717 {
718 keep_alive();
719 }
720 }
721 if (timeout)
722 {
723 LOG_ERROR("timeout waiting for SYSCOMP & DBGACK, last DBG_STATUS: %" PRIx32 "", buf_get_u32(dbg_stat->value, 0, dbg_stat->size));
724 return ERROR_TARGET_TIMEOUT;
725 }
726
727 return ERROR_OK;
728 }
729
730 /**
731 * Restarts the target by sending a RESTART instruction and moving the JTAG
732 * state to IDLE. This validates that DBGACK and SYSCOMP are set without
733 * waiting until they are.
734 *
735 * @param target Pointer to the target to issue commands to
736 * @return Always ERROR_OK
737 */
738 static int arm7_9_execute_fast_sys_speed(struct target *target)
739 {
740 static int set = 0;
741 static uint8_t check_value[4], check_mask[4];
742
743 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
744 struct arm_jtag *jtag_info = &arm7_9->jtag_info;
745 struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
746 int retval;
747
748 /* set RESTART instruction */
749 if (arm7_9->need_bypass_before_restart) {
750 arm7_9->need_bypass_before_restart = 0;
751 retval = arm_jtag_set_instr(jtag_info, 0xf, NULL, TAP_IDLE);
752 if (retval != ERROR_OK)
753 return retval;
754 }
755 retval = arm_jtag_set_instr(jtag_info, 0x4, NULL, TAP_IDLE);
756 if (retval != ERROR_OK)
757 return retval;
758
759 if (!set)
760 {
761 /* check for DBGACK and SYSCOMP set (others don't care) */
762
763 /* NB! These are constants that must be available until after next jtag_execute() and
764 * we evaluate the values upon first execution in lieu of setting up these constants
765 * during early setup.
766 * */
767 buf_set_u32(check_value, 0, 32, 0x9);
768 buf_set_u32(check_mask, 0, 32, 0x9);
769 set = 1;
770 }
771
772 /* read debug status register */
773 embeddedice_read_reg_w_check(dbg_stat, check_value, check_mask);
774
775 return ERROR_OK;
776 }
777
778 /**
779 * Get some data from the ARM7/9 target.
780 *
781 * @param target Pointer to the ARM7/9 target to read data from
782 * @param size The number of 32bit words to be read
783 * @param buffer Pointer to the buffer that will hold the data
784 * @return The result of receiving data from the Embedded ICE unit
785 */
786 int arm7_9_target_request_data(struct target *target, uint32_t size, uint8_t *buffer)
787 {
788 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
789 struct arm_jtag *jtag_info = &arm7_9->jtag_info;
790 uint32_t *data;
791 int retval = ERROR_OK;
792 uint32_t i;
793
794 data = malloc(size * (sizeof(uint32_t)));
795
796 retval = embeddedice_receive(jtag_info, data, size);
797
798 /* return the 32-bit ints in the 8-bit array */
799 for (i = 0; i < size; i++)
800 {
801 h_u32_to_le(buffer + (i * 4), data[i]);
802 }
803
804 free(data);
805
806 return retval;
807 }
808
809 /**
810 * Handles requests to an ARM7/9 target. If debug messaging is enabled, the
811 * target is running and the DCC control register has the W bit high, this will
812 * execute the request on the target.
813 *
814 * @param priv Void pointer expected to be a struct target pointer
815 * @return ERROR_OK unless there are issues with the JTAG queue or when reading
816 * from the Embedded ICE unit
817 */
818 static int arm7_9_handle_target_request(void *priv)
819 {
820 int retval = ERROR_OK;
821 struct target *target = priv;
822 if (!target_was_examined(target))
823 return ERROR_OK;
824 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
825 struct arm_jtag *jtag_info = &arm7_9->jtag_info;
826 struct reg *dcc_control = &arm7_9->eice_cache->reg_list[EICE_COMMS_CTRL];
827
828 if (!target->dbg_msg_enabled)
829 return ERROR_OK;
830
831 if (target->state == TARGET_RUNNING)
832 {
833 /* read DCC control register */
834 embeddedice_read_reg(dcc_control);
835 if ((retval = jtag_execute_queue()) != ERROR_OK)
836 {
837 return retval;
838 }
839
840 /* check W bit */
841 if (buf_get_u32(dcc_control->value, 1, 1) == 1)
842 {
843 uint32_t request;
844
845 if ((retval = embeddedice_receive(jtag_info, &request, 1)) != ERROR_OK)
846 {
847 return retval;
848 }
849 if ((retval = target_request(target, request)) != ERROR_OK)
850 {
851 return retval;
852 }
853 }
854 }
855
856 return ERROR_OK;
857 }
858
859 /**
860 * Polls an ARM7/9 target for its current status. If DBGACK is set, the target
861 * is manipulated to the right halted state based on its current state. This is
862 * what happens:
863 *
864 * <table>
865 * <tr><th > State</th><th > Action</th></tr>
866 * <tr><td > TARGET_RUNNING | TARGET_RESET</td><td > Enters debug mode. If TARGET_RESET, pc may be checked</td></tr>
867 * <tr><td > TARGET_UNKNOWN</td><td > Warning is logged</td></tr>
868 * <tr><td > TARGET_DEBUG_RUNNING</td><td > Enters debug mode</td></tr>
869 * <tr><td > TARGET_HALTED</td><td > Nothing</td></tr>
870 * </table>
871 *
872 * If the target does not end up in the halted state, a warning is produced. If
873 * DBGACK is cleared, then the target is expected to either be running or
874 * running in debug.
875 *
876 * @param target Pointer to the ARM7/9 target to poll
877 * @return ERROR_OK or an error status if a command fails
878 */
879 int arm7_9_poll(struct target *target)
880 {
881 int retval;
882 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
883 struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
884
885 /* read debug status register */
886 embeddedice_read_reg(dbg_stat);
887 if ((retval = jtag_execute_queue()) != ERROR_OK)
888 {
889 return retval;
890 }
891
892 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))
893 {
894 /* LOG_DEBUG("DBGACK set, dbg_state->value: 0x%x", buf_get_u32(dbg_stat->value, 0, 32));*/
895 if (target->state == TARGET_UNKNOWN)
896 {
897 /* Starting OpenOCD with target in debug-halt */
898 target->state = TARGET_RUNNING;
899 LOG_DEBUG("DBGACK already set during server startup.");
900 }
901 if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET))
902 {
903 target->state = TARGET_HALTED;
904
905 if ((retval = arm7_9_debug_entry(target)) != ERROR_OK)
906 return retval;
907
908 if (arm_semihosting(target, &retval) != 0)
909 return retval;
910
911 if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
912 {
913 return retval;
914 }
915 }
916 if (target->state == TARGET_DEBUG_RUNNING)
917 {
918 target->state = TARGET_HALTED;
919 if ((retval = arm7_9_debug_entry(target)) != ERROR_OK)
920 return retval;
921
922 if ((retval = target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED)) != ERROR_OK)
923 {
924 return retval;
925 }
926 }
927 if (target->state != TARGET_HALTED)
928 {
929 LOG_WARNING("DBGACK set, but the target did not end up in the halted state %d", target->state);
930 }
931 }
932 else
933 {
934 if (target->state != TARGET_DEBUG_RUNNING)
935 target->state = TARGET_RUNNING;
936 }
937
938 return ERROR_OK;
939 }
940
941 /**
942 * Asserts the reset (SRST) on an ARM7/9 target. Some -S targets (ARM966E-S in
943 * the STR912 isn't affected, ARM926EJ-S in the LPC3180 and AT91SAM9260 is
944 * affected) completely stop the JTAG clock while the core is held in reset
945 * (SRST). It isn't possible to program the halt condition once reset is
946 * asserted, hence a hook that allows the target to set up its reset-halt
947 * condition is setup prior to asserting reset.
948 *
949 * @param target Pointer to an ARM7/9 target to assert reset on
950 * @return ERROR_FAIL if the JTAG device does not have SRST, otherwise ERROR_OK
951 */
952 int arm7_9_assert_reset(struct target *target)
953 {
954 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
955 enum reset_types jtag_reset_config = jtag_get_reset_config();
956 bool use_event = false;
957
958 LOG_DEBUG("target->state: %s",
959 target_state_name(target));
960
961 if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT))
962 use_event = true;
963 else if (!(jtag_reset_config & RESET_HAS_SRST)) {
964 LOG_ERROR("%s: how to reset?", target_name(target));
965 return ERROR_FAIL;
966 }
967
968 /* At this point trst has been asserted/deasserted once. We would
969 * like to program EmbeddedICE while SRST is asserted, instead of
970 * depending on SRST to leave that module alone. However, many CPUs
971 * gate the JTAG clock while SRST is asserted; or JTAG may need
972 * clock stability guarantees (adaptive clocking might help).
973 *
974 * So we assume JTAG access during SRST is off the menu unless it's
975 * been specifically enabled.
976 */
977 bool srst_asserted = false;
978
979 if (!use_event
980 && !(jtag_reset_config & RESET_SRST_PULLS_TRST)
981 && (jtag_reset_config & RESET_SRST_NO_GATING))
982 {
983 jtag_add_reset(0, 1);
984 srst_asserted = true;
985 }
986
987 if (target->reset_halt)
988 {
989 /*
990 * For targets that don't support communication while SRST is
991 * asserted, we need to set up the reset vector catch first.
992 *
993 * When we use TRST+SRST and that's equivalent to a power-up
994 * reset, these settings may well be reset anyway; so setting
995 * them here won't matter.
996 */
997 if (arm7_9->has_vector_catch)
998 {
999 /* program vector catch register to catch reset */
1000 embeddedice_write_reg(&arm7_9->eice_cache
1001 ->reg_list[EICE_VEC_CATCH], 0x1);
1002
1003 /* extra runtest added as issues were found with
1004 * certain ARM9 cores (maybe more) - AT91SAM9260
1005 * and STR9
1006 */
1007 jtag_add_runtest(1, TAP_IDLE);
1008 }
1009 else
1010 {
1011 /* program watchpoint unit to match on reset vector
1012 * address
1013 */
1014 embeddedice_write_reg(&arm7_9->eice_cache
1015 ->reg_list[EICE_W0_ADDR_VALUE], 0x0);
1016 embeddedice_write_reg(&arm7_9->eice_cache
1017 ->reg_list[EICE_W0_ADDR_MASK], 0x3);
1018 embeddedice_write_reg(&arm7_9->eice_cache
1019 ->reg_list[EICE_W0_DATA_MASK],
1020 0xffffffff);
1021 embeddedice_write_reg(&arm7_9->eice_cache
1022 ->reg_list[EICE_W0_CONTROL_VALUE],
1023 EICE_W_CTRL_ENABLE);
1024 embeddedice_write_reg(&arm7_9->eice_cache
1025 ->reg_list[EICE_W0_CONTROL_MASK],
1026 ~EICE_W_CTRL_nOPC & 0xff);
1027 }
1028 }
1029
1030 if (use_event) {
1031 target_handle_event(target, TARGET_EVENT_RESET_ASSERT);
1032 } else {
1033 /* If we use SRST ... we'd like to issue just SRST, but the
1034 * board or chip may be set up so we have to assert TRST as
1035 * well. On some chips that combination is equivalent to a
1036 * power-up reset, and generally clobbers EICE state.
1037 */
1038 if (jtag_reset_config & RESET_SRST_PULLS_TRST)
1039 jtag_add_reset(1, 1);
1040 else if (!srst_asserted)
1041 jtag_add_reset(0, 1);
1042 jtag_add_sleep(50000);
1043 }
1044
1045 target->state = TARGET_RESET;
1046 register_cache_invalidate(arm7_9->armv4_5_common.core_cache);
1047
1048 /* REVISIT why isn't standard debug entry logic sufficient?? */
1049 if (target->reset_halt
1050 && (!(jtag_reset_config & RESET_SRST_PULLS_TRST)
1051 || use_event))
1052 {
1053 /* debug entry was prepared above */
1054 target->debug_reason = DBG_REASON_DBGRQ;
1055 }
1056
1057 return ERROR_OK;
1058 }
1059
1060 /**
1061 * Deassert the reset (SRST) signal on an ARM7/9 target. If SRST pulls TRST
1062 * and the target is being reset into a halt, a warning will be triggered
1063 * because it is not possible to reset into a halted mode in this case. The
1064 * target is halted using the target's functions.
1065 *
1066 * @param target Pointer to the target to have the reset deasserted
1067 * @return ERROR_OK or an error from polling or halting the target
1068 */
1069 int arm7_9_deassert_reset(struct target *target)
1070 {
1071 int retval = ERROR_OK;
1072 LOG_DEBUG("target->state: %s",
1073 target_state_name(target));
1074
1075 /* deassert reset lines */
1076 jtag_add_reset(0, 0);
1077
1078 /* In case polling is disabled, we need to examine the
1079 * target and poll here for this target to work correctly.
1080 *
1081 * Otherwise, e.g. halt will fail afterwards with bogus
1082 * error messages as halt will believe that reset is
1083 * still in effect.
1084 */
1085 if ((retval = target_examine_one(target)) != ERROR_OK)
1086 return retval;
1087
1088 if ((retval = target_poll(target)) != ERROR_OK)
1089 {
1090 return retval;
1091 }
1092
1093 enum reset_types jtag_reset_config = jtag_get_reset_config();
1094 if (target->reset_halt && (jtag_reset_config & RESET_SRST_PULLS_TRST) != 0)
1095 {
1096 LOG_WARNING("srst pulls trst - can not reset into halted mode. Issuing halt after reset.");
1097 if ((retval = target_halt(target)) != ERROR_OK)
1098 {
1099 return retval;
1100 }
1101 }
1102 return retval;
1103 }
1104
1105 /**
1106 * Clears the halt condition for an ARM7/9 target. If it isn't coming out of
1107 * reset and if DBGRQ is used, it is progammed to be deasserted. If the reset
1108 * vector catch was used, it is restored. Otherwise, the control value is
1109 * restored and the watchpoint unit is restored if it was in use.
1110 *
1111 * @param target Pointer to the ARM7/9 target to have halt cleared
1112 * @return Always ERROR_OK
1113 */
1114 static int arm7_9_clear_halt(struct target *target)
1115 {
1116 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
1117 struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1118
1119 /* we used DBGRQ only if we didn't come out of reset */
1120 if (!arm7_9->debug_entry_from_reset && arm7_9->use_dbgrq)
1121 {
1122 /* program EmbeddedICE Debug Control Register to deassert DBGRQ
1123 */
1124 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
1125 embeddedice_store_reg(dbg_ctrl);
1126 }
1127 else
1128 {
1129 if (arm7_9->debug_entry_from_reset && arm7_9->has_vector_catch)
1130 {
1131 /* if we came out of reset, and vector catch is supported, we used
1132 * vector catch to enter debug state
1133 * restore the register in that case
1134 */
1135 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH]);
1136 }
1137 else
1138 {
1139 /* restore registers if watchpoint unit 0 was in use
1140 */
1141 if (arm7_9->wp0_used)
1142 {
1143 if (arm7_9->debug_entry_from_reset)
1144 {
1145 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE]);
1146 }
1147 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
1148 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);
1149 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK]);
1150 }
1151 /* control value always has to be restored, as it was either disabled,
1152 * or enabled with possibly different bits
1153 */
1154 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]);
1155 }
1156 }
1157
1158 return ERROR_OK;
1159 }
1160
1161 /**
1162 * Issue a software reset and halt to an ARM7/9 target. The target is halted
1163 * and then there is a wait until the processor shows the halt. This wait can
1164 * timeout and results in an error being returned. The software reset involves
1165 * clearing the halt, updating the debug control register, changing to ARM mode,
1166 * reset of the program counter, and reset of all of the registers.
1167 *
1168 * @param target Pointer to the ARM7/9 target to be reset and halted by software
1169 * @return Error status if any of the commands fail, otherwise ERROR_OK
1170 */
1171 int arm7_9_soft_reset_halt(struct target *target)
1172 {
1173 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
1174 struct arm *armv4_5 = &arm7_9->armv4_5_common;
1175 struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
1176 struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1177 int i;
1178 int retval;
1179
1180 /* FIX!!! replace some of this code with tcl commands
1181 *
1182 * halt # the halt command is synchronous
1183 * armv4_5 core_state arm
1184 *
1185 */
1186
1187 if ((retval = target_halt(target)) != ERROR_OK)
1188 return retval;
1189
1190 long long then = timeval_ms();
1191 int timeout;
1192 while (!(timeout = ((timeval_ms()-then) > 1000)))
1193 {
1194 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) != 0)
1195 break;
1196 embeddedice_read_reg(dbg_stat);
1197 if ((retval = jtag_execute_queue()) != ERROR_OK)
1198 return retval;
1199 if (debug_level >= 3)
1200 {
1201 alive_sleep(100);
1202 } else
1203 {
1204 keep_alive();
1205 }
1206 }
1207 if (timeout)
1208 {
1209 LOG_ERROR("Failed to halt CPU after 1 sec");
1210 return ERROR_TARGET_TIMEOUT;
1211 }
1212 target->state = TARGET_HALTED;
1213
1214 /* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS
1215 * ensure that DBGRQ is cleared
1216 */
1217 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
1218 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
1219 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 1);
1220 embeddedice_store_reg(dbg_ctrl);
1221
1222 if ((retval = arm7_9_clear_halt(target)) != ERROR_OK)
1223 {
1224 return retval;
1225 }
1226
1227 /* if the target is in Thumb state, change to ARM state */
1228 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_ITBIT, 1))
1229 {
1230 uint32_t r0_thumb, pc_thumb;
1231 LOG_DEBUG("target entered debug from Thumb state, changing to ARM");
1232 /* Entered debug from Thumb mode */
1233 armv4_5->core_state = ARM_STATE_THUMB;
1234 arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb);
1235 }
1236
1237 /* REVISIT likewise for bit 5 -- switch Jazelle-to-ARM */
1238
1239 /* all register content is now invalid */
1240 register_cache_invalidate(armv4_5->core_cache);
1241
1242 /* SVC, ARM state, IRQ and FIQ disabled */
1243 uint32_t cpsr;
1244
1245 cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 32);
1246 cpsr &= ~0xff;
1247 cpsr |= 0xd3;
1248 arm_set_cpsr(armv4_5, cpsr);
1249 armv4_5->cpsr->dirty = 1;
1250
1251 /* start fetching from 0x0 */
1252 buf_set_u32(armv4_5->pc->value, 0, 32, 0x0);
1253 armv4_5->pc->dirty = 1;
1254 armv4_5->pc->valid = 1;
1255
1256 /* reset registers */
1257 for (i = 0; i <= 14; i++)
1258 {
1259 struct reg *r = arm_reg_current(armv4_5, i);
1260
1261 buf_set_u32(r->value, 0, 32, 0xffffffff);
1262 r->dirty = 1;
1263 r->valid = 1;
1264 }
1265
1266 if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
1267 {
1268 return retval;
1269 }
1270
1271 return ERROR_OK;
1272 }
1273
1274 /**
1275 * Halt an ARM7/9 target. This is accomplished by either asserting the DBGRQ
1276 * line or by programming a watchpoint to trigger on any address. It is
1277 * considered a bug to call this function while the target is in the
1278 * TARGET_RESET state.
1279 *
1280 * @param target Pointer to the ARM7/9 target to be halted
1281 * @return Always ERROR_OK
1282 */
1283 int arm7_9_halt(struct target *target)
1284 {
1285 if (target->state == TARGET_RESET)
1286 {
1287 LOG_ERROR("BUG: arm7/9 does not support halt during reset. This is handled in arm7_9_assert_reset()");
1288 return ERROR_OK;
1289 }
1290
1291 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
1292 struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1293
1294 LOG_DEBUG("target->state: %s",
1295 target_state_name(target));
1296
1297 if (target->state == TARGET_HALTED)
1298 {
1299 LOG_DEBUG("target was already halted");
1300 return ERROR_OK;
1301 }
1302
1303 if (target->state == TARGET_UNKNOWN)
1304 {
1305 LOG_WARNING("target was in unknown state when halt was requested");
1306 }
1307
1308 if (arm7_9->use_dbgrq)
1309 {
1310 /* program EmbeddedICE Debug Control Register to assert DBGRQ
1311 */
1312 if (arm7_9->set_special_dbgrq) {
1313 arm7_9->set_special_dbgrq(target);
1314 } else {
1315 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 1);
1316 embeddedice_store_reg(dbg_ctrl);
1317 }
1318 }
1319 else
1320 {
1321 /* program watchpoint unit to match on any address
1322 */
1323 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
1324 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
1325 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
1326 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
1327 }
1328
1329 target->debug_reason = DBG_REASON_DBGRQ;
1330
1331 return ERROR_OK;
1332 }
1333
1334 /**
1335 * Handle an ARM7/9 target's entry into debug mode. The halt is cleared on the
1336 * ARM. The JTAG queue is then executed and the reason for debug entry is
1337 * examined. Once done, the target is verified to be halted and the processor
1338 * is forced into ARM mode. The core registers are saved for the current core
1339 * mode and the program counter (register 15) is updated as needed. The core
1340 * registers and CPSR and SPSR are saved for restoration later.
1341 *
1342 * @param target Pointer to target that is entering debug mode
1343 * @return Error code if anything fails, otherwise ERROR_OK
1344 */
1345 static int arm7_9_debug_entry(struct target *target)
1346 {
1347 int i;
1348 uint32_t context[16];
1349 uint32_t* context_p[16];
1350 uint32_t r0_thumb, pc_thumb;
1351 uint32_t cpsr, cpsr_mask = 0;
1352 int retval;
1353 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
1354 struct arm *armv4_5 = &arm7_9->armv4_5_common;
1355 struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
1356 struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1357
1358 #ifdef _DEBUG_ARM7_9_
1359 LOG_DEBUG("-");
1360 #endif
1361
1362 /* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS
1363 * ensure that DBGRQ is cleared
1364 */
1365 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
1366 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
1367 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 1);
1368 embeddedice_store_reg(dbg_ctrl);
1369
1370 if ((retval = arm7_9_clear_halt(target)) != ERROR_OK)
1371 {
1372 return retval;
1373 }
1374
1375 if ((retval = jtag_execute_queue()) != ERROR_OK)
1376 {
1377 return retval;
1378 }
1379
1380 if ((retval = arm7_9->examine_debug_reason(target)) != ERROR_OK)
1381 return retval;
1382
1383
1384 if (target->state != TARGET_HALTED)
1385 {
1386 LOG_WARNING("target not halted");
1387 return ERROR_TARGET_NOT_HALTED;
1388 }
1389
1390 /* if the target is in Thumb state, change to ARM state */
1391 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_ITBIT, 1))
1392 {
1393 LOG_DEBUG("target entered debug from Thumb state");
1394 /* Entered debug from Thumb mode */
1395 armv4_5->core_state = ARM_STATE_THUMB;
1396 cpsr_mask = 1 << 5;
1397 arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb);
1398 LOG_DEBUG("r0_thumb: 0x%8.8" PRIx32
1399 ", pc_thumb: 0x%8.8" PRIx32, r0_thumb, pc_thumb);
1400 } else if (buf_get_u32(dbg_stat->value, 5, 1)) {
1401 /* \todo Get some vaguely correct handling of Jazelle, if
1402 * anyone ever uses it and full info becomes available.
1403 * See ARM9EJS TRM B.7.1 for how to switch J->ARM; and
1404 * B.7.3 for the reverse. That'd be the bare minimum...
1405 */
1406 LOG_DEBUG("target entered debug from Jazelle state");
1407 armv4_5->core_state = ARM_STATE_JAZELLE;
1408 cpsr_mask = 1 << 24;
1409 LOG_ERROR("Jazelle debug entry -- BROKEN!");
1410 } else {
1411 LOG_DEBUG("target entered debug from ARM state");
1412 /* Entered debug from ARM mode */
1413 armv4_5->core_state = ARM_STATE_ARM;
1414 }
1415
1416 for (i = 0; i < 16; i++)
1417 context_p[i] = &context[i];
1418 /* save core registers (r0 - r15 of current core mode) */
1419 arm7_9->read_core_regs(target, 0xffff, context_p);
1420
1421 arm7_9->read_xpsr(target, &cpsr, 0);
1422
1423 if ((retval = jtag_execute_queue()) != ERROR_OK)
1424 return retval;
1425
1426 /* Sync our CPSR copy with J or T bits EICE reported, but
1427 * which we then erased by putting the core into ARM mode.
1428 */
1429 arm_set_cpsr(armv4_5, cpsr | cpsr_mask);
1430
1431 if (!is_arm_mode(armv4_5->core_mode))
1432 {
1433 target->state = TARGET_UNKNOWN;
1434 LOG_ERROR("cpsr contains invalid mode value - communication failure");
1435 return ERROR_TARGET_FAILURE;
1436 }
1437
1438 LOG_DEBUG("target entered debug state in %s mode",
1439 arm_mode_name(armv4_5->core_mode));
1440
1441 if (armv4_5->core_state == ARM_STATE_THUMB)
1442 {
1443 LOG_DEBUG("thumb state, applying fixups");
1444 context[0] = r0_thumb;
1445 context[15] = pc_thumb;
1446 } else if (armv4_5->core_state == ARM_STATE_ARM)
1447 {
1448 /* adjust value stored by STM */
1449 context[15] -= 3 * 4;
1450 }
1451
1452 if ((target->debug_reason != DBG_REASON_DBGRQ) || (!arm7_9->use_dbgrq))
1453 context[15] -= 3 * ((armv4_5->core_state == ARM_STATE_ARM) ? 4 : 2);
1454 else
1455 context[15] -= arm7_9->dbgreq_adjust_pc * ((armv4_5->core_state == ARM_STATE_ARM) ? 4 : 2);
1456
1457 for (i = 0; i <= 15; i++)
1458 {
1459 struct reg *r = arm_reg_current(armv4_5, i);
1460
1461 LOG_DEBUG("r%i: 0x%8.8" PRIx32 "", i, context[i]);
1462
1463 buf_set_u32(r->value, 0, 32, context[i]);
1464 /* r0 and r15 (pc) have to be restored later */
1465 r->dirty = (i == 0) || (i == 15);
1466 r->valid = 1;
1467 }
1468
1469 LOG_DEBUG("entered debug state at PC 0x%" PRIx32 "", context[15]);
1470
1471 /* exceptions other than USR & SYS have a saved program status register */
1472 if (armv4_5->spsr) {
1473 uint32_t spsr;
1474 arm7_9->read_xpsr(target, &spsr, 1);
1475 if ((retval = jtag_execute_queue()) != ERROR_OK)
1476 {
1477 return retval;
1478 }
1479 buf_set_u32(armv4_5->spsr->value, 0, 32, spsr);
1480 armv4_5->spsr->dirty = 0;
1481 armv4_5->spsr->valid = 1;
1482 }
1483
1484 if ((retval = jtag_execute_queue()) != ERROR_OK)
1485 return retval;
1486
1487 if (arm7_9->post_debug_entry)
1488 {
1489 retval = arm7_9->post_debug_entry(target);
1490 if (retval != ERROR_OK)
1491 return retval;
1492 }
1493
1494 return ERROR_OK;
1495 }
1496
1497 /**
1498 * Validate the full context for an ARM7/9 target in all processor modes. If
1499 * there are any invalid registers for the target, they will all be read. This
1500 * includes the PSR.
1501 *
1502 * @param target Pointer to the ARM7/9 target to capture the full context from
1503 * @return Error if the target is not halted, has an invalid core mode, or if
1504 * the JTAG queue fails to execute
1505 */
1506 static int arm7_9_full_context(struct target *target)
1507 {
1508 int i;
1509 int retval;
1510 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
1511 struct arm *armv4_5 = &arm7_9->armv4_5_common;
1512
1513 LOG_DEBUG("-");
1514
1515 if (target->state != TARGET_HALTED)
1516 {
1517 LOG_WARNING("target not halted");
1518 return ERROR_TARGET_NOT_HALTED;
1519 }
1520
1521 if (!is_arm_mode(armv4_5->core_mode))
1522 {
1523 LOG_ERROR("not a valid arm core mode - communication failure?");
1524 return ERROR_FAIL;
1525 }
1526
1527 /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
1528 * SYS shares registers with User, so we don't touch SYS
1529 */
1530 for (i = 0; i < 6; i++)
1531 {
1532 uint32_t mask = 0;
1533 uint32_t* reg_p[16];
1534 int j;
1535 int valid = 1;
1536
1537 /* check if there are invalid registers in the current mode
1538 */
1539 for (j = 0; j <= 16; j++)
1540 {
1541 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid == 0)
1542 valid = 0;
1543 }
1544
1545 if (!valid)
1546 {
1547 uint32_t tmp_cpsr;
1548
1549 /* change processor mode (and mask T bit) */
1550 tmp_cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 8)
1551 & 0xe0;
1552 tmp_cpsr |= armv4_5_number_to_mode(i);
1553 tmp_cpsr &= ~0x20;
1554 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1555
1556 for (j = 0; j < 15; j++)
1557 {
1558 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid == 0)
1559 {
1560 reg_p[j] = (uint32_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).value;
1561 mask |= 1 << j;
1562 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid = 1;
1563 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).dirty = 0;
1564 }
1565 }
1566
1567 /* if only the PSR is invalid, mask is all zeroes */
1568 if (mask)
1569 arm7_9->read_core_regs(target, mask, reg_p);
1570
1571 /* check if the PSR has to be read */
1572 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).valid == 0)
1573 {
1574 arm7_9->read_xpsr(target, (uint32_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).value, 1);
1575 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).valid = 1;
1576 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).dirty = 0;
1577 }
1578 }
1579 }
1580
1581 /* restore processor mode (mask T bit) */
1582 arm7_9->write_xpsr_im8(target,
1583 buf_get_u32(armv4_5->cpsr->value, 0, 8) & ~0x20,
1584 0, 0);
1585
1586 if ((retval = jtag_execute_queue()) != ERROR_OK)
1587 {
1588 return retval;
1589 }
1590 return ERROR_OK;
1591 }
1592
1593 /**
1594 * Restore the processor context on an ARM7/9 target. The full processor
1595 * context is analyzed to see if any of the registers are dirty on this end, but
1596 * have a valid new value. If this is the case, the processor is changed to the
1597 * appropriate mode and the new register values are written out to the
1598 * processor. If there happens to be a dirty register with an invalid value, an
1599 * error will be logged.
1600 *
1601 * @param target Pointer to the ARM7/9 target to have its context restored
1602 * @return Error status if the target is not halted or the core mode in the
1603 * armv4_5 struct is invalid.
1604 */
1605 static int arm7_9_restore_context(struct target *target)
1606 {
1607 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
1608 struct arm *armv4_5 = &arm7_9->armv4_5_common;
1609 struct reg *reg;
1610 enum arm_mode current_mode = armv4_5->core_mode;
1611 int i, j;
1612 int dirty;
1613 int mode_change;
1614
1615 LOG_DEBUG("-");
1616
1617 if (target->state != TARGET_HALTED)
1618 {
1619 LOG_WARNING("target not halted");
1620 return ERROR_TARGET_NOT_HALTED;
1621 }
1622
1623 if (arm7_9->pre_restore_context)
1624 arm7_9->pre_restore_context(target);
1625
1626 if (!is_arm_mode(armv4_5->core_mode))
1627 {
1628 LOG_ERROR("not a valid arm core mode - communication failure?");
1629 return ERROR_FAIL;
1630 }
1631
1632 /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
1633 * SYS shares registers with User, so we don't touch SYS
1634 */
1635 for (i = 0; i < 6; i++)
1636 {
1637 LOG_DEBUG("examining %s mode",
1638 arm_mode_name(armv4_5->core_mode));
1639 dirty = 0;
1640 mode_change = 0;
1641 /* check if there are dirty registers in the current mode
1642 */
1643 for (j = 0; j <= 16; j++)
1644 {
1645 reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j);
1646 if (reg->dirty == 1)
1647 {
1648 if (reg->valid == 1)
1649 {
1650 dirty = 1;
1651 LOG_DEBUG("examining dirty reg: %s", reg->name);
1652 struct arm_reg *reg_arch_info;
1653 reg_arch_info = reg->arch_info;
1654 if ((reg_arch_info->mode != ARM_MODE_ANY)
1655 && (reg_arch_info->mode != current_mode)
1656 && !((reg_arch_info->mode == ARM_MODE_USR) && (armv4_5->core_mode == ARM_MODE_SYS))
1657 && !((reg_arch_info->mode == ARM_MODE_SYS) && (armv4_5->core_mode == ARM_MODE_USR)))
1658 {
1659 mode_change = 1;
1660 LOG_DEBUG("require mode change");
1661 }
1662 }
1663 else
1664 {
1665 LOG_ERROR("BUG: dirty register '%s', but no valid data", reg->name);
1666 }
1667 }
1668 }
1669
1670 if (dirty)
1671 {
1672 uint32_t mask = 0x0;
1673 int num_regs = 0;
1674 uint32_t regs[16];
1675
1676 if (mode_change)
1677 {
1678 uint32_t tmp_cpsr;
1679
1680 /* change processor mode (mask T bit) */
1681 tmp_cpsr = buf_get_u32(armv4_5->cpsr->value,
1682 0, 8) & 0xe0;
1683 tmp_cpsr |= armv4_5_number_to_mode(i);
1684 tmp_cpsr &= ~0x20;
1685 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1686 current_mode = armv4_5_number_to_mode(i);
1687 }
1688
1689 for (j = 0; j <= 14; j++)
1690 {
1691 reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j);
1692
1693 if (reg->dirty == 1)
1694 {
1695 regs[j] = buf_get_u32(reg->value, 0, 32);
1696 mask |= 1 << j;
1697 num_regs++;
1698 reg->dirty = 0;
1699 reg->valid = 1;
1700 LOG_DEBUG("writing register %i mode %s "
1701 "with value 0x%8.8" PRIx32, j,
1702 arm_mode_name(armv4_5->core_mode),
1703 regs[j]);
1704 }
1705 }
1706
1707 if (mask)
1708 {
1709 arm7_9->write_core_regs(target, mask, regs);
1710 }
1711
1712 reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16);
1713 struct arm_reg *reg_arch_info;
1714 reg_arch_info = reg->arch_info;
1715 if ((reg->dirty) && (reg_arch_info->mode != ARM_MODE_ANY))
1716 {
1717 LOG_DEBUG("writing SPSR of mode %i with value 0x%8.8" PRIx32 "", i, buf_get_u32(reg->value, 0, 32));
1718 arm7_9->write_xpsr(target, buf_get_u32(reg->value, 0, 32), 1);
1719 }
1720 }
1721 }
1722
1723 if (!armv4_5->cpsr->dirty && (armv4_5->core_mode != current_mode))
1724 {
1725 /* restore processor mode (mask T bit) */
1726 uint32_t tmp_cpsr;
1727
1728 tmp_cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 8) & 0xE0;
1729 tmp_cpsr |= armv4_5_number_to_mode(i);
1730 tmp_cpsr &= ~0x20;
1731 LOG_DEBUG("writing lower 8 bit of cpsr with value 0x%2.2x", (unsigned)(tmp_cpsr));
1732 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1733 }
1734 else if (armv4_5->cpsr->dirty)
1735 {
1736 /* CPSR has been changed, full restore necessary (mask T bit) */
1737 LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32,
1738 buf_get_u32(armv4_5->cpsr->value, 0, 32));
1739 arm7_9->write_xpsr(target,
1740 buf_get_u32(armv4_5->cpsr->value, 0, 32)
1741 & ~0x20, 0);
1742 armv4_5->cpsr->dirty = 0;
1743 armv4_5->cpsr->valid = 1;
1744 }
1745
1746 /* restore PC */
1747 LOG_DEBUG("writing PC with value 0x%8.8" PRIx32,
1748 buf_get_u32(armv4_5->pc->value, 0, 32));
1749 arm7_9->write_pc(target, buf_get_u32(armv4_5->pc->value, 0, 32));
1750 armv4_5->pc->dirty = 0;
1751
1752 return ERROR_OK;
1753 }
1754
1755 /**
1756 * Restart the core of an ARM7/9 target. A RESTART command is sent to the
1757 * instruction register and the JTAG state is set to TAP_IDLE causing a core
1758 * restart.
1759 *
1760 * @param target Pointer to the ARM7/9 target to be restarted
1761 * @return Result of executing the JTAG queue
1762 */
1763 static int arm7_9_restart_core(struct target *target)
1764 {
1765 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
1766 struct arm_jtag *jtag_info = &arm7_9->jtag_info;
1767 int retval;
1768
1769 /* set RESTART instruction */
1770 if (arm7_9->need_bypass_before_restart) {
1771 arm7_9->need_bypass_before_restart = 0;
1772
1773 retval = arm_jtag_set_instr(jtag_info, 0xf, NULL, TAP_IDLE);
1774 if (retval != ERROR_OK)
1775 return retval;
1776 }
1777 retval = arm_jtag_set_instr(jtag_info, 0x4, NULL, TAP_IDLE);
1778 if (retval != ERROR_OK)
1779 return retval;
1780
1781 jtag_add_runtest(1, TAP_IDLE);
1782 return jtag_execute_queue();
1783 }
1784
1785 /**
1786 * Enable the watchpoints on an ARM7/9 target. The target's watchpoints are
1787 * iterated through and are set on the target if they aren't already set.
1788 *
1789 * @param target Pointer to the ARM7/9 target to enable watchpoints on
1790 */
1791 static void arm7_9_enable_watchpoints(struct target *target)
1792 {
1793 struct watchpoint *watchpoint = target->watchpoints;
1794
1795 while (watchpoint)
1796 {
1797 if (watchpoint->set == 0)
1798 arm7_9_set_watchpoint(target, watchpoint);
1799 watchpoint = watchpoint->next;
1800 }
1801 }
1802
1803 /**
1804 * Enable the breakpoints on an ARM7/9 target. The target's breakpoints are
1805 * iterated through and are set on the target.
1806 *
1807 * @param target Pointer to the ARM7/9 target to enable breakpoints on
1808 */
1809 static void arm7_9_enable_breakpoints(struct target *target)
1810 {
1811 struct breakpoint *breakpoint = target->breakpoints;
1812
1813 /* set any pending breakpoints */
1814 while (breakpoint)
1815 {
1816 arm7_9_set_breakpoint(target, breakpoint);
1817 breakpoint = breakpoint->next;
1818 }
1819 }
1820
1821 int arm7_9_resume(struct target *target, int current, uint32_t address, int handle_breakpoints, int debug_execution)
1822 {
1823 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
1824 struct arm *armv4_5 = &arm7_9->armv4_5_common;
1825 struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1826 int err, retval = ERROR_OK;
1827
1828 LOG_DEBUG("-");
1829
1830 if (target->state != TARGET_HALTED)
1831 {
1832 LOG_WARNING("target not halted");
1833 return ERROR_TARGET_NOT_HALTED;
1834 }
1835
1836 if (!debug_execution)
1837 {
1838 target_free_all_working_areas(target);
1839 }
1840
1841 /* current = 1: continue on current pc, otherwise continue at <address> */
1842 if (!current)
1843 buf_set_u32(armv4_5->pc->value, 0, 32, address);
1844
1845 uint32_t current_pc;
1846 current_pc = buf_get_u32(armv4_5->pc->value, 0, 32);
1847
1848 /* the front-end may request us not to handle breakpoints */
1849 if (handle_breakpoints)
1850 {
1851 struct breakpoint *breakpoint;
1852 breakpoint = breakpoint_find(target,
1853 buf_get_u32(armv4_5->pc->value, 0, 32));
1854 if (breakpoint != NULL)
1855 {
1856 LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 " (id: %d)", breakpoint->address, breakpoint->unique_id );
1857 if ((retval = arm7_9_unset_breakpoint(target, breakpoint)) != ERROR_OK)
1858 {
1859 return retval;
1860 }
1861
1862 /* calculate PC of next instruction */
1863 uint32_t next_pc;
1864 if ((retval = arm_simulate_step(target, &next_pc)) != ERROR_OK)
1865 {
1866 uint32_t current_opcode;
1867 target_read_u32(target, current_pc, &current_opcode);
1868 LOG_ERROR("Couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32 "", current_opcode);
1869 return retval;
1870 }
1871
1872 LOG_DEBUG("enable single-step");
1873 arm7_9->enable_single_step(target, next_pc);
1874
1875 target->debug_reason = DBG_REASON_SINGLESTEP;
1876
1877 if ((retval = arm7_9_restore_context(target)) != ERROR_OK)
1878 {
1879 return retval;
1880 }
1881
1882 if (armv4_5->core_state == ARM_STATE_ARM)
1883 arm7_9->branch_resume(target);
1884 else if (armv4_5->core_state == ARM_STATE_THUMB)
1885 {
1886 arm7_9->branch_resume_thumb(target);
1887 }
1888 else
1889 {
1890 LOG_ERROR("unhandled core state");
1891 return ERROR_FAIL;
1892 }
1893
1894 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
1895 embeddedice_write_reg(dbg_ctrl, buf_get_u32(dbg_ctrl->value, 0, dbg_ctrl->size));
1896 err = arm7_9_execute_sys_speed(target);
1897
1898 LOG_DEBUG("disable single-step");
1899 arm7_9->disable_single_step(target);
1900
1901 if (err != ERROR_OK)
1902 {
1903 if ((retval = arm7_9_set_breakpoint(target, breakpoint)) != ERROR_OK)
1904 {
1905 return retval;
1906 }
1907 target->state = TARGET_UNKNOWN;
1908 return err;
1909 }
1910
1911 retval = arm7_9_debug_entry(target);
1912 if (retval != ERROR_OK)
1913 return retval;
1914 LOG_DEBUG("new PC after step: 0x%8.8" PRIx32,
1915 buf_get_u32(armv4_5->pc->value, 0, 32));
1916
1917 LOG_DEBUG("set breakpoint at 0x%8.8" PRIx32 "", breakpoint->address);
1918 if ((retval = arm7_9_set_breakpoint(target, breakpoint)) != ERROR_OK)
1919 {
1920 return retval;
1921 }
1922 }
1923 }
1924
1925 /* enable any pending breakpoints and watchpoints */
1926 arm7_9_enable_breakpoints(target);
1927 arm7_9_enable_watchpoints(target);
1928
1929 if ((retval = arm7_9_restore_context(target)) != ERROR_OK)
1930 {
1931 return retval;
1932 }
1933
1934 if (armv4_5->core_state == ARM_STATE_ARM)
1935 {
1936 arm7_9->branch_resume(target);
1937 }
1938 else if (armv4_5->core_state == ARM_STATE_THUMB)
1939 {
1940 arm7_9->branch_resume_thumb(target);
1941 }
1942 else
1943 {
1944 LOG_ERROR("unhandled core state");
1945 return ERROR_FAIL;
1946 }
1947
1948 /* deassert DBGACK and INTDIS */
1949 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
1950 /* INTDIS only when we really resume, not during debug execution */
1951 if (!debug_execution)
1952 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 0);
1953 embeddedice_write_reg(dbg_ctrl, buf_get_u32(dbg_ctrl->value, 0, dbg_ctrl->size));
1954
1955 if ((retval = arm7_9_restart_core(target)) != ERROR_OK)
1956 {
1957 return retval;
1958 }
1959
1960 target->debug_reason = DBG_REASON_NOTHALTED;
1961
1962 if (!debug_execution)
1963 {
1964 /* registers are now invalid */
1965 register_cache_invalidate(armv4_5->core_cache);
1966 target->state = TARGET_RUNNING;
1967 if ((retval = target_call_event_callbacks(target, TARGET_EVENT_RESUMED)) != ERROR_OK)
1968 {
1969 return retval;
1970 }
1971 }
1972 else
1973 {
1974 target->state = TARGET_DEBUG_RUNNING;
1975 if ((retval = target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED)) != ERROR_OK)
1976 {
1977 return retval;
1978 }
1979 }
1980
1981 LOG_DEBUG("target resumed");
1982
1983 return ERROR_OK;
1984 }
1985
1986 void arm7_9_enable_eice_step(struct target *target, uint32_t next_pc)
1987 {
1988 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
1989 struct arm *armv4_5 = &arm7_9->armv4_5_common;
1990 uint32_t current_pc;
1991 current_pc = buf_get_u32(armv4_5->pc->value, 0, 32);
1992
1993 if (next_pc != current_pc)
1994 {
1995 /* setup an inverse breakpoint on the current PC
1996 * - comparator 1 matches the current address
1997 * - rangeout from comparator 1 is connected to comparator 0 rangein
1998 * - comparator 0 matches any address, as long as rangein is low */
1999 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
2000 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
2001 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
2002 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~(EICE_W_CTRL_RANGE | EICE_W_CTRL_nOPC) & 0xff);
2003 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], current_pc);
2004 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0);
2005 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffff);
2006 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
2007 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
2008 }
2009 else
2010 {
2011 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
2012 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
2013 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
2014 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xff);
2015 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], next_pc);
2016 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0);
2017 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffff);
2018 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
2019 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
2020 }
2021 }
2022
2023 void arm7_9_disable_eice_step(struct target *target)
2024 {
2025 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2026
2027 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
2028 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);
2029 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]);
2030 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK]);
2031 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE]);
2032 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK]);
2033 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK]);
2034 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK]);
2035 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE]);
2036 }
2037
2038 int arm7_9_step(struct target *target, int current, uint32_t address, int handle_breakpoints)
2039 {
2040 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2041 struct arm *armv4_5 = &arm7_9->armv4_5_common;
2042 struct breakpoint *breakpoint = NULL;
2043 int err, retval;
2044
2045 if (target->state != TARGET_HALTED)
2046 {
2047 LOG_WARNING("target not halted");
2048 return ERROR_TARGET_NOT_HALTED;
2049 }
2050
2051 /* current = 1: continue on current pc, otherwise continue at <address> */
2052 if (!current)
2053 buf_set_u32(armv4_5->pc->value, 0, 32, address);
2054
2055 uint32_t current_pc = buf_get_u32(armv4_5->pc->value, 0, 32);
2056
2057 /* the front-end may request us not to handle breakpoints */
2058 if (handle_breakpoints)
2059 breakpoint = breakpoint_find(target, current_pc);
2060 if (breakpoint != NULL) {
2061 retval = arm7_9_unset_breakpoint(target, breakpoint);
2062 if (retval != ERROR_OK)
2063 return retval;
2064 }
2065
2066 target->debug_reason = DBG_REASON_SINGLESTEP;
2067
2068 /* calculate PC of next instruction */
2069 uint32_t next_pc;
2070 if ((retval = arm_simulate_step(target, &next_pc)) != ERROR_OK)
2071 {
2072 uint32_t current_opcode;
2073 target_read_u32(target, current_pc, &current_opcode);
2074 LOG_ERROR("Couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32 "", current_opcode);
2075 return retval;
2076 }
2077
2078 if ((retval = arm7_9_restore_context(target)) != ERROR_OK)
2079 {
2080 return retval;
2081 }
2082
2083 arm7_9->enable_single_step(target, next_pc);
2084
2085 if (armv4_5->core_state == ARM_STATE_ARM)
2086 {
2087 arm7_9->branch_resume(target);
2088 }
2089 else if (armv4_5->core_state == ARM_STATE_THUMB)
2090 {
2091 arm7_9->branch_resume_thumb(target);
2092 }
2093 else
2094 {
2095 LOG_ERROR("unhandled core state");
2096 return ERROR_FAIL;
2097 }
2098
2099 if ((retval = target_call_event_callbacks(target, TARGET_EVENT_RESUMED)) != ERROR_OK)
2100 {
2101 return retval;
2102 }
2103
2104 err = arm7_9_execute_sys_speed(target);
2105 arm7_9->disable_single_step(target);
2106
2107 /* registers are now invalid */
2108 register_cache_invalidate(armv4_5->core_cache);
2109
2110 if (err != ERROR_OK)
2111 {
2112 target->state = TARGET_UNKNOWN;
2113 } else {
2114 retval = arm7_9_debug_entry(target);
2115 if (retval != ERROR_OK)
2116 return retval;
2117 if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
2118 {
2119 return retval;
2120 }
2121 LOG_DEBUG("target stepped");
2122 }
2123
2124 if (breakpoint)
2125 if ((retval = arm7_9_set_breakpoint(target, breakpoint)) != ERROR_OK)
2126 {
2127 return retval;
2128 }
2129
2130 return err;
2131 }
2132
2133 static int arm7_9_read_core_reg(struct target *target, struct reg *r,
2134 int num, enum arm_mode mode)
2135 {
2136 uint32_t* reg_p[16];
2137 int retval;
2138 struct arm_reg *areg = r->arch_info;
2139 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2140 struct arm *armv4_5 = &arm7_9->armv4_5_common;
2141
2142 if (!is_arm_mode(armv4_5->core_mode))
2143 return ERROR_FAIL;
2144 if ((num < 0) || (num > 16))
2145 return ERROR_COMMAND_SYNTAX_ERROR;
2146
2147 if ((mode != ARM_MODE_ANY)
2148 && (mode != armv4_5->core_mode)
2149 && (areg->mode != ARM_MODE_ANY))
2150 {
2151 uint32_t tmp_cpsr;
2152
2153 /* change processor mode (mask T bit) */
2154 tmp_cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 8) & 0xE0;
2155 tmp_cpsr |= mode;
2156 tmp_cpsr &= ~0x20;
2157 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
2158 }
2159
2160 uint32_t value = 0;
2161 if ((num >= 0) && (num <= 15))
2162 {
2163 /* read a normal core register */
2164 reg_p[num] = &value;
2165
2166 arm7_9->read_core_regs(target, 1 << num, reg_p);
2167 }
2168 else
2169 {
2170 /* read a program status register
2171 * if the register mode is MODE_ANY, we read the cpsr, otherwise a spsr
2172 */
2173 arm7_9->read_xpsr(target, &value, areg->mode != ARM_MODE_ANY);
2174 }
2175
2176 if ((retval = jtag_execute_queue()) != ERROR_OK)
2177 {
2178 return retval;
2179 }
2180
2181 r->valid = 1;
2182 r->dirty = 0;
2183 buf_set_u32(r->value, 0, 32, value);
2184
2185 if ((mode != ARM_MODE_ANY)
2186 && (mode != armv4_5->core_mode)
2187 && (areg->mode != ARM_MODE_ANY)) {
2188 /* restore processor mode (mask T bit) */
2189 arm7_9->write_xpsr_im8(target,
2190 buf_get_u32(armv4_5->cpsr->value, 0, 8)
2191 & ~0x20, 0, 0);
2192 }
2193
2194 return ERROR_OK;
2195 }
2196
2197 static int arm7_9_write_core_reg(struct target *target, struct reg *r,
2198 int num, enum arm_mode mode, uint32_t value)
2199 {
2200 uint32_t reg[16];
2201 struct arm_reg *areg = r->arch_info;
2202 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2203 struct arm *armv4_5 = &arm7_9->armv4_5_common;
2204
2205 if (!is_arm_mode(armv4_5->core_mode))
2206 return ERROR_FAIL;
2207 if ((num < 0) || (num > 16))
2208 return ERROR_COMMAND_SYNTAX_ERROR;
2209
2210 if ((mode != ARM_MODE_ANY)
2211 && (mode != armv4_5->core_mode)
2212 && (areg->mode != ARM_MODE_ANY)) {
2213 uint32_t tmp_cpsr;
2214
2215 /* change processor mode (mask T bit) */
2216 tmp_cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 8) & 0xE0;
2217 tmp_cpsr |= mode;
2218 tmp_cpsr &= ~0x20;
2219 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
2220 }
2221
2222 if ((num >= 0) && (num <= 15))
2223 {
2224 /* write a normal core register */
2225 reg[num] = value;
2226
2227 arm7_9->write_core_regs(target, 1 << num, reg);
2228 }
2229 else
2230 {
2231 /* write a program status register
2232 * if the register mode is MODE_ANY, we write the cpsr, otherwise a spsr
2233 */
2234 int spsr = (areg->mode != ARM_MODE_ANY);
2235
2236 /* if we're writing the CPSR, mask the T bit */
2237 if (!spsr)
2238 value &= ~0x20;
2239
2240 arm7_9->write_xpsr(target, value, spsr);
2241 }
2242
2243 r->valid = 1;
2244 r->dirty = 0;
2245
2246 if ((mode != ARM_MODE_ANY)
2247 && (mode != armv4_5->core_mode)
2248 && (areg->mode != ARM_MODE_ANY)) {
2249 /* restore processor mode (mask T bit) */
2250 arm7_9->write_xpsr_im8(target,
2251 buf_get_u32(armv4_5->cpsr->value, 0, 8)
2252 & ~0x20, 0, 0);
2253 }
2254
2255 return jtag_execute_queue();
2256 }
2257
2258 int arm7_9_read_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
2259 {
2260 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2261 struct arm *armv4_5 = &arm7_9->armv4_5_common;
2262 uint32_t reg[16];
2263 uint32_t num_accesses = 0;
2264 int thisrun_accesses;
2265 int i;
2266 uint32_t cpsr;
2267 int retval;
2268 int last_reg = 0;
2269
2270 LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "", address, size, count);
2271
2272 if (target->state != TARGET_HALTED)
2273 {
2274 LOG_WARNING("target not halted");
2275 return ERROR_TARGET_NOT_HALTED;
2276 }
2277
2278 /* sanitize arguments */
2279 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
2280 return ERROR_COMMAND_SYNTAX_ERROR;
2281
2282 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
2283 return ERROR_TARGET_UNALIGNED_ACCESS;
2284
2285 /* load the base register with the address of the first word */
2286 reg[0] = address;
2287 arm7_9->write_core_regs(target, 0x1, reg);
2288
2289 int j = 0;
2290
2291 switch (size)
2292 {
2293 case 4:
2294 while (num_accesses < count)
2295 {
2296 uint32_t reg_list;
2297 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
2298 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2299
2300 if (last_reg <= thisrun_accesses)
2301 last_reg = thisrun_accesses;
2302
2303 arm7_9->load_word_regs(target, reg_list);
2304
2305 /* fast memory reads are only safe when the target is running
2306 * from a sufficiently high clock (32 kHz is usually too slow)
2307 */
2308 if (arm7_9->fast_memory_access)
2309 retval = arm7_9_execute_fast_sys_speed(target);
2310 else
2311 retval = arm7_9_execute_sys_speed(target);
2312 if (retval != ERROR_OK)
2313 return retval;
2314
2315 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 4);
2316
2317 /* advance buffer, count number of accesses */
2318 buffer += thisrun_accesses * 4;
2319 num_accesses += thisrun_accesses;
2320
2321 if ((j++%1024) == 0)
2322 {
2323 keep_alive();
2324 }
2325 }
2326 break;
2327 case 2:
2328 while (num_accesses < count)
2329 {
2330 uint32_t reg_list;
2331 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
2332 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2333
2334 for (i = 1; i <= thisrun_accesses; i++)
2335 {
2336 if (i > last_reg)
2337 last_reg = i;
2338 arm7_9->load_hword_reg(target, i);
2339 /* fast memory reads are only safe when the target is running
2340 * from a sufficiently high clock (32 kHz is usually too slow)
2341 */
2342 if (arm7_9->fast_memory_access)
2343 retval = arm7_9_execute_fast_sys_speed(target);
2344 else
2345 retval = arm7_9_execute_sys_speed(target);
2346 if (retval != ERROR_OK)
2347 {
2348 return retval;
2349 }
2350
2351 }
2352
2353 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 2);
2354
2355 /* advance buffer, count number of accesses */
2356 buffer += thisrun_accesses * 2;
2357 num_accesses += thisrun_accesses;
2358
2359 if ((j++%1024) == 0)
2360 {
2361 keep_alive();
2362 }
2363 }
2364 break;
2365 case 1:
2366 while (num_accesses < count)
2367 {
2368 uint32_t reg_list;
2369 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
2370 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2371
2372 for (i = 1; i <= thisrun_accesses; i++)
2373 {
2374 if (i > last_reg)
2375 last_reg = i;
2376 arm7_9->load_byte_reg(target, i);
2377 /* fast memory reads are only safe when the target is running
2378 * from a sufficiently high clock (32 kHz is usually too slow)
2379 */
2380 if (arm7_9->fast_memory_access)
2381 retval = arm7_9_execute_fast_sys_speed(target);
2382 else
2383 retval = arm7_9_execute_sys_speed(target);
2384 if (retval != ERROR_OK)
2385 {
2386 return retval;
2387 }
2388 }
2389
2390 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 1);
2391
2392 /* advance buffer, count number of accesses */
2393 buffer += thisrun_accesses * 1;
2394 num_accesses += thisrun_accesses;
2395
2396 if ((j++%1024) == 0)
2397 {
2398 keep_alive();
2399 }
2400 }
2401 break;
2402 }
2403
2404 if (!is_arm_mode(armv4_5->core_mode))
2405 return ERROR_FAIL;
2406
2407 for (i = 0; i <= last_reg; i++) {
2408 struct reg *r = arm_reg_current(armv4_5, i);
2409
2410 r->dirty = r->valid;
2411 }
2412
2413 arm7_9->read_xpsr(target, &cpsr, 0);
2414 if ((retval = jtag_execute_queue()) != ERROR_OK)
2415 {
2416 LOG_ERROR("JTAG error while reading cpsr");
2417 return ERROR_TARGET_DATA_ABORT;
2418 }
2419
2420 if (((cpsr & 0x1f) == ARM_MODE_ABT) && (armv4_5->core_mode != ARM_MODE_ABT))
2421 {
2422 LOG_WARNING("memory read caused data abort (address: 0x%8.8" PRIx32 ", size: 0x%" PRIx32 ", count: 0x%" PRIx32 ")", address, size, count);
2423
2424 arm7_9->write_xpsr_im8(target,
2425 buf_get_u32(armv4_5->cpsr->value, 0, 8)
2426 & ~0x20, 0, 0);
2427
2428 return ERROR_TARGET_DATA_ABORT;
2429 }
2430
2431 return ERROR_OK;
2432 }
2433
2434 int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
2435 {
2436 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2437 struct arm *armv4_5 = &arm7_9->armv4_5_common;
2438 struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
2439
2440 uint32_t reg[16];
2441 uint32_t num_accesses = 0;
2442 int thisrun_accesses;
2443 int i;
2444 uint32_t cpsr;
2445 int retval;
2446 int last_reg = 0;
2447
2448 #ifdef _DEBUG_ARM7_9_
2449 LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
2450 #endif
2451
2452 if (target->state != TARGET_HALTED)
2453 {
2454 LOG_WARNING("target not halted");
2455 return ERROR_TARGET_NOT_HALTED;
2456 }
2457
2458 /* sanitize arguments */
2459 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
2460 return ERROR_COMMAND_SYNTAX_ERROR;
2461
2462 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
2463 return ERROR_TARGET_UNALIGNED_ACCESS;
2464
2465 /* load the base register with the address of the first word */
2466 reg[0] = address;
2467 arm7_9->write_core_regs(target, 0x1, reg);
2468
2469 /* Clear DBGACK, to make sure memory fetches work as expected */
2470 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
2471 embeddedice_store_reg(dbg_ctrl);
2472
2473 switch (size)
2474 {
2475 case 4:
2476 while (num_accesses < count)
2477 {
2478 uint32_t reg_list;
2479 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
2480 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2481
2482 for (i = 1; i <= thisrun_accesses; i++)
2483 {
2484 if (i > last_reg)
2485 last_reg = i;
2486 reg[i] = target_buffer_get_u32(target, buffer);
2487 buffer += 4;
2488 }
2489
2490 arm7_9->write_core_regs(target, reg_list, reg);
2491
2492 arm7_9->store_word_regs(target, reg_list);
2493
2494 /* fast memory writes are only safe when the target is running
2495 * from a sufficiently high clock (32 kHz is usually too slow)
2496 */
2497 if (arm7_9->fast_memory_access)
2498 retval = arm7_9_execute_fast_sys_speed(target);
2499 else
2500 {
2501 retval = arm7_9_execute_sys_speed(target);
2502
2503 /*
2504 * if memory writes are made when the clock is running slow
2505 * (i.e. 32 kHz) which is necessary in some scripts to reconfigure
2506 * processor operations after a "reset halt" or "reset init",
2507 * need to immediately stroke the keep alive or will end up with
2508 * gdb "keep alive not sent error message" problem.
2509 */
2510
2511 keep_alive();
2512 }
2513
2514 if (retval != ERROR_OK)
2515 {
2516 return retval;
2517 }
2518
2519 num_accesses += thisrun_accesses;
2520 }
2521 break;
2522 case 2:
2523 while (num_accesses < count)
2524 {
2525 uint32_t reg_list;
2526 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
2527 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2528
2529 for (i = 1; i <= thisrun_accesses; i++)
2530 {
2531 if (i > last_reg)
2532 last_reg = i;
2533 reg[i] = target_buffer_get_u16(target, buffer) & 0xffff;
2534 buffer += 2;
2535 }
2536
2537 arm7_9->write_core_regs(target, reg_list, reg);
2538
2539 for (i = 1; i <= thisrun_accesses; i++)
2540 {
2541 arm7_9->store_hword_reg(target, i);
2542
2543 /* fast memory writes are only safe when the target is running
2544 * from a sufficiently high clock (32 kHz is usually too slow)
2545 */
2546 if (arm7_9->fast_memory_access)
2547 retval = arm7_9_execute_fast_sys_speed(target);
2548 else
2549 {
2550 retval = arm7_9_execute_sys_speed(target);
2551
2552 /*
2553 * if memory writes are made when the clock is running slow
2554 * (i.e. 32 kHz) which is necessary in some scripts to reconfigure
2555 * processor operations after a "reset halt" or "reset init",
2556 * need to immediately stroke the keep alive or will end up with
2557 * gdb "keep alive not sent error message" problem.
2558 */
2559
2560 keep_alive();
2561 }
2562
2563 if (retval != ERROR_OK)
2564 {
2565 return retval;
2566 }
2567 }
2568
2569 num_accesses += thisrun_accesses;
2570 }
2571 break;
2572 case 1:
2573 while (num_accesses < count)
2574 {
2575 uint32_t reg_list;
2576 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
2577 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2578
2579 for (i = 1; i <= thisrun_accesses; i++)
2580 {
2581 if (i > last_reg)
2582 last_reg = i;
2583 reg[i] = *buffer++ & 0xff;
2584 }
2585
2586 arm7_9->write_core_regs(target, reg_list, reg);
2587
2588 for (i = 1; i <= thisrun_accesses; i++)
2589 {
2590 arm7_9->store_byte_reg(target, i);
2591 /* fast memory writes are only safe when the target is running
2592 * from a sufficiently high clock (32 kHz is usually too slow)
2593 */
2594 if (arm7_9->fast_memory_access)
2595 retval = arm7_9_execute_fast_sys_speed(target);
2596 else
2597 {
2598 retval = arm7_9_execute_sys_speed(target);
2599
2600 /*
2601 * if memory writes are made when the clock is running slow
2602 * (i.e. 32 kHz) which is necessary in some scripts to reconfigure
2603 * processor operations after a "reset halt" or "reset init",
2604 * need to immediately stroke the keep alive or will end up with
2605 * gdb "keep alive not sent error message" problem.
2606 */
2607
2608 keep_alive();
2609 }
2610
2611 if (retval != ERROR_OK)
2612 {
2613 return retval;
2614 }
2615
2616 }
2617
2618 num_accesses += thisrun_accesses;
2619 }
2620 break;
2621 }
2622
2623 /* Re-Set DBGACK */
2624 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
2625 embeddedice_store_reg(dbg_ctrl);
2626
2627 if (!is_arm_mode(armv4_5->core_mode))
2628 return ERROR_FAIL;
2629
2630 for (i = 0; i <= last_reg; i++) {
2631 struct reg *r = arm_reg_current(armv4_5, i);
2632
2633 r->dirty = r->valid;
2634 }
2635
2636 arm7_9->read_xpsr(target, &cpsr, 0);
2637 if ((retval = jtag_execute_queue()) != ERROR_OK)
2638 {
2639 LOG_ERROR("JTAG error while reading cpsr");
2640 return ERROR_TARGET_DATA_ABORT;
2641 }
2642
2643 if (((cpsr & 0x1f) == ARM_MODE_ABT) && (armv4_5->core_mode != ARM_MODE_ABT))
2644 {
2645 LOG_WARNING("memory write caused data abort (address: 0x%8.8" PRIx32 ", size: 0x%" PRIx32 ", count: 0x%" PRIx32 ")", address, size, count);
2646
2647 arm7_9->write_xpsr_im8(target,
2648 buf_get_u32(armv4_5->cpsr->value, 0, 8)
2649 & ~0x20, 0, 0);
2650
2651 return ERROR_TARGET_DATA_ABORT;
2652 }
2653
2654 return ERROR_OK;
2655 }
2656
2657 static int dcc_count;
2658 static const uint8_t *dcc_buffer;
2659
2660 static int arm7_9_dcc_completion(struct target *target, uint32_t exit_point, int timeout_ms, void *arch_info)
2661 {
2662 int retval = ERROR_OK;
2663 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2664
2665 if ((retval = target_wait_state(target, TARGET_DEBUG_RUNNING, 500)) != ERROR_OK)
2666 return retval;
2667
2668 int little = target->endianness == TARGET_LITTLE_ENDIAN;
2669 int count = dcc_count;
2670 const uint8_t *buffer = dcc_buffer;
2671 if (count > 2)
2672 {
2673 /* Handle first & last using standard embeddedice_write_reg and the middle ones w/the
2674 * core function repeated. */
2675 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
2676 buffer += 4;
2677
2678 struct embeddedice_reg *ice_reg = arm7_9->eice_cache->reg_list[EICE_COMMS_DATA].arch_info;
2679 uint8_t reg_addr = ice_reg->addr & 0x1f;
2680 struct jtag_tap *tap;
2681 tap = ice_reg->jtag_info->tap;
2682
2683 embeddedice_write_dcc(tap, reg_addr, buffer, little, count-2);
2684 buffer += (count-2)*4;
2685
2686 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
2687 } else
2688 {
2689 int i;
2690 for (i = 0; i < count; i++)
2691 {
2692 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
2693 buffer += 4;
2694 }
2695 }
2696
2697 if ((retval = target_halt(target))!= ERROR_OK)
2698 {
2699 return retval;
2700 }
2701 return target_wait_state(target, TARGET_HALTED, 500);
2702 }
2703
2704 static const uint32_t dcc_code[] =
2705 {
2706 /* r0 == input, points to memory buffer
2707 * r1 == scratch
2708 */
2709
2710 /* spin until DCC control (c0) reports data arrived */
2711 0xee101e10, /* w: mrc p14, #0, r1, c0, c0 */
2712 0xe3110001, /* tst r1, #1 */
2713 0x0afffffc, /* bne w */
2714
2715 /* read word from DCC (c1), write to memory */
2716 0xee111e10, /* mrc p14, #0, r1, c1, c0 */
2717 0xe4801004, /* str r1, [r0], #4 */
2718
2719 /* repeat */
2720 0xeafffff9 /* b w */
2721 };
2722
2723 int arm7_9_bulk_write_memory(struct target *target, uint32_t address, uint32_t count, const uint8_t *buffer)
2724 {
2725 int retval;
2726 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2727 int i;
2728
2729 if (!arm7_9->dcc_downloads)
2730 return target_write_memory(target, address, 4, count, buffer);
2731
2732 /* regrab previously allocated working_area, or allocate a new one */
2733 if (!arm7_9->dcc_working_area)
2734 {
2735 uint8_t dcc_code_buf[6 * 4];
2736
2737 /* make sure we have a working area */
2738 if (target_alloc_working_area(target, 24, &arm7_9->dcc_working_area) != ERROR_OK)
2739 {
2740 LOG_INFO("no working area available, falling back to memory writes");
2741 return target_write_memory(target, address, 4, count, buffer);
2742 }
2743
2744 /* copy target instructions to target endianness */
2745 for (i = 0; i < 6; i++)
2746 {
2747 target_buffer_set_u32(target, dcc_code_buf + i*4, dcc_code[i]);
2748 }
2749
2750 /* write DCC code to working area */
2751 if ((retval = target_write_memory(target, arm7_9->dcc_working_area->address, 4, 6, dcc_code_buf)) != ERROR_OK)
2752 {
2753 return retval;
2754 }
2755 }
2756
2757 struct arm_algorithm armv4_5_info;
2758 struct reg_param reg_params[1];
2759
2760 armv4_5_info.common_magic = ARM_COMMON_MAGIC;
2761 armv4_5_info.core_mode = ARM_MODE_SVC;
2762 armv4_5_info.core_state = ARM_STATE_ARM;
2763
2764 init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT);
2765
2766 buf_set_u32(reg_params[0].value, 0, 32, address);
2767
2768 dcc_count = count;
2769 dcc_buffer = buffer;
2770 retval = armv4_5_run_algorithm_inner(target, 0, NULL, 1, reg_params,
2771 arm7_9->dcc_working_area->address,
2772 arm7_9->dcc_working_area->address + 6*4,
2773 20*1000, &armv4_5_info, arm7_9_dcc_completion);
2774
2775 if (retval == ERROR_OK)
2776 {
2777 uint32_t endaddress = buf_get_u32(reg_params[0].value, 0, 32);
2778 if (endaddress != (address + count*4))
2779 {
2780 LOG_ERROR("DCC write failed, expected end address 0x%08" PRIx32 " got 0x%0" PRIx32 "", (address + count*4), endaddress);
2781 retval = ERROR_FAIL;
2782 }
2783 }
2784
2785 destroy_reg_param(&reg_params[0]);
2786
2787 return retval;
2788 }
2789
2790 /**
2791 * Perform per-target setup that requires JTAG access.
2792 */
2793 int arm7_9_examine(struct target *target)
2794 {
2795 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2796 int retval;
2797
2798 if (!target_was_examined(target)) {
2799 struct reg_cache *t, **cache_p;
2800
2801 t = embeddedice_build_reg_cache(target, arm7_9);
2802 if (t == NULL)
2803 return ERROR_FAIL;
2804
2805 cache_p = register_get_last_cache_p(&target->reg_cache);
2806 (*cache_p) = t;
2807 arm7_9->eice_cache = (*cache_p);
2808
2809 if (arm7_9->armv4_5_common.etm)
2810 (*cache_p)->next = etm_build_reg_cache(target,
2811 &arm7_9->jtag_info,
2812 arm7_9->armv4_5_common.etm);
2813
2814 target_set_examined(target);
2815 }
2816
2817 retval = embeddedice_setup(target);
2818 if (retval == ERROR_OK)
2819 retval = arm7_9_setup(target);
2820 if (retval == ERROR_OK && arm7_9->armv4_5_common.etm)
2821 retval = etm_setup(target);
2822 return retval;
2823 }
2824
2825
2826 int arm7_9_check_reset(struct target *target)
2827 {
2828 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2829
2830 if (get_target_reset_nag() && !arm7_9->dcc_downloads)
2831 {
2832 LOG_WARNING("NOTE! DCC downloads have not been enabled, defaulting to slow memory writes. Type 'help dcc'.");
2833 }
2834
2835 if (get_target_reset_nag() && (target->working_area_size == 0))
2836 {
2837 LOG_WARNING("NOTE! Severe performance degradation without working memory enabled.");
2838 }
2839
2840 if (get_target_reset_nag() && !arm7_9->fast_memory_access)
2841 {
2842 LOG_WARNING("NOTE! Severe performance degradation without fast memory access enabled. Type 'help fast'.");
2843 }
2844
2845 return ERROR_OK;
2846 }
2847
2848 COMMAND_HANDLER(handle_arm7_9_dbgrq_command)
2849 {
2850 struct target *target = get_current_target(CMD_CTX);
2851 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2852
2853 if (!is_arm7_9(arm7_9))
2854 {
2855 command_print(CMD_CTX, "current target isn't an ARM7/ARM9 target");
2856 return ERROR_TARGET_INVALID;
2857 }
2858
2859 if (CMD_ARGC > 0)
2860 COMMAND_PARSE_ENABLE(CMD_ARGV[0],arm7_9->use_dbgrq);
2861
2862 command_print(CMD_CTX, "use of EmbeddedICE dbgrq instead of breakpoint for target halt %s", (arm7_9->use_dbgrq) ? "enabled" : "disabled");
2863
2864 return ERROR_OK;
2865 }
2866
2867 COMMAND_HANDLER(handle_arm7_9_fast_memory_access_command)
2868 {
2869 struct target *target = get_current_target(CMD_CTX);
2870 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2871
2872 if (!is_arm7_9(arm7_9))
2873 {
2874 command_print(CMD_CTX, "current target isn't an ARM7/ARM9 target");
2875 return ERROR_TARGET_INVALID;
2876 }
2877
2878 if (CMD_ARGC > 0)
2879 COMMAND_PARSE_ENABLE(CMD_ARGV[0], arm7_9->fast_memory_access);
2880
2881 command_print(CMD_CTX, "fast memory access is %s", (arm7_9->fast_memory_access) ? "enabled" : "disabled");
2882
2883 return ERROR_OK;
2884 }
2885
2886 COMMAND_HANDLER(handle_arm7_9_dcc_downloads_command)
2887 {
2888 struct target *target = get_current_target(CMD_CTX);
2889 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2890
2891 if (!is_arm7_9(arm7_9))
2892 {
2893 command_print(CMD_CTX, "current target isn't an ARM7/ARM9 target");
2894 return ERROR_TARGET_INVALID;
2895 }
2896
2897 if (CMD_ARGC > 0)
2898 COMMAND_PARSE_ENABLE(CMD_ARGV[0], arm7_9->dcc_downloads);
2899
2900 command_print(CMD_CTX, "dcc downloads are %s", (arm7_9->dcc_downloads) ? "enabled" : "disabled");
2901
2902 return ERROR_OK;
2903 }
2904
2905 static int arm7_9_setup_semihosting(struct target *target, int enable)
2906 {
2907 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2908
2909 if (!is_arm7_9(arm7_9))
2910 {
2911 LOG_USER("current target isn't an ARM7/ARM9 target");
2912 return ERROR_TARGET_INVALID;
2913 }
2914
2915 if (arm7_9->has_vector_catch) {
2916 struct reg *vector_catch = &arm7_9->eice_cache
2917 ->reg_list[EICE_VEC_CATCH];
2918
2919 if (!vector_catch->valid)
2920 embeddedice_read_reg(vector_catch);
2921 buf_set_u32(vector_catch->value, 2, 1, enable);
2922 embeddedice_store_reg(vector_catch);
2923 } else {
2924 /* TODO: allow optional high vectors and/or BKPT_HARD */
2925 if (enable)
2926 breakpoint_add(target, 8, 4, BKPT_SOFT);
2927 else
2928 breakpoint_remove(target, 8);
2929 }
2930
2931 return ERROR_OK;
2932 }
2933
2934 int arm7_9_init_arch_info(struct target *target, struct arm7_9_common *arm7_9)
2935 {
2936 int retval = ERROR_OK;
2937 struct arm *armv4_5 = &arm7_9->armv4_5_common;
2938
2939 arm7_9->common_magic = ARM7_9_COMMON_MAGIC;
2940
2941 if ((retval = arm_jtag_setup_connection(&arm7_9->jtag_info)) != ERROR_OK)
2942 return retval;
2943
2944 /* caller must have allocated via calloc(), so everything's zeroed */
2945
2946 arm7_9->wp_available_max = 2;
2947
2948 arm7_9->fast_memory_access = false;
2949 arm7_9->dcc_downloads = false;
2950
2951 armv4_5->arch_info = arm7_9;
2952 armv4_5->read_core_reg = arm7_9_read_core_reg;
2953 armv4_5->write_core_reg = arm7_9_write_core_reg;
2954 armv4_5->full_context = arm7_9_full_context;
2955 armv4_5->setup_semihosting = arm7_9_setup_semihosting;
2956
2957 retval = arm_init_arch_info(target, armv4_5);
2958 if (retval != ERROR_OK)
2959 return retval;
2960
2961 return target_register_timer_callback(arm7_9_handle_target_request,
2962 1, 1, target);
2963 }
2964
2965 static const struct command_registration arm7_9_any_command_handlers[] = {
2966 {
2967 "dbgrq",
2968 .handler = handle_arm7_9_dbgrq_command,
2969 .mode = COMMAND_ANY,
2970 .usage = "['enable'|'disable']",
2971 .help = "use EmbeddedICE dbgrq instead of breakpoint "
2972 "for target halt requests",
2973 },
2974 {
2975 "fast_memory_access",
2976 .handler = handle_arm7_9_fast_memory_access_command,
2977 .mode = COMMAND_ANY,
2978 .usage = "['enable'|'disable']",
2979 .help = "use fast memory accesses instead of slower "
2980 "but potentially safer accesses",
2981 },
2982 {
2983 "dcc_downloads",
2984 .handler = handle_arm7_9_dcc_downloads_command,
2985 .mode = COMMAND_ANY,
2986 .usage = "['enable'|'disable']",
2987 .help = "use DCC downloads for larger memory writes",
2988 },
2989 COMMAND_REGISTRATION_DONE
2990 };
2991 const struct command_registration arm7_9_command_handlers[] = {
2992 {
2993 .chain = arm_command_handlers,
2994 },
2995 {
2996 .chain = etm_command_handlers,
2997 },
2998 {
2999 .name = "arm7_9",
3000 .mode = COMMAND_ANY,
3001 .help = "arm7/9 specific commands",
3002 .usage = "",
3003 .chain = arm7_9_any_command_handlers,
3004 },
3005 COMMAND_REGISTRATION_DONE
3006 };