1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
24 #include "replacements.h"
26 #include "embeddedice.h"
28 #include "target_request.h"
33 #include "arm7_9_common.h"
34 #include "breakpoints.h"
40 #include <sys/types.h>
45 int arm7_9_debug_entry(target_t
*target
);
46 int arm7_9_enable_sw_bkpts(struct target_s
*target
);
48 /* command handler forward declarations */
49 int handle_arm7_9_write_xpsr_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
50 int handle_arm7_9_write_xpsr_im8_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
51 int handle_arm7_9_read_core_reg_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
52 int handle_arm7_9_write_core_reg_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
53 int handle_arm7_9_sw_bkpts_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
54 int handle_arm7_9_force_hw_bkpts_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
55 int handle_arm7_9_dbgrq_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
56 int handle_arm7_9_fast_memory_access_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
57 int handle_arm7_9_dcc_downloads_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
58 int handle_arm7_9_etm_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
60 int arm7_9_reinit_embeddedice(target_t
*target
)
62 armv4_5_common_t
*armv4_5
= target
->arch_info
;
63 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
65 breakpoint_t
*breakpoint
= target
->breakpoints
;
67 arm7_9
->wp_available
= 2;
71 /* mark all hardware breakpoints as unset */
74 if (breakpoint
->type
== BKPT_HARD
)
78 breakpoint
= breakpoint
->next
;
81 if (arm7_9
->sw_bkpts_enabled
&& arm7_9
->sw_bkpts_use_wp
)
83 arm7_9
->sw_bkpts_enabled
= 0;
84 arm7_9_enable_sw_bkpts(target
);
87 arm7_9
->reinit_embeddedice
= 0;
92 int arm7_9_jtag_callback(enum jtag_event event
, void *priv
)
94 target_t
*target
= priv
;
95 armv4_5_common_t
*armv4_5
= target
->arch_info
;
96 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
98 /* a test-logic reset occured
99 * the EmbeddedICE registers have been reset
100 * hardware breakpoints have been cleared
102 if (event
== JTAG_TRST_ASSERTED
)
104 arm7_9
->reinit_embeddedice
= 1;
110 int arm7_9_get_arch_pointers(target_t
*target
, armv4_5_common_t
**armv4_5_p
, arm7_9_common_t
**arm7_9_p
)
112 armv4_5_common_t
*armv4_5
= target
->arch_info
;
113 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
115 if (armv4_5
->common_magic
!= ARMV4_5_COMMON_MAGIC
)
120 if (arm7_9
->common_magic
!= ARM7_9_COMMON_MAGIC
)
125 *armv4_5_p
= armv4_5
;
131 int arm7_9_set_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
)
133 armv4_5_common_t
*armv4_5
= target
->arch_info
;
134 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
136 if (target
->state
!= TARGET_HALTED
)
138 WARNING("target not halted");
139 return ERROR_TARGET_NOT_HALTED
;
142 if (arm7_9
->force_hw_bkpts
)
143 breakpoint
->type
= BKPT_HARD
;
147 WARNING("breakpoint already set");
151 if (breakpoint
->type
== BKPT_HARD
)
153 /* either an ARM (4 byte) or Thumb (2 byte) breakpoint */
154 u32 mask
= (breakpoint
->length
== 4) ? 0x3u
: 0x1u
;
155 if (!arm7_9
->wp0_used
)
157 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_VALUE
], breakpoint
->address
);
158 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_MASK
], mask
);
159 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_DATA_MASK
], 0xffffffffu
);
160 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_MASK
], ~EICE_W_CTRL_nOPC
& 0xff);
161 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
], EICE_W_CTRL_ENABLE
);
163 jtag_execute_queue();
164 arm7_9
->wp0_used
= 1;
167 else if (!arm7_9
->wp1_used
)
169 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_ADDR_VALUE
], breakpoint
->address
);
170 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_ADDR_MASK
], mask
);
171 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_DATA_MASK
], 0xffffffffu
);
172 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_MASK
], ~EICE_W_CTRL_nOPC
& 0xff);
173 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_VALUE
], EICE_W_CTRL_ENABLE
);
175 jtag_execute_queue();
176 arm7_9
->wp1_used
= 1;
181 ERROR("BUG: no hardware comparator available");
185 else if (breakpoint
->type
== BKPT_SOFT
)
187 if (breakpoint
->length
== 4)
189 u32 verify
= 0xffffffff;
190 /* keep the original instruction in target endianness */
191 target
->type
->read_memory(target
, breakpoint
->address
, 4, 1, breakpoint
->orig_instr
);
192 /* write the breakpoint instruction in target endianness (arm7_9->arm_bkpt is host endian) */
193 target_write_u32(target
, breakpoint
->address
, arm7_9
->arm_bkpt
);
195 target
->type
->read_memory(target
, breakpoint
->address
, 4, 1, (u8
*)&verify
);
196 if (verify
!= arm7_9
->arm_bkpt
)
198 ERROR("Unable to set 32 bit software breakpoint at address %08x", breakpoint
->address
);
205 /* keep the original instruction in target endianness */
206 target
->type
->read_memory(target
, breakpoint
->address
, 2, 1, breakpoint
->orig_instr
);
207 /* write the breakpoint instruction in target endianness (arm7_9->thumb_bkpt is host endian) */
208 target_write_u16(target
, breakpoint
->address
, arm7_9
->thumb_bkpt
);
210 target
->type
->read_memory(target
, breakpoint
->address
, 2, 1, (u8
*)&verify
);
211 if (verify
!= arm7_9
->thumb_bkpt
)
213 ERROR("Unable to set thumb software breakpoint at address %08x", breakpoint
->address
);
224 int arm7_9_unset_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
)
226 armv4_5_common_t
*armv4_5
= target
->arch_info
;
227 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
229 if (target
->state
!= TARGET_HALTED
)
231 WARNING("target not halted");
232 return ERROR_TARGET_NOT_HALTED
;
235 if (!breakpoint
->set
)
237 WARNING("breakpoint not set");
241 if (breakpoint
->type
== BKPT_HARD
)
243 if (breakpoint
->set
== 1)
245 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
], 0x0);
246 jtag_execute_queue();
247 arm7_9
->wp0_used
= 0;
249 else if (breakpoint
->set
== 2)
251 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_VALUE
], 0x0);
252 jtag_execute_queue();
253 arm7_9
->wp1_used
= 0;
259 /* restore original instruction (kept in target endianness) */
260 if (breakpoint
->length
== 4)
263 /* check that user program as not modified breakpoint instruction */
264 target
->type
->read_memory(target
, breakpoint
->address
, 4, 1, (u8
*)¤t_instr
);
265 if (current_instr
==arm7_9
->arm_bkpt
)
266 target
->type
->write_memory(target
, breakpoint
->address
, 4, 1, breakpoint
->orig_instr
);
271 /* check that user program as not modified breakpoint instruction */
272 target
->type
->read_memory(target
, breakpoint
->address
, 2, 1, (u8
*)¤t_instr
);
273 if (current_instr
==arm7_9
->thumb_bkpt
)
274 target
->type
->write_memory(target
, breakpoint
->address
, 2, 1, breakpoint
->orig_instr
);
282 int arm7_9_add_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
)
284 armv4_5_common_t
*armv4_5
= target
->arch_info
;
285 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
287 if (target
->state
!= TARGET_HALTED
)
289 WARNING("target not halted");
290 return ERROR_TARGET_NOT_HALTED
;
293 if (arm7_9
->force_hw_bkpts
)
295 DEBUG("forcing use of hardware breakpoint at address 0x%8.8x", breakpoint
->address
);
296 breakpoint
->type
= BKPT_HARD
;
299 if ((breakpoint
->type
== BKPT_SOFT
) && (arm7_9
->sw_bkpts_enabled
== 0))
301 INFO("sw breakpoint requested, but software breakpoints not enabled");
302 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
305 if ((breakpoint
->type
== BKPT_HARD
) && (arm7_9
->wp_available
< 1))
307 INFO("no watchpoint unit available for hardware breakpoint");
308 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
311 if ((breakpoint
->length
!= 2) && (breakpoint
->length
!= 4))
313 INFO("only breakpoints of two (Thumb) or four (ARM) bytes length supported");
314 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
317 if (breakpoint
->type
== BKPT_HARD
)
318 arm7_9
->wp_available
--;
323 int arm7_9_remove_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
)
325 armv4_5_common_t
*armv4_5
= target
->arch_info
;
326 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
328 if (target
->state
!= TARGET_HALTED
)
330 WARNING("target not halted");
331 return ERROR_TARGET_NOT_HALTED
;
336 arm7_9_unset_breakpoint(target
, breakpoint
);
339 if (breakpoint
->type
== BKPT_HARD
)
340 arm7_9
->wp_available
++;
345 int arm7_9_set_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
)
347 armv4_5_common_t
*armv4_5
= target
->arch_info
;
348 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
352 mask
= watchpoint
->length
- 1;
354 if (target
->state
!= TARGET_HALTED
)
356 WARNING("target not halted");
357 return ERROR_TARGET_NOT_HALTED
;
360 if (watchpoint
->rw
== WPT_ACCESS
)
365 if (!arm7_9
->wp0_used
)
367 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_VALUE
], watchpoint
->address
);
368 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_MASK
], mask
);
369 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_DATA_MASK
], watchpoint
->mask
);
370 if( watchpoint
->mask
!= 0xffffffffu
)
371 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_DATA_VALUE
], watchpoint
->value
);
372 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_MASK
], 0xff & ~EICE_W_CTRL_nOPC
& ~rw_mask
);
373 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
], EICE_W_CTRL_ENABLE
| EICE_W_CTRL_nOPC
| (watchpoint
->rw
& 1));
375 jtag_execute_queue();
377 arm7_9
->wp0_used
= 2;
379 else if (!arm7_9
->wp1_used
)
381 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_ADDR_VALUE
], watchpoint
->address
);
382 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_ADDR_MASK
], mask
);
383 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_DATA_MASK
], watchpoint
->mask
);
384 if( watchpoint
->mask
!= 0xffffffffu
)
385 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_DATA_VALUE
], watchpoint
->value
);
386 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_MASK
], 0xff & ~EICE_W_CTRL_nOPC
& ~rw_mask
);
387 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_VALUE
], EICE_W_CTRL_ENABLE
| EICE_W_CTRL_nOPC
| (watchpoint
->rw
& 1));
389 jtag_execute_queue();
391 arm7_9
->wp1_used
= 2;
395 ERROR("BUG: no hardware comparator available");
402 int arm7_9_unset_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
)
404 armv4_5_common_t
*armv4_5
= target
->arch_info
;
405 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
407 if (target
->state
!= TARGET_HALTED
)
409 WARNING("target not halted");
410 return ERROR_TARGET_NOT_HALTED
;
413 if (!watchpoint
->set
)
415 WARNING("breakpoint not set");
419 if (watchpoint
->set
== 1)
421 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
], 0x0);
422 jtag_execute_queue();
423 arm7_9
->wp0_used
= 0;
425 else if (watchpoint
->set
== 2)
427 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_VALUE
], 0x0);
428 jtag_execute_queue();
429 arm7_9
->wp1_used
= 0;
436 int arm7_9_add_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
)
438 armv4_5_common_t
*armv4_5
= target
->arch_info
;
439 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
441 if (target
->state
!= TARGET_HALTED
)
443 WARNING("target not halted");
444 return ERROR_TARGET_NOT_HALTED
;
447 if (arm7_9
->wp_available
< 1)
449 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
452 if ((watchpoint
->length
!= 1) && (watchpoint
->length
!= 2) && (watchpoint
->length
!= 4))
454 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
457 arm7_9
->wp_available
--;
462 int arm7_9_remove_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
)
464 armv4_5_common_t
*armv4_5
= target
->arch_info
;
465 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
467 if (target
->state
!= TARGET_HALTED
)
469 WARNING("target not halted");
470 return ERROR_TARGET_NOT_HALTED
;
475 arm7_9_unset_watchpoint(target
, watchpoint
);
478 arm7_9
->wp_available
++;
483 int arm7_9_enable_sw_bkpts(struct target_s
*target
)
485 armv4_5_common_t
*armv4_5
= target
->arch_info
;
486 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
489 if (arm7_9
->sw_bkpts_enabled
)
492 if (arm7_9
->wp_available
< 1)
494 WARNING("can't enable sw breakpoints with no watchpoint unit available");
495 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
497 arm7_9
->wp_available
--;
499 if (!arm7_9
->wp0_used
)
501 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_DATA_VALUE
], arm7_9
->arm_bkpt
);
502 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_DATA_MASK
], 0x0);
503 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_MASK
], 0xffffffffu
);
504 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_MASK
], ~EICE_W_CTRL_nOPC
& 0xff);
505 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
], EICE_W_CTRL_ENABLE
);
506 arm7_9
->sw_bkpts_enabled
= 1;
507 arm7_9
->wp0_used
= 3;
509 else if (!arm7_9
->wp1_used
)
511 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_DATA_VALUE
], arm7_9
->arm_bkpt
);
512 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_DATA_MASK
], 0x0);
513 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_ADDR_MASK
], 0xffffffffu
);
514 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_MASK
], ~EICE_W_CTRL_nOPC
& 0xff);
515 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_VALUE
], EICE_W_CTRL_ENABLE
);
516 arm7_9
->sw_bkpts_enabled
= 2;
517 arm7_9
->wp1_used
= 3;
521 ERROR("BUG: both watchpoints used, but wp_available >= 1");
525 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
527 ERROR("error writing EmbeddedICE registers to enable sw breakpoints");
534 int arm7_9_disable_sw_bkpts(struct target_s
*target
)
536 armv4_5_common_t
*armv4_5
= target
->arch_info
;
537 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
539 if (!arm7_9
->sw_bkpts_enabled
)
542 if (arm7_9
->sw_bkpts_enabled
== 1)
544 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
], 0x0);
545 arm7_9
->sw_bkpts_enabled
= 0;
546 arm7_9
->wp0_used
= 0;
547 arm7_9
->wp_available
++;
549 else if (arm7_9
->sw_bkpts_enabled
== 2)
551 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_VALUE
], 0x0);
552 arm7_9
->sw_bkpts_enabled
= 0;
553 arm7_9
->wp1_used
= 0;
554 arm7_9
->wp_available
++;
560 int arm7_9_execute_sys_speed(struct target_s
*target
)
565 armv4_5_common_t
*armv4_5
= target
->arch_info
;
566 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
567 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
568 reg_t
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
570 /* set RESTART instruction */
571 jtag_add_end_state(TAP_RTI
);
572 arm_jtag_set_instr(jtag_info
, 0x4, NULL
);
574 for (timeout
=0; timeout
<50; timeout
++)
576 /* read debug status register */
577 embeddedice_read_reg(dbg_stat
);
578 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
580 if ((buf_get_u32(dbg_stat
->value
, EICE_DBG_STATUS_DBGACK
, 1))
581 && (buf_get_u32(dbg_stat
->value
, EICE_DBG_STATUS_SYSCOMP
, 1)))
587 ERROR("timeout waiting for SYSCOMP & DBGACK, last DBG_STATUS: %x", buf_get_u32(dbg_stat
->value
, 0, dbg_stat
->size
));
588 return ERROR_TARGET_TIMEOUT
;
594 int arm7_9_execute_fast_sys_speed(struct target_s
*target
)
597 static u8 check_value
[4], check_mask
[4];
599 armv4_5_common_t
*armv4_5
= target
->arch_info
;
600 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
601 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
602 reg_t
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
604 /* set RESTART instruction */
605 jtag_add_end_state(TAP_RTI
);
606 arm_jtag_set_instr(jtag_info
, 0x4, NULL
);
610 /* check for DBGACK and SYSCOMP set (others don't care) */
612 /* NB! These are constants that must be available until after next jtag_execute() and
613 we evaluate the values upon first execution in lieu of setting up these constants
616 buf_set_u32(check_value
, 0, 32, 0x9);
617 buf_set_u32(check_mask
, 0, 32, 0x9);
621 /* read debug status register */
622 embeddedice_read_reg_w_check(dbg_stat
, check_value
, check_value
);
627 int arm7_9_target_request_data(target_t
*target
, u32 size
, u8
*buffer
)
629 armv4_5_common_t
*armv4_5
= target
->arch_info
;
630 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
631 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
635 data
= malloc(size
* (sizeof(u32
)));
637 embeddedice_receive(jtag_info
, data
, size
);
639 for (i
= 0; i
< size
; i
++)
641 h_u32_to_le(buffer
+ (i
* 4), data
[i
]);
649 int arm7_9_handle_target_request(void *priv
)
651 target_t
*target
= priv
;
652 armv4_5_common_t
*armv4_5
= target
->arch_info
;
653 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
654 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
655 reg_t
*dcc_control
= &arm7_9
->eice_cache
->reg_list
[EICE_COMMS_CTRL
];
657 if (!target
->dbg_msg_enabled
)
660 if (target
->state
== TARGET_RUNNING
)
662 /* read DCC control register */
663 embeddedice_read_reg(dcc_control
);
664 jtag_execute_queue();
667 if (buf_get_u32(dcc_control
->value
, 1, 1) == 1)
671 embeddedice_receive(jtag_info
, &request
, 1);
672 target_request(target
, request
);
679 int arm7_9_poll(target_t
*target
)
682 armv4_5_common_t
*armv4_5
= target
->arch_info
;
683 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
684 reg_t
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
686 if (arm7_9
->reinit_embeddedice
)
688 arm7_9_reinit_embeddedice(target
);
691 /* read debug status register */
692 embeddedice_read_reg(dbg_stat
);
693 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
698 if (buf_get_u32(dbg_stat
->value
, EICE_DBG_STATUS_DBGACK
, 1))
700 DEBUG("DBGACK set, dbg_state->value: 0x%x", buf_get_u32(dbg_stat
->value
, 0, 32));
701 if (target
->state
== TARGET_UNKNOWN
)
703 target
->state
= TARGET_RUNNING
;
704 WARNING("DBGACK set while target was in unknown state. Reset or initialize target.");
706 if ((target
->state
== TARGET_RUNNING
) || (target
->state
== TARGET_RESET
))
708 target
->state
= TARGET_HALTED
;
709 if ((retval
= arm7_9_debug_entry(target
)) != ERROR_OK
)
712 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
714 if (target
->state
== TARGET_DEBUG_RUNNING
)
716 target
->state
= TARGET_HALTED
;
717 if ((retval
= arm7_9_debug_entry(target
)) != ERROR_OK
)
720 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_HALTED
);
722 if (target
->state
!= TARGET_HALTED
)
724 WARNING("DBGACK set, but the target did not end up in the halted stated %d", target
->state
);
729 if (target
->state
!= TARGET_DEBUG_RUNNING
)
730 target
->state
= TARGET_RUNNING
;
736 int arm7_9_assert_reset(target_t
*target
)
740 DEBUG("target->state: %s", target_state_strings
[target
->state
]);
742 if (target
->state
== TARGET_HALTED
|| target
->state
== TARGET_UNKNOWN
)
744 /* if the target wasn't running, there might be working areas allocated */
745 target_free_all_working_areas(target
);
747 /* assert SRST and TRST */
748 /* system would get ouf sync if we didn't reset test-logic, too */
749 if ((retval
= jtag_add_reset(1, 1)) != ERROR_OK
)
751 if (retval
== ERROR_JTAG_RESET_CANT_SRST
)
753 WARNING("can't assert srst");
758 ERROR("unknown error");
762 jtag_add_sleep(5000);
763 if ((retval
= jtag_add_reset(0, 1)) != ERROR_OK
)
765 if (retval
== ERROR_JTAG_RESET_WOULD_ASSERT_TRST
)
767 retval
= jtag_add_reset(1, 1);
773 if ((retval
= jtag_add_reset(0, 1)) != ERROR_OK
)
775 if (retval
== ERROR_JTAG_RESET_WOULD_ASSERT_TRST
)
777 retval
= jtag_add_reset(1, 1);
780 if (retval
== ERROR_JTAG_RESET_CANT_SRST
)
782 WARNING("can't assert srst");
785 else if (retval
!= ERROR_OK
)
787 ERROR("unknown error");
793 target
->state
= TARGET_RESET
;
794 jtag_add_sleep(50000);
796 armv4_5_invalidate_core_regs(target
);
802 int arm7_9_deassert_reset(target_t
*target
)
804 DEBUG("target->state: %s", target_state_strings
[target
->state
]);
806 /* deassert reset lines */
807 jtag_add_reset(0, 0);
812 int arm7_9_clear_halt(target_t
*target
)
814 armv4_5_common_t
*armv4_5
= target
->arch_info
;
815 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
816 reg_t
*dbg_ctrl
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_CTRL
];
818 /* we used DBGRQ only if we didn't come out of reset */
819 if (!arm7_9
->debug_entry_from_reset
&& arm7_9
->use_dbgrq
)
821 /* program EmbeddedICE Debug Control Register to deassert DBGRQ
823 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_DBGRQ
, 1, 0);
824 embeddedice_store_reg(dbg_ctrl
);
828 if (arm7_9
->debug_entry_from_reset
&& arm7_9
->has_vector_catch
)
830 /* if we came out of reset, and vector catch is supported, we used
831 * vector catch to enter debug state
832 * restore the register in that case
834 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_VEC_CATCH
]);
838 /* restore registers if watchpoint unit 0 was in use
840 if (arm7_9
->wp0_used
)
842 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_MASK
]);
843 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_DATA_MASK
]);
844 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_MASK
]);
846 /* control value always has to be restored, as it was either disabled,
847 * or enabled with possibly different bits
849 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
]);
856 int arm7_9_soft_reset_halt(struct target_s
*target
)
858 armv4_5_common_t
*armv4_5
= target
->arch_info
;
859 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
860 reg_t
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
861 reg_t
*dbg_ctrl
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_CTRL
];
864 if (target
->state
== TARGET_RUNNING
)
866 target
->type
->halt(target
);
869 while (buf_get_u32(dbg_stat
->value
, EICE_DBG_STATUS_DBGACK
, 1) == 0)
871 embeddedice_read_reg(dbg_stat
);
872 jtag_execute_queue();
874 target
->state
= TARGET_HALTED
;
876 /* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS
877 * ensure that DBGRQ is cleared
879 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_DBGACK
, 1, 1);
880 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_DBGRQ
, 1, 0);
881 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_INTDIS
, 1, 1);
882 embeddedice_store_reg(dbg_ctrl
);
884 arm7_9_clear_halt(target
);
886 /* if the target is in Thumb state, change to ARM state */
887 if (buf_get_u32(dbg_stat
->value
, EICE_DBG_STATUS_ITBIT
, 1))
889 u32 r0_thumb
, pc_thumb
;
890 DEBUG("target entered debug from Thumb state, changing to ARM");
891 /* Entered debug from Thumb mode */
892 armv4_5
->core_state
= ARMV4_5_STATE_THUMB
;
893 arm7_9
->change_to_arm(target
, &r0_thumb
, &pc_thumb
);
896 /* all register content is now invalid */
897 armv4_5_invalidate_core_regs(target
);
899 /* SVC, ARM state, IRQ and FIQ disabled */
900 buf_set_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8, 0xd3);
901 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].dirty
= 1;
902 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].valid
= 1;
904 /* start fetching from 0x0 */
905 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, 0x0);
906 armv4_5
->core_cache
->reg_list
[15].dirty
= 1;
907 armv4_5
->core_cache
->reg_list
[15].valid
= 1;
909 armv4_5
->core_mode
= ARMV4_5_MODE_SVC
;
910 armv4_5
->core_state
= ARMV4_5_STATE_ARM
;
912 /* reset registers */
913 for (i
= 0; i
<= 14; i
++)
915 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).value
, 0, 32, 0xffffffff);
916 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).dirty
= 1;
917 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).valid
= 1;
920 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
925 int arm7_9_prepare_reset_halt(target_t
*target
)
927 armv4_5_common_t
*armv4_5
= target
->arch_info
;
928 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
930 /* poll the target, and resume if it was currently halted */
932 if (target
->state
== TARGET_HALTED
)
934 arm7_9_resume(target
, 1, 0x0, 0, 1);
937 if (arm7_9
->has_vector_catch
)
939 /* program vector catch register to catch reset vector */
940 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_VEC_CATCH
], 0x1);
944 /* program watchpoint unit to match on reset vector address */
945 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_MASK
], 0x3);
946 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_DATA_MASK
], 0x0);
947 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
], 0x100);
948 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_MASK
], 0xf7);
954 int arm7_9_halt(target_t
*target
)
956 armv4_5_common_t
*armv4_5
= target
->arch_info
;
957 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
958 reg_t
*dbg_ctrl
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_CTRL
];
960 DEBUG("target->state: %s", target_state_strings
[target
->state
]);
962 if (target
->state
== TARGET_HALTED
)
964 WARNING("target was already halted");
965 return ERROR_TARGET_ALREADY_HALTED
;
968 if (target
->state
== TARGET_UNKNOWN
)
970 WARNING("target was in unknown state when halt was requested");
973 if (target
->state
== TARGET_RESET
)
975 if ((jtag_reset_config
& RESET_SRST_PULLS_TRST
) && jtag_srst
)
977 ERROR("can't request a halt while in reset if nSRST pulls nTRST");
978 return ERROR_TARGET_FAILURE
;
982 /* we came here in a reset_halt or reset_init sequence
983 * debug entry was already prepared in arm7_9_prepare_reset_halt()
985 target
->debug_reason
= DBG_REASON_DBGRQ
;
991 if (arm7_9
->use_dbgrq
)
993 /* program EmbeddedICE Debug Control Register to assert DBGRQ
995 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_DBGRQ
, 1, 1);
996 embeddedice_store_reg(dbg_ctrl
);
1000 /* program watchpoint unit to match on any address
1002 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_MASK
], 0xffffffff);
1003 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_DATA_MASK
], 0xffffffff);
1004 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
], 0x100);
1005 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_MASK
], 0xf7);
1008 target
->debug_reason
= DBG_REASON_DBGRQ
;
1013 int arm7_9_debug_entry(target_t
*target
)
1018 u32 r0_thumb
, pc_thumb
;
1021 /* get pointers to arch-specific information */
1022 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1023 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
1024 reg_t
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
1025 reg_t
*dbg_ctrl
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_CTRL
];
1027 #ifdef _DEBUG_ARM7_9_
1031 if (arm7_9
->pre_debug_entry
)
1032 arm7_9
->pre_debug_entry(target
);
1034 /* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS
1035 * ensure that DBGRQ is cleared
1037 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_DBGACK
, 1, 1);
1038 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_DBGRQ
, 1, 0);
1039 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_INTDIS
, 1, 1);
1040 embeddedice_store_reg(dbg_ctrl
);
1042 arm7_9_clear_halt(target
);
1044 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1048 case ERROR_JTAG_QUEUE_FAILED
:
1049 ERROR("JTAG queue failed while writing EmbeddedICE control register");
1057 if ((retval
= arm7_9
->examine_debug_reason(target
)) != ERROR_OK
)
1061 if (target
->state
!= TARGET_HALTED
)
1063 WARNING("target not halted");
1064 return ERROR_TARGET_NOT_HALTED
;
1067 /* if the target is in Thumb state, change to ARM state */
1068 if (buf_get_u32(dbg_stat
->value
, EICE_DBG_STATUS_ITBIT
, 1))
1070 DEBUG("target entered debug from Thumb state");
1071 /* Entered debug from Thumb mode */
1072 armv4_5
->core_state
= ARMV4_5_STATE_THUMB
;
1073 arm7_9
->change_to_arm(target
, &r0_thumb
, &pc_thumb
);
1074 DEBUG("r0_thumb: 0x%8.8x, pc_thumb: 0x%8.8x", r0_thumb
, pc_thumb
);
1078 DEBUG("target entered debug from ARM state");
1079 /* Entered debug from ARM mode */
1080 armv4_5
->core_state
= ARMV4_5_STATE_ARM
;
1083 for (i
= 0; i
< 16; i
++)
1084 context_p
[i
] = &context
[i
];
1085 /* save core registers (r0 - r15 of current core mode) */
1086 arm7_9
->read_core_regs(target
, 0xffff, context_p
);
1088 arm7_9
->read_xpsr(target
, &cpsr
, 0);
1090 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1093 /* if the core has been executing in Thumb state, set the T bit */
1094 if (armv4_5
->core_state
== ARMV4_5_STATE_THUMB
)
1097 buf_set_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32, cpsr
);
1098 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].dirty
= 0;
1099 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].valid
= 1;
1101 armv4_5
->core_mode
= cpsr
& 0x1f;
1103 if (armv4_5_mode_to_number(armv4_5
->core_mode
) == -1)
1105 target
->state
= TARGET_UNKNOWN
;
1106 ERROR("cpsr contains invalid mode value - communication failure");
1107 return ERROR_TARGET_FAILURE
;
1110 DEBUG("target entered debug state in %s mode", armv4_5_mode_strings
[armv4_5_mode_to_number(armv4_5
->core_mode
)]);
1112 if (armv4_5
->core_state
== ARMV4_5_STATE_THUMB
)
1114 DEBUG("thumb state, applying fixups");
1115 context
[0] = r0_thumb
;
1116 context
[15] = pc_thumb
;
1117 } else if (armv4_5
->core_state
== ARMV4_5_STATE_ARM
)
1119 /* adjust value stored by STM */
1120 context
[15] -= 3 * 4;
1123 if ((target
->debug_reason
== DBG_REASON_BREAKPOINT
)
1124 || (target
->debug_reason
== DBG_REASON_SINGLESTEP
)
1125 || (target
->debug_reason
== DBG_REASON_WATCHPOINT
)
1126 || (target
->debug_reason
== DBG_REASON_WPTANDBKPT
)
1127 || ((target
->debug_reason
== DBG_REASON_DBGRQ
) && (arm7_9
->use_dbgrq
== 0)))
1128 context
[15] -= 3 * ((armv4_5
->core_state
== ARMV4_5_STATE_ARM
) ? 4 : 2);
1129 else if (target
->debug_reason
== DBG_REASON_DBGRQ
)
1130 context
[15] -= arm7_9
->dbgreq_adjust_pc
* ((armv4_5
->core_state
== ARMV4_5_STATE_ARM
) ? 4 : 2);
1133 ERROR("unknown debug reason: %i", target
->debug_reason
);
1137 for (i
=0; i
<=15; i
++)
1139 DEBUG("r%i: 0x%8.8x", i
, context
[i
]);
1140 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).value
, 0, 32, context
[i
]);
1141 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).dirty
= 0;
1142 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).valid
= 1;
1145 DEBUG("entered debug state at PC 0x%x", context
[15]);
1147 /* exceptions other than USR & SYS have a saved program status register */
1148 if ((armv4_5_mode_to_number(armv4_5
->core_mode
) != ARMV4_5_MODE_USR
) && (armv4_5_mode_to_number(armv4_5
->core_mode
) != ARMV4_5_MODE_SYS
))
1151 arm7_9
->read_xpsr(target
, &spsr
, 1);
1152 jtag_execute_queue();
1153 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 16).value
, 0, 32, spsr
);
1154 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 16).dirty
= 0;
1155 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 16).valid
= 1;
1158 /* r0 and r15 (pc) have to be restored later */
1159 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 0).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 0).valid
;
1160 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 15).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 15).valid
;
1162 if ((retval
= jtag
->execute_queue()) != ERROR_OK
)
1165 if (arm7_9
->post_debug_entry
)
1166 arm7_9
->post_debug_entry(target
);
1171 int arm7_9_full_context(target_t
*target
)
1175 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1176 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
1180 if (target
->state
!= TARGET_HALTED
)
1182 WARNING("target not halted");
1183 return ERROR_TARGET_NOT_HALTED
;
1186 /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
1187 * SYS shares registers with User, so we don't touch SYS
1189 for(i
= 0; i
< 6; i
++)
1196 /* check if there are invalid registers in the current mode
1198 for (j
= 0; j
<= 16; j
++)
1200 if (ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).valid
== 0)
1208 /* change processor mode (and mask T bit) */
1209 tmp_cpsr
= buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8) & 0xE0;
1210 tmp_cpsr
|= armv4_5_number_to_mode(i
);
1212 arm7_9
->write_xpsr_im8(target
, tmp_cpsr
& 0xff, 0, 0);
1214 for (j
= 0; j
< 15; j
++)
1216 if (ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).valid
== 0)
1218 reg_p
[j
] = (u32
*)ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).value
;
1220 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).valid
= 1;
1221 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).dirty
= 0;
1225 /* if only the PSR is invalid, mask is all zeroes */
1227 arm7_9
->read_core_regs(target
, mask
, reg_p
);
1229 /* check if the PSR has to be read */
1230 if (ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), 16).valid
== 0)
1232 arm7_9
->read_xpsr(target
, (u32
*)ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), 16).value
, 1);
1233 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), 16).valid
= 1;
1234 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), 16).dirty
= 0;
1239 /* restore processor mode (mask T bit) */
1240 arm7_9
->write_xpsr_im8(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8) & ~0x20, 0, 0);
1242 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1244 ERROR("JTAG failure");
1250 int arm7_9_restore_context(target_t
*target
)
1252 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1253 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
1255 armv4_5_core_reg_t
*reg_arch_info
;
1256 enum armv4_5_mode current_mode
= armv4_5
->core_mode
;
1263 if (target
->state
!= TARGET_HALTED
)
1265 WARNING("target not halted");
1266 return ERROR_TARGET_NOT_HALTED
;
1269 if (arm7_9
->pre_restore_context
)
1270 arm7_9
->pre_restore_context(target
);
1272 /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
1273 * SYS shares registers with User, so we don't touch SYS
1275 for (i
= 0; i
< 6; i
++)
1277 DEBUG("examining %s mode", armv4_5_mode_strings
[i
]);
1280 /* check if there are dirty registers in the current mode
1282 for (j
= 0; j
<= 16; j
++)
1284 reg
= &ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
);
1285 reg_arch_info
= reg
->arch_info
;
1286 if (reg
->dirty
== 1)
1288 if (reg
->valid
== 1)
1291 DEBUG("examining dirty reg: %s", reg
->name
);
1292 if ((reg_arch_info
->mode
!= ARMV4_5_MODE_ANY
)
1293 && (reg_arch_info
->mode
!= current_mode
)
1294 && !((reg_arch_info
->mode
== ARMV4_5_MODE_USR
) && (armv4_5
->core_mode
== ARMV4_5_MODE_SYS
))
1295 && !((reg_arch_info
->mode
== ARMV4_5_MODE_SYS
) && (armv4_5
->core_mode
== ARMV4_5_MODE_USR
)))
1298 DEBUG("require mode change");
1303 ERROR("BUG: dirty register '%s', but no valid data", reg
->name
);
1318 /* change processor mode (mask T bit) */
1319 tmp_cpsr
= buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8) & 0xE0;
1320 tmp_cpsr
|= armv4_5_number_to_mode(i
);
1322 arm7_9
->write_xpsr_im8(target
, tmp_cpsr
& 0xff, 0, 0);
1323 current_mode
= armv4_5_number_to_mode(i
);
1326 for (j
= 0; j
<= 14; j
++)
1328 reg
= &ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
);
1329 reg_arch_info
= reg
->arch_info
;
1332 if (reg
->dirty
== 1)
1334 regs
[j
] = buf_get_u32(reg
->value
, 0, 32);
1339 DEBUG("writing register %i of mode %s with value 0x%8.8x", j
, armv4_5_mode_strings
[i
], regs
[j
]);
1345 arm7_9
->write_core_regs(target
, mask
, regs
);
1348 reg
= &ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), 16);
1349 reg_arch_info
= reg
->arch_info
;
1350 if ((reg
->dirty
) && (reg_arch_info
->mode
!= ARMV4_5_MODE_ANY
))
1352 DEBUG("writing SPSR of mode %i with value 0x%8.8x", i
, buf_get_u32(reg
->value
, 0, 32));
1353 arm7_9
->write_xpsr(target
, buf_get_u32(reg
->value
, 0, 32), 1);
1358 if ((armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].dirty
== 0) && (armv4_5
->core_mode
!= current_mode
))
1360 /* restore processor mode (mask T bit) */
1363 tmp_cpsr
= buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8) & 0xE0;
1364 tmp_cpsr
|= armv4_5_number_to_mode(i
);
1366 DEBUG("writing lower 8 bit of cpsr with value 0x%2.2x", tmp_cpsr
);
1367 arm7_9
->write_xpsr_im8(target
, tmp_cpsr
& 0xff, 0, 0);
1369 else if (armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].dirty
== 1)
1371 /* CPSR has been changed, full restore necessary (mask T bit) */
1372 DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32));
1373 arm7_9
->write_xpsr(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32) & ~0x20, 0);
1374 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].dirty
= 0;
1375 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].valid
= 1;
1379 DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32));
1380 arm7_9
->write_pc(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32));
1381 armv4_5
->core_cache
->reg_list
[15].dirty
= 0;
1383 if (arm7_9
->post_restore_context
)
1384 arm7_9
->post_restore_context(target
);
1389 int arm7_9_restart_core(struct target_s
*target
)
1391 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1392 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
1393 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
1395 /* set RESTART instruction */
1396 jtag_add_end_state(TAP_RTI
);
1397 arm_jtag_set_instr(jtag_info
, 0x4, NULL
);
1399 jtag_add_runtest(1, TAP_RTI
);
1400 if ((jtag_execute_queue()) != ERROR_OK
)
1408 void arm7_9_enable_watchpoints(struct target_s
*target
)
1410 watchpoint_t
*watchpoint
= target
->watchpoints
;
1414 if (watchpoint
->set
== 0)
1415 arm7_9_set_watchpoint(target
, watchpoint
);
1416 watchpoint
= watchpoint
->next
;
1420 void arm7_9_enable_breakpoints(struct target_s
*target
)
1422 breakpoint_t
*breakpoint
= target
->breakpoints
;
1424 /* set any pending breakpoints */
1427 if (breakpoint
->set
== 0)
1428 arm7_9_set_breakpoint(target
, breakpoint
);
1429 breakpoint
= breakpoint
->next
;
1433 void arm7_9_disable_bkpts_and_wpts(struct target_s
*target
)
1435 breakpoint_t
*breakpoint
= target
->breakpoints
;
1436 watchpoint_t
*watchpoint
= target
->watchpoints
;
1438 /* set any pending breakpoints */
1441 if (breakpoint
->set
!= 0)
1442 arm7_9_unset_breakpoint(target
, breakpoint
);
1443 breakpoint
= breakpoint
->next
;
1448 if (watchpoint
->set
!= 0)
1449 arm7_9_unset_watchpoint(target
, watchpoint
);
1450 watchpoint
= watchpoint
->next
;
1454 int arm7_9_resume(struct target_s
*target
, int current
, u32 address
, int handle_breakpoints
, int debug_execution
)
1456 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1457 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
1458 breakpoint_t
*breakpoint
= target
->breakpoints
;
1459 reg_t
*dbg_ctrl
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_CTRL
];
1464 if (target
->state
!= TARGET_HALTED
)
1466 WARNING("target not halted");
1467 return ERROR_TARGET_NOT_HALTED
;
1470 if (!debug_execution
)
1472 target_free_all_working_areas(target
);
1475 /* current = 1: continue on current pc, otherwise continue at <address> */
1477 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, address
);
1479 /* the front-end may request us not to handle breakpoints */
1480 if (handle_breakpoints
)
1482 if ((breakpoint
= breakpoint_find(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32))))
1484 DEBUG("unset breakpoint at 0x%8.8x", breakpoint
->address
);
1485 arm7_9_unset_breakpoint(target
, breakpoint
);
1487 DEBUG("enable single-step");
1488 arm7_9
->enable_single_step(target
);
1490 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
1492 arm7_9_restore_context(target
);
1494 if (armv4_5
->core_state
== ARMV4_5_STATE_ARM
)
1495 arm7_9
->branch_resume(target
);
1496 else if (armv4_5
->core_state
== ARMV4_5_STATE_THUMB
)
1498 arm7_9
->branch_resume_thumb(target
);
1502 ERROR("unhandled core state");
1506 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_DBGACK
, 1, 0);
1507 embeddedice_write_reg(dbg_ctrl
, buf_get_u32(dbg_ctrl
->value
, 0, dbg_ctrl
->size
));
1508 err
= arm7_9_execute_sys_speed(target
);
1510 DEBUG("disable single-step");
1511 arm7_9
->disable_single_step(target
);
1513 if (err
!= ERROR_OK
)
1515 arm7_9_set_breakpoint(target
, breakpoint
);
1516 target
->state
= TARGET_UNKNOWN
;
1520 arm7_9_debug_entry(target
);
1521 DEBUG("new PC after step: 0x%8.8x", buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32));
1523 DEBUG("set breakpoint at 0x%8.8x", breakpoint
->address
);
1524 arm7_9_set_breakpoint(target
, breakpoint
);
1528 /* enable any pending breakpoints and watchpoints */
1529 arm7_9_enable_breakpoints(target
);
1530 arm7_9_enable_watchpoints(target
);
1532 arm7_9_restore_context(target
);
1534 if (armv4_5
->core_state
== ARMV4_5_STATE_ARM
)
1536 arm7_9
->branch_resume(target
);
1538 else if (armv4_5
->core_state
== ARMV4_5_STATE_THUMB
)
1540 arm7_9
->branch_resume_thumb(target
);
1544 ERROR("unhandled core state");
1548 /* deassert DBGACK and INTDIS */
1549 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_DBGACK
, 1, 0);
1550 /* INTDIS only when we really resume, not during debug execution */
1551 if (!debug_execution
)
1552 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_INTDIS
, 1, 0);
1553 embeddedice_write_reg(dbg_ctrl
, buf_get_u32(dbg_ctrl
->value
, 0, dbg_ctrl
->size
));
1555 arm7_9_restart_core(target
);
1557 target
->debug_reason
= DBG_REASON_NOTHALTED
;
1559 if (!debug_execution
)
1561 /* registers are now invalid */
1562 armv4_5_invalidate_core_regs(target
);
1563 target
->state
= TARGET_RUNNING
;
1564 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
1568 target
->state
= TARGET_DEBUG_RUNNING
;
1569 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_RESUMED
);
1572 DEBUG("target resumed");
1577 void arm7_9_enable_eice_step(target_t
*target
)
1579 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1580 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
1582 /* setup an inverse breakpoint on the current PC
1583 * - comparator 1 matches the current address
1584 * - rangeout from comparator 1 is connected to comparator 0 rangein
1585 * - comparator 0 matches any address, as long as rangein is low */
1586 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_MASK
], 0xffffffff);
1587 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_DATA_MASK
], 0xffffffff);
1588 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
], 0x100);
1589 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_MASK
], 0x77);
1590 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_ADDR_VALUE
], buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32));
1591 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_ADDR_MASK
], 0);
1592 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_DATA_MASK
], 0xffffffff);
1593 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_VALUE
], 0x0);
1594 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_MASK
], 0xf7);
1597 void arm7_9_disable_eice_step(target_t
*target
)
1599 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1600 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
1602 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_MASK
]);
1603 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_DATA_MASK
]);
1604 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
]);
1605 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_MASK
]);
1606 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_ADDR_VALUE
]);
1607 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_ADDR_MASK
]);
1608 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_DATA_MASK
]);
1609 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_MASK
]);
1610 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_VALUE
]);
1613 int arm7_9_step(struct target_s
*target
, int current
, u32 address
, int handle_breakpoints
)
1615 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1616 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
1617 breakpoint_t
*breakpoint
= NULL
;
1620 if (target
->state
!= TARGET_HALTED
)
1622 WARNING("target not halted");
1623 return ERROR_TARGET_NOT_HALTED
;
1626 /* current = 1: continue on current pc, otherwise continue at <address> */
1628 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, address
);
1630 /* the front-end may request us not to handle breakpoints */
1631 if (handle_breakpoints
)
1632 if ((breakpoint
= breakpoint_find(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32))))
1633 arm7_9_unset_breakpoint(target
, breakpoint
);
1635 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
1637 arm7_9_restore_context(target
);
1639 arm7_9
->enable_single_step(target
);
1641 if (armv4_5
->core_state
== ARMV4_5_STATE_ARM
)
1643 arm7_9
->branch_resume(target
);
1645 else if (armv4_5
->core_state
== ARMV4_5_STATE_THUMB
)
1647 arm7_9
->branch_resume_thumb(target
);
1651 ERROR("unhandled core state");
1655 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
1657 err
= arm7_9_execute_sys_speed(target
);
1658 arm7_9
->disable_single_step(target
);
1660 /* registers are now invalid */
1661 armv4_5_invalidate_core_regs(target
);
1663 if (err
!= ERROR_OK
)
1665 target
->state
= TARGET_UNKNOWN
;
1667 arm7_9_debug_entry(target
);
1668 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
1669 DEBUG("target stepped");
1673 arm7_9_set_breakpoint(target
, breakpoint
);
1679 int arm7_9_read_core_reg(struct target_s
*target
, int num
, enum armv4_5_mode mode
)
1684 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1685 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
1686 enum armv4_5_mode reg_mode
= ((armv4_5_core_reg_t
*)ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, mode
, num
).arch_info
)->mode
;
1688 if ((num
< 0) || (num
> 16))
1689 return ERROR_INVALID_ARGUMENTS
;
1691 if ((mode
!= ARMV4_5_MODE_ANY
)
1692 && (mode
!= armv4_5
->core_mode
)
1693 && (reg_mode
!= ARMV4_5_MODE_ANY
))
1697 /* change processor mode (mask T bit) */
1698 tmp_cpsr
= buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8) & 0xE0;
1701 arm7_9
->write_xpsr_im8(target
, tmp_cpsr
& 0xff, 0, 0);
1704 if ((num
>= 0) && (num
<= 15))
1706 /* read a normal core register */
1707 reg_p
[num
] = &value
;
1709 arm7_9
->read_core_regs(target
, 1 << num
, reg_p
);
1713 /* read a program status register
1714 * if the register mode is MODE_ANY, we read the cpsr, otherwise a spsr
1716 armv4_5_core_reg_t
*arch_info
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, mode
, num
).arch_info
;
1717 int spsr
= (arch_info
->mode
== ARMV4_5_MODE_ANY
) ? 0 : 1;
1719 arm7_9
->read_xpsr(target
, &value
, spsr
);
1722 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1724 ERROR("JTAG failure");
1728 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, mode
, num
).valid
= 1;
1729 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, mode
, num
).dirty
= 0;
1730 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, mode
, num
).value
, 0, 32, value
);
1732 if ((mode
!= ARMV4_5_MODE_ANY
)
1733 && (mode
!= armv4_5
->core_mode
)
1734 && (reg_mode
!= ARMV4_5_MODE_ANY
)) {
1735 /* restore processor mode (mask T bit) */
1736 arm7_9
->write_xpsr_im8(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8) & ~0x20, 0, 0);
1743 int arm7_9_write_core_reg(struct target_s
*target
, int num
, enum armv4_5_mode mode
, u32 value
)
1747 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1748 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
1749 enum armv4_5_mode reg_mode
= ((armv4_5_core_reg_t
*)ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, mode
, num
).arch_info
)->mode
;
1751 if ((num
< 0) || (num
> 16))
1752 return ERROR_INVALID_ARGUMENTS
;
1754 if ((mode
!= ARMV4_5_MODE_ANY
)
1755 && (mode
!= armv4_5
->core_mode
)
1756 && (reg_mode
!= ARMV4_5_MODE_ANY
)) {
1759 /* change processor mode (mask T bit) */
1760 tmp_cpsr
= buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8) & 0xE0;
1763 arm7_9
->write_xpsr_im8(target
, tmp_cpsr
& 0xff, 0, 0);
1766 if ((num
>= 0) && (num
<= 15))
1768 /* write a normal core register */
1771 arm7_9
->write_core_regs(target
, 1 << num
, reg
);
1775 /* write a program status register
1776 * if the register mode is MODE_ANY, we write the cpsr, otherwise a spsr
1778 armv4_5_core_reg_t
*arch_info
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, mode
, num
).arch_info
;
1779 int spsr
= (arch_info
->mode
== ARMV4_5_MODE_ANY
) ? 0 : 1;
1781 /* if we're writing the CPSR, mask the T bit */
1785 arm7_9
->write_xpsr(target
, value
, spsr
);
1788 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, mode
, num
).valid
= 1;
1789 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, mode
, num
).dirty
= 0;
1791 if ((mode
!= ARMV4_5_MODE_ANY
)
1792 && (mode
!= armv4_5
->core_mode
)
1793 && (reg_mode
!= ARMV4_5_MODE_ANY
)) {
1794 /* restore processor mode (mask T bit) */
1795 arm7_9
->write_xpsr_im8(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8) & ~0x20, 0, 0);
1798 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1800 ERROR("JTAG failure");
1808 int arm7_9_read_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
)
1810 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1811 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
1814 int num_accesses
= 0;
1815 int thisrun_accesses
;
1821 DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address
, size
, count
);
1823 if (target
->state
!= TARGET_HALTED
)
1825 WARNING("target not halted");
1826 return ERROR_TARGET_NOT_HALTED
;
1829 /* sanitize arguments */
1830 if (((size
!= 4) && (size
!= 2) && (size
!= 1)) || (count
== 0) || !(buffer
))
1831 return ERROR_INVALID_ARGUMENTS
;
1833 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
1834 return ERROR_TARGET_UNALIGNED_ACCESS
;
1836 /* load the base register with the address of the first word */
1838 arm7_9
->write_core_regs(target
, 0x1, reg
);
1843 while (num_accesses
< count
)
1846 thisrun_accesses
= ((count
- num_accesses
) >= 14) ? 14 : (count
- num_accesses
);
1847 reg_list
= (0xffff >> (15 - thisrun_accesses
)) & 0xfffe;
1849 if (last_reg
<= thisrun_accesses
)
1850 last_reg
= thisrun_accesses
;
1852 arm7_9
->load_word_regs(target
, reg_list
);
1854 /* fast memory reads are only safe when the target is running
1855 * from a sufficiently high clock (32 kHz is usually too slow)
1857 if (arm7_9
->fast_memory_access
)
1858 arm7_9_execute_fast_sys_speed(target
);
1860 arm7_9_execute_sys_speed(target
);
1862 arm7_9
->read_core_regs_target_buffer(target
, reg_list
, buffer
, 4);
1864 /* advance buffer, count number of accesses */
1865 buffer
+= thisrun_accesses
* 4;
1866 num_accesses
+= thisrun_accesses
;
1870 while (num_accesses
< count
)
1873 thisrun_accesses
= ((count
- num_accesses
) >= 14) ? 14 : (count
- num_accesses
);
1874 reg_list
= (0xffff >> (15 - thisrun_accesses
)) & 0xfffe;
1876 for (i
= 1; i
<= thisrun_accesses
; i
++)
1880 arm7_9
->load_hword_reg(target
, i
);
1881 /* fast memory reads are only safe when the target is running
1882 * from a sufficiently high clock (32 kHz is usually too slow)
1884 if (arm7_9
->fast_memory_access
)
1885 arm7_9_execute_fast_sys_speed(target
);
1887 arm7_9_execute_sys_speed(target
);
1890 arm7_9
->read_core_regs_target_buffer(target
, reg_list
, buffer
, 2);
1892 /* advance buffer, count number of accesses */
1893 buffer
+= thisrun_accesses
* 2;
1894 num_accesses
+= thisrun_accesses
;
1898 while (num_accesses
< count
)
1901 thisrun_accesses
= ((count
- num_accesses
) >= 14) ? 14 : (count
- num_accesses
);
1902 reg_list
= (0xffff >> (15 - thisrun_accesses
)) & 0xfffe;
1904 for (i
= 1; i
<= thisrun_accesses
; i
++)
1908 arm7_9
->load_byte_reg(target
, i
);
1909 /* fast memory reads are only safe when the target is running
1910 * from a sufficiently high clock (32 kHz is usually too slow)
1912 if (arm7_9
->fast_memory_access
)
1913 arm7_9_execute_fast_sys_speed(target
);
1915 arm7_9_execute_sys_speed(target
);
1918 arm7_9
->read_core_regs_target_buffer(target
, reg_list
, buffer
, 1);
1920 /* advance buffer, count number of accesses */
1921 buffer
+= thisrun_accesses
* 1;
1922 num_accesses
+= thisrun_accesses
;
1926 ERROR("BUG: we shouldn't get here");
1931 for (i
=0; i
<=last_reg
; i
++)
1932 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).valid
;
1934 arm7_9
->read_xpsr(target
, &cpsr
, 0);
1935 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1937 ERROR("JTAG error while reading cpsr");
1938 return ERROR_TARGET_DATA_ABORT
;
1941 if (((cpsr
& 0x1f) == ARMV4_5_MODE_ABT
) && (armv4_5
->core_mode
!= ARMV4_5_MODE_ABT
))
1943 WARNING("memory read caused data abort (address: 0x%8.8x, size: 0x%x, count: 0x%x)", address
, size
, count
);
1945 arm7_9
->write_xpsr_im8(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8) & ~0x20, 0, 0);
1947 return ERROR_TARGET_DATA_ABORT
;
1953 int arm7_9_write_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
)
1955 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1956 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
1957 reg_t
*dbg_ctrl
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_CTRL
];
1960 int num_accesses
= 0;
1961 int thisrun_accesses
;
1967 #ifdef _DEBUG_ARM7_9_
1968 DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address
, size
, count
);
1971 if (target
->state
!= TARGET_HALTED
)
1973 WARNING("target not halted");
1974 return ERROR_TARGET_NOT_HALTED
;
1977 /* sanitize arguments */
1978 if (((size
!= 4) && (size
!= 2) && (size
!= 1)) || (count
== 0) || !(buffer
))
1979 return ERROR_INVALID_ARGUMENTS
;
1981 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
1982 return ERROR_TARGET_UNALIGNED_ACCESS
;
1984 /* load the base register with the address of the first word */
1986 arm7_9
->write_core_regs(target
, 0x1, reg
);
1988 /* Clear DBGACK, to make sure memory fetches work as expected */
1989 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_DBGACK
, 1, 0);
1990 embeddedice_store_reg(dbg_ctrl
);
1995 while (num_accesses
< count
)
1998 thisrun_accesses
= ((count
- num_accesses
) >= 14) ? 14 : (count
- num_accesses
);
1999 reg_list
= (0xffff >> (15 - thisrun_accesses
)) & 0xfffe;
2001 for (i
= 1; i
<= thisrun_accesses
; i
++)
2005 reg
[i
] = target_buffer_get_u32(target
, buffer
);
2009 arm7_9
->write_core_regs(target
, reg_list
, reg
);
2011 arm7_9
->store_word_regs(target
, reg_list
);
2013 /* fast memory writes are only safe when the target is running
2014 * from a sufficiently high clock (32 kHz is usually too slow)
2016 if (arm7_9
->fast_memory_access
)
2017 arm7_9_execute_fast_sys_speed(target
);
2019 arm7_9_execute_sys_speed(target
);
2021 num_accesses
+= thisrun_accesses
;
2025 while (num_accesses
< count
)
2028 thisrun_accesses
= ((count
- num_accesses
) >= 14) ? 14 : (count
- num_accesses
);
2029 reg_list
= (0xffff >> (15 - thisrun_accesses
)) & 0xfffe;
2031 for (i
= 1; i
<= thisrun_accesses
; i
++)
2035 reg
[i
] = target_buffer_get_u16(target
, buffer
) & 0xffff;
2039 arm7_9
->write_core_regs(target
, reg_list
, reg
);
2041 for (i
= 1; i
<= thisrun_accesses
; i
++)
2043 arm7_9
->store_hword_reg(target
, i
);
2045 /* fast memory writes are only safe when the target is running
2046 * from a sufficiently high clock (32 kHz is usually too slow)
2048 if (arm7_9
->fast_memory_access
)
2049 arm7_9_execute_fast_sys_speed(target
);
2051 arm7_9_execute_sys_speed(target
);
2054 num_accesses
+= thisrun_accesses
;
2058 while (num_accesses
< count
)
2061 thisrun_accesses
= ((count
- num_accesses
) >= 14) ? 14 : (count
- num_accesses
);
2062 reg_list
= (0xffff >> (15 - thisrun_accesses
)) & 0xfffe;
2064 for (i
= 1; i
<= thisrun_accesses
; i
++)
2068 reg
[i
] = *buffer
++ & 0xff;
2071 arm7_9
->write_core_regs(target
, reg_list
, reg
);
2073 for (i
= 1; i
<= thisrun_accesses
; i
++)
2075 arm7_9
->store_byte_reg(target
, i
);
2076 /* fast memory writes are only safe when the target is running
2077 * from a sufficiently high clock (32 kHz is usually too slow)
2079 if (arm7_9
->fast_memory_access
)
2080 arm7_9_execute_fast_sys_speed(target
);
2082 arm7_9_execute_sys_speed(target
);
2085 num_accesses
+= thisrun_accesses
;
2089 ERROR("BUG: we shouldn't get here");
2095 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_DBGACK
, 1, 1);
2096 embeddedice_store_reg(dbg_ctrl
);
2098 for (i
=0; i
<=last_reg
; i
++)
2099 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).valid
;
2101 arm7_9
->read_xpsr(target
, &cpsr
, 0);
2102 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
2104 ERROR("JTAG error while reading cpsr");
2105 return ERROR_TARGET_DATA_ABORT
;
2108 if (((cpsr
& 0x1f) == ARMV4_5_MODE_ABT
) && (armv4_5
->core_mode
!= ARMV4_5_MODE_ABT
))
2110 WARNING("memory write caused data abort (address: 0x%8.8x, size: 0x%x, count: 0x%x)", address
, size
, count
);
2112 arm7_9
->write_xpsr_im8(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8) & ~0x20, 0, 0);
2114 return ERROR_TARGET_DATA_ABORT
;
2120 int arm7_9_bulk_write_memory(target_t
*target
, u32 address
, u32 count
, u8
*buffer
)
2122 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2123 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
2124 enum armv4_5_state core_state
= armv4_5
->core_state
;
2125 u32 r0
= buf_get_u32(armv4_5
->core_cache
->reg_list
[0].value
, 0, 32);
2126 u32 r1
= buf_get_u32(armv4_5
->core_cache
->reg_list
[1].value
, 0, 32);
2127 u32 pc
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
2132 /* MRC TST BNE MRC STR B */
2133 0xee101e10, 0xe3110001, 0x0afffffc, 0xee111e10, 0xe4801004, 0xeafffff9
2136 if (!arm7_9
->dcc_downloads
)
2137 return target
->type
->write_memory(target
, address
, 4, count
, buffer
);
2139 /* regrab previously allocated working_area, or allocate a new one */
2140 if (!arm7_9
->dcc_working_area
)
2142 u8 dcc_code_buf
[6 * 4];
2144 /* make sure we have a working area */
2145 if (target_alloc_working_area(target
, 24, &arm7_9
->dcc_working_area
) != ERROR_OK
)
2147 INFO("no working area available, falling back to memory writes");
2148 return target
->type
->write_memory(target
, address
, 4, count
, buffer
);
2151 /* copy target instructions to target endianness */
2152 for (i
= 0; i
< 6; i
++)
2154 target_buffer_set_u32(target
, dcc_code_buf
+ i
*4, dcc_code
[i
]);
2157 /* write DCC code to working area */
2158 target
->type
->write_memory(target
, arm7_9
->dcc_working_area
->address
, 4, 6, dcc_code_buf
);
2161 buf_set_u32(armv4_5
->core_cache
->reg_list
[0].value
, 0, 32, address
);
2162 armv4_5
->core_cache
->reg_list
[0].valid
= 1;
2163 armv4_5
->core_cache
->reg_list
[0].dirty
= 1;
2164 armv4_5
->core_state
= ARMV4_5_STATE_ARM
;
2166 arm7_9_resume(target
, 0, arm7_9
->dcc_working_area
->address
, 1, 1);
2168 for (i
= 0; i
< count
; i
++)
2170 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_COMMS_DATA
], target_buffer_get_u32(target
, buffer
));
2174 target
->type
->halt(target
);
2176 while (target
->state
!= TARGET_HALTED
)
2177 target
->type
->poll(target
);
2179 /* restore target state */
2180 buf_set_u32(armv4_5
->core_cache
->reg_list
[0].value
, 0, 32, r0
);
2181 armv4_5
->core_cache
->reg_list
[0].valid
= 1;
2182 armv4_5
->core_cache
->reg_list
[0].dirty
= 1;
2183 buf_set_u32(armv4_5
->core_cache
->reg_list
[1].value
, 0, 32, r1
);
2184 armv4_5
->core_cache
->reg_list
[1].valid
= 1;
2185 armv4_5
->core_cache
->reg_list
[1].dirty
= 1;
2186 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, pc
);
2187 armv4_5
->core_cache
->reg_list
[15].valid
= 1;
2188 armv4_5
->core_cache
->reg_list
[15].dirty
= 1;
2189 armv4_5
->core_state
= core_state
;
2194 int arm7_9_checksum_memory(struct target_s
*target
, u32 address
, u32 count
, u32
* checksum
)
2196 working_area_t
*crc_algorithm
;
2197 armv4_5_algorithm_t armv4_5_info
;
2198 reg_param_t reg_params
[2];
2201 u32 arm7_9_crc_code
[] = {
2202 0xE1A02000, /* mov r2, r0 */
2203 0xE3E00000, /* mov r0, #0xffffffff */
2204 0xE1A03001, /* mov r3, r1 */
2205 0xE3A04000, /* mov r4, #0 */
2206 0xEA00000B, /* b ncomp */
2208 0xE7D21004, /* ldrb r1, [r2, r4] */
2209 0xE59F7030, /* ldr r7, CRC32XOR */
2210 0xE0200C01, /* eor r0, r0, r1, asl 24 */
2211 0xE3A05000, /* mov r5, #0 */
2213 0xE3500000, /* cmp r0, #0 */
2214 0xE1A06080, /* mov r6, r0, asl #1 */
2215 0xE2855001, /* add r5, r5, #1 */
2216 0xE1A00006, /* mov r0, r6 */
2217 0xB0260007, /* eorlt r0, r6, r7 */
2218 0xE3550008, /* cmp r5, #8 */
2219 0x1AFFFFF8, /* bne loop */
2220 0xE2844001, /* add r4, r4, #1 */
2222 0xE1540003, /* cmp r4, r3 */
2223 0x1AFFFFF1, /* bne nbyte */
2225 0xEAFFFFFE, /* b end */
2226 0x04C11DB7 /* CRC32XOR: .word 0x04C11DB7 */
2231 if (target_alloc_working_area(target
, sizeof(arm7_9_crc_code
), &crc_algorithm
) != ERROR_OK
)
2233 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
2236 /* convert flash writing code into a buffer in target endianness */
2237 for (i
= 0; i
< (sizeof(arm7_9_crc_code
)/sizeof(u32
)); i
++)
2238 target_write_u32(target
, crc_algorithm
->address
+ i
*sizeof(u32
), arm7_9_crc_code
[i
]);
2240 armv4_5_info
.common_magic
= ARMV4_5_COMMON_MAGIC
;
2241 armv4_5_info
.core_mode
= ARMV4_5_MODE_SVC
;
2242 armv4_5_info
.core_state
= ARMV4_5_STATE_ARM
;
2244 init_reg_param(®_params
[0], "r0", 32, PARAM_IN_OUT
);
2245 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
);
2247 buf_set_u32(reg_params
[0].value
, 0, 32, address
);
2248 buf_set_u32(reg_params
[1].value
, 0, 32, count
);
2250 if ((retval
= target
->type
->run_algorithm(target
, 0, NULL
, 2, reg_params
,
2251 crc_algorithm
->address
, crc_algorithm
->address
+ (sizeof(arm7_9_crc_code
) - 8), 20000, &armv4_5_info
)) != ERROR_OK
)
2253 ERROR("error executing arm7_9 crc algorithm");
2254 destroy_reg_param(®_params
[0]);
2255 destroy_reg_param(®_params
[1]);
2256 target_free_working_area(target
, crc_algorithm
);
2260 *checksum
= buf_get_u32(reg_params
[0].value
, 0, 32);
2262 destroy_reg_param(®_params
[0]);
2263 destroy_reg_param(®_params
[1]);
2265 target_free_working_area(target
, crc_algorithm
);
2270 int arm7_9_register_commands(struct command_context_s
*cmd_ctx
)
2272 command_t
*arm7_9_cmd
;
2274 arm7_9_cmd
= register_command(cmd_ctx
, NULL
, "arm7_9", NULL
, COMMAND_ANY
, "arm7/9 specific commands");
2276 register_command(cmd_ctx
, arm7_9_cmd
, "write_xpsr", handle_arm7_9_write_xpsr_command
, COMMAND_EXEC
, "write program status register <value> <not cpsr|spsr>");
2277 register_command(cmd_ctx
, arm7_9_cmd
, "write_xpsr_im8", handle_arm7_9_write_xpsr_im8_command
, COMMAND_EXEC
, "write program status register <8bit immediate> <rotate> <not cpsr|spsr>");
2279 register_command(cmd_ctx
, arm7_9_cmd
, "write_core_reg", handle_arm7_9_write_core_reg_command
, COMMAND_EXEC
, "write core register <num> <mode> <value>");
2281 register_command(cmd_ctx
, arm7_9_cmd
, "sw_bkpts", handle_arm7_9_sw_bkpts_command
, COMMAND_EXEC
, "support for software breakpoints <enable|disable>");
2282 register_command(cmd_ctx
, arm7_9_cmd
, "force_hw_bkpts", handle_arm7_9_force_hw_bkpts_command
, COMMAND_EXEC
, "use hardware breakpoints for all breakpoints (disables sw breakpoint support) <enable|disable>");
2283 register_command(cmd_ctx
, arm7_9_cmd
, "dbgrq", handle_arm7_9_dbgrq_command
,
2284 COMMAND_ANY
, "use EmbeddedICE dbgrq instead of breakpoint for target halt requests <enable|disable>");
2285 register_command(cmd_ctx
, arm7_9_cmd
, "fast_writes", handle_arm7_9_fast_memory_access_command
,
2286 COMMAND_ANY
, "(deprecated, see: arm7_9 fast_memory_access)");
2287 register_command(cmd_ctx
, arm7_9_cmd
, "fast_memory_access", handle_arm7_9_fast_memory_access_command
,
2288 COMMAND_ANY
, "use fast memory accesses instead of slower but potentially unsafe slow accesses <enable|disable>");
2289 register_command(cmd_ctx
, arm7_9_cmd
, "dcc_downloads", handle_arm7_9_dcc_downloads_command
,
2290 COMMAND_ANY
, "use DCC downloads for larger memory writes <enable|disable>");
2292 armv4_5_register_commands(cmd_ctx
);
2294 etm_register_commands(cmd_ctx
);
2299 int handle_arm7_9_write_xpsr_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
2304 target_t
*target
= get_current_target(cmd_ctx
);
2305 armv4_5_common_t
*armv4_5
;
2306 arm7_9_common_t
*arm7_9
;
2308 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
2310 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
2314 if (target
->state
!= TARGET_HALTED
)
2316 command_print(cmd_ctx
, "can't write registers while running");
2322 command_print(cmd_ctx
, "usage: write_xpsr <value> <not cpsr|spsr>");
2326 value
= strtoul(args
[0], NULL
, 0);
2327 spsr
= strtol(args
[1], NULL
, 0);
2329 /* if we're writing the CPSR, mask the T bit */
2333 arm7_9
->write_xpsr(target
, value
, spsr
);
2334 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
2336 ERROR("JTAG error while writing to xpsr");
2343 int handle_arm7_9_write_xpsr_im8_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
2349 target_t
*target
= get_current_target(cmd_ctx
);
2350 armv4_5_common_t
*armv4_5
;
2351 arm7_9_common_t
*arm7_9
;
2353 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
2355 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
2359 if (target
->state
!= TARGET_HALTED
)
2361 command_print(cmd_ctx
, "can't write registers while running");
2367 command_print(cmd_ctx
, "usage: write_xpsr_im8 <im8> <rotate> <not cpsr|spsr>");
2371 value
= strtoul(args
[0], NULL
, 0);
2372 rotate
= strtol(args
[1], NULL
, 0);
2373 spsr
= strtol(args
[2], NULL
, 0);
2375 arm7_9
->write_xpsr_im8(target
, value
, rotate
, spsr
);
2376 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
2378 ERROR("JTAG error while writing 8-bit immediate to xpsr");
2385 int handle_arm7_9_write_core_reg_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
2390 target_t
*target
= get_current_target(cmd_ctx
);
2391 armv4_5_common_t
*armv4_5
;
2392 arm7_9_common_t
*arm7_9
;
2394 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
2396 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
2400 if (target
->state
!= TARGET_HALTED
)
2402 command_print(cmd_ctx
, "can't write registers while running");
2408 command_print(cmd_ctx
, "usage: write_core_reg <num> <mode> <value>");
2412 num
= strtol(args
[0], NULL
, 0);
2413 mode
= strtoul(args
[1], NULL
, 0);
2414 value
= strtoul(args
[2], NULL
, 0);
2416 arm7_9_write_core_reg(target
, num
, mode
, value
);
2421 int handle_arm7_9_sw_bkpts_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
2423 target_t
*target
= get_current_target(cmd_ctx
);
2424 armv4_5_common_t
*armv4_5
;
2425 arm7_9_common_t
*arm7_9
;
2427 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
2429 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
2435 command_print(cmd_ctx
, "software breakpoints %s", (arm7_9
->sw_bkpts_enabled
) ? "enabled" : "disabled");
2439 if (strcmp("enable", args
[0]) == 0)
2441 if (arm7_9
->sw_bkpts_use_wp
)
2443 arm7_9_enable_sw_bkpts(target
);
2447 arm7_9
->sw_bkpts_enabled
= 1;
2450 else if (strcmp("disable", args
[0]) == 0)
2452 if (arm7_9
->sw_bkpts_use_wp
)
2454 arm7_9_disable_sw_bkpts(target
);
2458 arm7_9
->sw_bkpts_enabled
= 0;
2463 command_print(cmd_ctx
, "usage: arm7_9 sw_bkpts <enable|disable>");
2466 command_print(cmd_ctx
, "software breakpoints %s", (arm7_9
->sw_bkpts_enabled
) ? "enabled" : "disabled");
2471 int handle_arm7_9_force_hw_bkpts_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
2473 target_t
*target
= get_current_target(cmd_ctx
);
2474 armv4_5_common_t
*armv4_5
;
2475 arm7_9_common_t
*arm7_9
;
2477 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
2479 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
2483 if ((argc
>= 1) && (strcmp("enable", args
[0]) == 0))
2485 arm7_9
->force_hw_bkpts
= 1;
2486 if (arm7_9
->sw_bkpts_use_wp
)
2488 arm7_9_disable_sw_bkpts(target
);
2491 else if ((argc
>= 1) && (strcmp("disable", args
[0]) == 0))
2493 arm7_9
->force_hw_bkpts
= 0;
2497 command_print(cmd_ctx
, "usage: arm7_9 force_hw_bkpts <enable|disable>");
2500 command_print(cmd_ctx
, "force hardware breakpoints %s", (arm7_9
->force_hw_bkpts
) ? "enabled" : "disabled");
2505 int handle_arm7_9_dbgrq_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
2507 target_t
*target
= get_current_target(cmd_ctx
);
2508 armv4_5_common_t
*armv4_5
;
2509 arm7_9_common_t
*arm7_9
;
2511 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
2513 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
2519 if (strcmp("enable", args
[0]) == 0)
2521 arm7_9
->use_dbgrq
= 1;
2523 else if (strcmp("disable", args
[0]) == 0)
2525 arm7_9
->use_dbgrq
= 0;
2529 command_print(cmd_ctx
, "usage: arm7_9 dbgrq <enable|disable>");
2533 command_print(cmd_ctx
, "use of EmbeddedICE dbgrq instead of breakpoint for target halt %s", (arm7_9
->use_dbgrq
) ? "enabled" : "disabled");
2538 int handle_arm7_9_fast_memory_access_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
2540 target_t
*target
= get_current_target(cmd_ctx
);
2541 armv4_5_common_t
*armv4_5
;
2542 arm7_9_common_t
*arm7_9
;
2544 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
2546 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
2552 if (strcmp("enable", args
[0]) == 0)
2554 arm7_9
->fast_memory_access
= 1;
2556 else if (strcmp("disable", args
[0]) == 0)
2558 arm7_9
->fast_memory_access
= 0;
2562 command_print(cmd_ctx
, "usage: arm7_9 fast_memory_access <enable|disable>");
2566 command_print(cmd_ctx
, "fast memory access is %s", (arm7_9
->fast_memory_access
) ? "enabled" : "disabled");
2571 int handle_arm7_9_dcc_downloads_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
2573 target_t
*target
= get_current_target(cmd_ctx
);
2574 armv4_5_common_t
*armv4_5
;
2575 arm7_9_common_t
*arm7_9
;
2577 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
2579 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
2585 if (strcmp("enable", args
[0]) == 0)
2587 arm7_9
->dcc_downloads
= 1;
2589 else if (strcmp("disable", args
[0]) == 0)
2591 arm7_9
->dcc_downloads
= 0;
2595 command_print(cmd_ctx
, "usage: arm7_9 dcc_downloads <enable|disable>");
2599 command_print(cmd_ctx
, "dcc downloads are %s", (arm7_9
->dcc_downloads
) ? "enabled" : "disabled");
2604 int arm7_9_init_arch_info(target_t
*target
, arm7_9_common_t
*arm7_9
)
2606 armv4_5_common_t
*armv4_5
= &arm7_9
->armv4_5_common
;
2608 arm7_9
->common_magic
= ARM7_9_COMMON_MAGIC
;
2610 arm_jtag_setup_connection(&arm7_9
->jtag_info
);
2611 arm7_9
->wp_available
= 2;
2612 arm7_9
->wp0_used
= 0;
2613 arm7_9
->wp1_used
= 0;
2614 arm7_9
->force_hw_bkpts
= 0;
2615 arm7_9
->use_dbgrq
= 0;
2617 arm7_9
->etm_ctx
= NULL
;
2618 arm7_9
->has_single_step
= 0;
2619 arm7_9
->has_monitor_mode
= 0;
2620 arm7_9
->has_vector_catch
= 0;
2622 arm7_9
->reinit_embeddedice
= 0;
2624 arm7_9
->debug_entry_from_reset
= 0;
2626 arm7_9
->dcc_working_area
= NULL
;
2628 arm7_9
->fast_memory_access
= 0;
2629 arm7_9
->dcc_downloads
= 0;
2631 jtag_register_event_callback(arm7_9_jtag_callback
, target
);
2633 armv4_5
->arch_info
= arm7_9
;
2634 armv4_5
->read_core_reg
= arm7_9_read_core_reg
;
2635 armv4_5
->write_core_reg
= arm7_9_write_core_reg
;
2636 armv4_5
->full_context
= arm7_9_full_context
;
2638 armv4_5_init_arch_info(target
, armv4_5
);
2640 target_register_timer_callback(arm7_9_handle_target_request
, 1, 1, target
);
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