- adds two speeds to jtag_speed. reset and post reset speed. Default
[openocd.git] / src / target / arm7_9_common.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
20 #ifdef HAVE_CONFIG_H
21 #include "config.h"
22 #endif
23
24 #include "replacements.h"
25
26 #include "embeddedice.h"
27 #include "target.h"
28 #include "target_request.h"
29 #include "armv4_5.h"
30 #include "arm_jtag.h"
31 #include "jtag.h"
32 #include "log.h"
33 #include "arm7_9_common.h"
34 #include "breakpoints.h"
35
36 #include <stdlib.h>
37 #include <string.h>
38 #include <unistd.h>
39
40 #include <sys/types.h>
41 #include <sys/stat.h>
42 #include <sys/time.h>
43 #include <errno.h>
44
45 int arm7_9_debug_entry(target_t *target);
46 int arm7_9_enable_sw_bkpts(struct target_s *target);
47
48 /* command handler forward declarations */
49 int handle_arm7_9_write_xpsr_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
50 int handle_arm7_9_write_xpsr_im8_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
51 int handle_arm7_9_read_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
52 int handle_arm7_9_write_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
53 int handle_arm7_9_sw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
54 int handle_arm7_9_force_hw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
55 int handle_arm7_9_dbgrq_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
56 int handle_arm7_9_fast_memory_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
57 int handle_arm7_9_dcc_downloads_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
58 int handle_arm7_9_etm_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
59
60 int arm7_9_reinit_embeddedice(target_t *target)
61 {
62 armv4_5_common_t *armv4_5 = target->arch_info;
63 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
64
65 breakpoint_t *breakpoint = target->breakpoints;
66
67 arm7_9->wp_available = 2;
68 arm7_9->wp0_used = 0;
69 arm7_9->wp1_used = 0;
70
71 /* mark all hardware breakpoints as unset */
72 while (breakpoint)
73 {
74 if (breakpoint->type == BKPT_HARD)
75 {
76 breakpoint->set = 0;
77 }
78 breakpoint = breakpoint->next;
79 }
80
81 if (arm7_9->sw_bkpts_enabled && arm7_9->sw_bkpts_use_wp)
82 {
83 arm7_9->sw_bkpts_enabled = 0;
84 arm7_9_enable_sw_bkpts(target);
85 }
86
87 arm7_9->reinit_embeddedice = 0;
88
89 return ERROR_OK;
90 }
91
92 int arm7_9_jtag_callback(enum jtag_event event, void *priv)
93 {
94 target_t *target = priv;
95 armv4_5_common_t *armv4_5 = target->arch_info;
96 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
97
98 /* a test-logic reset occured
99 * the EmbeddedICE registers have been reset
100 * hardware breakpoints have been cleared
101 */
102 if (event == JTAG_TRST_ASSERTED)
103 {
104 arm7_9->reinit_embeddedice = 1;
105 }
106
107 return ERROR_OK;
108 }
109
110 int arm7_9_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p)
111 {
112 armv4_5_common_t *armv4_5 = target->arch_info;
113 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
114
115 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
116 {
117 return -1;
118 }
119
120 if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
121 {
122 return -1;
123 }
124
125 *armv4_5_p = armv4_5;
126 *arm7_9_p = arm7_9;
127
128 return ERROR_OK;
129 }
130
131 int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
132 {
133 armv4_5_common_t *armv4_5 = target->arch_info;
134 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
135
136 if (target->state != TARGET_HALTED)
137 {
138 WARNING("target not halted");
139 return ERROR_TARGET_NOT_HALTED;
140 }
141
142 if (arm7_9->force_hw_bkpts)
143 breakpoint->type = BKPT_HARD;
144
145 if (breakpoint->set)
146 {
147 WARNING("breakpoint already set");
148 return ERROR_OK;
149 }
150
151 if (breakpoint->type == BKPT_HARD)
152 {
153 /* either an ARM (4 byte) or Thumb (2 byte) breakpoint */
154 u32 mask = (breakpoint->length == 4) ? 0x3u : 0x1u;
155 if (!arm7_9->wp0_used)
156 {
157 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], breakpoint->address);
158 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask);
159 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffffu);
160 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
161 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
162
163 jtag_execute_queue();
164 arm7_9->wp0_used = 1;
165 breakpoint->set = 1;
166 }
167 else if (!arm7_9->wp1_used)
168 {
169 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], breakpoint->address);
170 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask);
171 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffffu);
172 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
173 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
174
175 jtag_execute_queue();
176 arm7_9->wp1_used = 1;
177 breakpoint->set = 2;
178 }
179 else
180 {
181 ERROR("BUG: no hardware comparator available");
182 return ERROR_OK;
183 }
184 }
185 else if (breakpoint->type == BKPT_SOFT)
186 {
187 if (breakpoint->length == 4)
188 {
189 u32 verify = 0xffffffff;
190 /* keep the original instruction in target endianness */
191 target->type->read_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr);
192 /* write the breakpoint instruction in target endianness (arm7_9->arm_bkpt is host endian) */
193 target_write_u32(target, breakpoint->address, arm7_9->arm_bkpt);
194
195 target->type->read_memory(target, breakpoint->address, 4, 1, (u8 *)&verify);
196 if (verify != arm7_9->arm_bkpt)
197 {
198 ERROR("Unable to set 32 bit software breakpoint at address %08x", breakpoint->address);
199 return ERROR_OK;
200 }
201 }
202 else
203 {
204 u16 verify = 0xffff;
205 /* keep the original instruction in target endianness */
206 target->type->read_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr);
207 /* write the breakpoint instruction in target endianness (arm7_9->thumb_bkpt is host endian) */
208 target_write_u16(target, breakpoint->address, arm7_9->thumb_bkpt);
209
210 target->type->read_memory(target, breakpoint->address, 2, 1, (u8 *)&verify);
211 if (verify != arm7_9->thumb_bkpt)
212 {
213 ERROR("Unable to set thumb software breakpoint at address %08x", breakpoint->address);
214 return ERROR_OK;
215 }
216 }
217 breakpoint->set = 1;
218 }
219
220 return ERROR_OK;
221
222 }
223
224 int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
225 {
226 armv4_5_common_t *armv4_5 = target->arch_info;
227 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
228
229 if (target->state != TARGET_HALTED)
230 {
231 WARNING("target not halted");
232 return ERROR_TARGET_NOT_HALTED;
233 }
234
235 if (!breakpoint->set)
236 {
237 WARNING("breakpoint not set");
238 return ERROR_OK;
239 }
240
241 if (breakpoint->type == BKPT_HARD)
242 {
243 if (breakpoint->set == 1)
244 {
245 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
246 jtag_execute_queue();
247 arm7_9->wp0_used = 0;
248 }
249 else if (breakpoint->set == 2)
250 {
251 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
252 jtag_execute_queue();
253 arm7_9->wp1_used = 0;
254 }
255 breakpoint->set = 0;
256 }
257 else
258 {
259 /* restore original instruction (kept in target endianness) */
260 if (breakpoint->length == 4)
261 {
262 u32 current_instr;
263 /* check that user program as not modified breakpoint instruction */
264 target->type->read_memory(target, breakpoint->address, 4, 1, (u8*)&current_instr);
265 if (current_instr==arm7_9->arm_bkpt)
266 target->type->write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr);
267 }
268 else
269 {
270 u16 current_instr;
271 /* check that user program as not modified breakpoint instruction */
272 target->type->read_memory(target, breakpoint->address, 2, 1, (u8*)&current_instr);
273 if (current_instr==arm7_9->thumb_bkpt)
274 target->type->write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr);
275 }
276 breakpoint->set = 0;
277 }
278
279 return ERROR_OK;
280 }
281
282 int arm7_9_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
283 {
284 armv4_5_common_t *armv4_5 = target->arch_info;
285 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
286
287 if (target->state != TARGET_HALTED)
288 {
289 WARNING("target not halted");
290 return ERROR_TARGET_NOT_HALTED;
291 }
292
293 if (arm7_9->force_hw_bkpts)
294 {
295 DEBUG("forcing use of hardware breakpoint at address 0x%8.8x", breakpoint->address);
296 breakpoint->type = BKPT_HARD;
297 }
298
299 if ((breakpoint->type == BKPT_SOFT) && (arm7_9->sw_bkpts_enabled == 0))
300 {
301 INFO("sw breakpoint requested, but software breakpoints not enabled");
302 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
303 }
304
305 if ((breakpoint->type == BKPT_HARD) && (arm7_9->wp_available < 1))
306 {
307 INFO("no watchpoint unit available for hardware breakpoint");
308 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
309 }
310
311 if ((breakpoint->length != 2) && (breakpoint->length != 4))
312 {
313 INFO("only breakpoints of two (Thumb) or four (ARM) bytes length supported");
314 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
315 }
316
317 if (breakpoint->type == BKPT_HARD)
318 arm7_9->wp_available--;
319
320 return ERROR_OK;
321 }
322
323 int arm7_9_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
324 {
325 armv4_5_common_t *armv4_5 = target->arch_info;
326 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
327
328 if (target->state != TARGET_HALTED)
329 {
330 WARNING("target not halted");
331 return ERROR_TARGET_NOT_HALTED;
332 }
333
334 if (breakpoint->set)
335 {
336 arm7_9_unset_breakpoint(target, breakpoint);
337 }
338
339 if (breakpoint->type == BKPT_HARD)
340 arm7_9->wp_available++;
341
342 return ERROR_OK;
343 }
344
345 int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
346 {
347 armv4_5_common_t *armv4_5 = target->arch_info;
348 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
349 int rw_mask = 1;
350 u32 mask;
351
352 mask = watchpoint->length - 1;
353
354 if (target->state != TARGET_HALTED)
355 {
356 WARNING("target not halted");
357 return ERROR_TARGET_NOT_HALTED;
358 }
359
360 if (watchpoint->rw == WPT_ACCESS)
361 rw_mask = 0;
362 else
363 rw_mask = 1;
364
365 if (!arm7_9->wp0_used)
366 {
367 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], watchpoint->address);
368 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask);
369 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], watchpoint->mask);
370 if( watchpoint->mask != 0xffffffffu )
371 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], watchpoint->value);
372 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
373 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
374
375 jtag_execute_queue();
376 watchpoint->set = 1;
377 arm7_9->wp0_used = 2;
378 }
379 else if (!arm7_9->wp1_used)
380 {
381 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], watchpoint->address);
382 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask);
383 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], watchpoint->mask);
384 if( watchpoint->mask != 0xffffffffu )
385 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], watchpoint->value);
386 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
387 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
388
389 jtag_execute_queue();
390 watchpoint->set = 2;
391 arm7_9->wp1_used = 2;
392 }
393 else
394 {
395 ERROR("BUG: no hardware comparator available");
396 return ERROR_OK;
397 }
398
399 return ERROR_OK;
400 }
401
402 int arm7_9_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
403 {
404 armv4_5_common_t *armv4_5 = target->arch_info;
405 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
406
407 if (target->state != TARGET_HALTED)
408 {
409 WARNING("target not halted");
410 return ERROR_TARGET_NOT_HALTED;
411 }
412
413 if (!watchpoint->set)
414 {
415 WARNING("breakpoint not set");
416 return ERROR_OK;
417 }
418
419 if (watchpoint->set == 1)
420 {
421 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
422 jtag_execute_queue();
423 arm7_9->wp0_used = 0;
424 }
425 else if (watchpoint->set == 2)
426 {
427 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
428 jtag_execute_queue();
429 arm7_9->wp1_used = 0;
430 }
431 watchpoint->set = 0;
432
433 return ERROR_OK;
434 }
435
436 int arm7_9_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
437 {
438 armv4_5_common_t *armv4_5 = target->arch_info;
439 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
440
441 if (target->state != TARGET_HALTED)
442 {
443 WARNING("target not halted");
444 return ERROR_TARGET_NOT_HALTED;
445 }
446
447 if (arm7_9->wp_available < 1)
448 {
449 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
450 }
451
452 if ((watchpoint->length != 1) && (watchpoint->length != 2) && (watchpoint->length != 4))
453 {
454 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
455 }
456
457 arm7_9->wp_available--;
458
459 return ERROR_OK;
460 }
461
462 int arm7_9_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
463 {
464 armv4_5_common_t *armv4_5 = target->arch_info;
465 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
466
467 if (target->state != TARGET_HALTED)
468 {
469 WARNING("target not halted");
470 return ERROR_TARGET_NOT_HALTED;
471 }
472
473 if (watchpoint->set)
474 {
475 arm7_9_unset_watchpoint(target, watchpoint);
476 }
477
478 arm7_9->wp_available++;
479
480 return ERROR_OK;
481 }
482
483 int arm7_9_enable_sw_bkpts(struct target_s *target)
484 {
485 armv4_5_common_t *armv4_5 = target->arch_info;
486 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
487 int retval;
488
489 if (arm7_9->sw_bkpts_enabled)
490 return ERROR_OK;
491
492 if (arm7_9->wp_available < 1)
493 {
494 WARNING("can't enable sw breakpoints with no watchpoint unit available");
495 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
496 }
497 arm7_9->wp_available--;
498
499 if (!arm7_9->wp0_used)
500 {
501 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], arm7_9->arm_bkpt);
502 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0x0);
503 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffffu);
504 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
505 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
506 arm7_9->sw_bkpts_enabled = 1;
507 arm7_9->wp0_used = 3;
508 }
509 else if (!arm7_9->wp1_used)
510 {
511 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], arm7_9->arm_bkpt);
512 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0x0);
513 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0xffffffffu);
514 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
515 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
516 arm7_9->sw_bkpts_enabled = 2;
517 arm7_9->wp1_used = 3;
518 }
519 else
520 {
521 ERROR("BUG: both watchpoints used, but wp_available >= 1");
522 exit(-1);
523 }
524
525 if ((retval = jtag_execute_queue()) != ERROR_OK)
526 {
527 ERROR("error writing EmbeddedICE registers to enable sw breakpoints");
528 exit(-1);
529 };
530
531 return ERROR_OK;
532 }
533
534 int arm7_9_disable_sw_bkpts(struct target_s *target)
535 {
536 armv4_5_common_t *armv4_5 = target->arch_info;
537 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
538
539 if (!arm7_9->sw_bkpts_enabled)
540 return ERROR_OK;
541
542 if (arm7_9->sw_bkpts_enabled == 1)
543 {
544 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
545 arm7_9->sw_bkpts_enabled = 0;
546 arm7_9->wp0_used = 0;
547 arm7_9->wp_available++;
548 }
549 else if (arm7_9->sw_bkpts_enabled == 2)
550 {
551 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
552 arm7_9->sw_bkpts_enabled = 0;
553 arm7_9->wp1_used = 0;
554 arm7_9->wp_available++;
555 }
556
557 return ERROR_OK;
558 }
559
560 int arm7_9_execute_sys_speed(struct target_s *target)
561 {
562 int timeout;
563 int retval;
564
565 armv4_5_common_t *armv4_5 = target->arch_info;
566 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
567 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
568 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
569
570 /* set RESTART instruction */
571 jtag_add_end_state(TAP_RTI);
572 arm_jtag_set_instr(jtag_info, 0x4, NULL);
573
574 for (timeout=0; timeout<50; timeout++)
575 {
576 /* read debug status register */
577 embeddedice_read_reg(dbg_stat);
578 if ((retval = jtag_execute_queue()) != ERROR_OK)
579 return retval;
580 if ((buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))
581 && (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_SYSCOMP, 1)))
582 break;
583 usleep(100000);
584 }
585 if (timeout == 50)
586 {
587 ERROR("timeout waiting for SYSCOMP & DBGACK, last DBG_STATUS: %x", buf_get_u32(dbg_stat->value, 0, dbg_stat->size));
588 return ERROR_TARGET_TIMEOUT;
589 }
590
591 return ERROR_OK;
592 }
593
594 int arm7_9_execute_fast_sys_speed(struct target_s *target)
595 {
596 static int set=0;
597 static u8 check_value[4], check_mask[4];
598
599 armv4_5_common_t *armv4_5 = target->arch_info;
600 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
601 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
602 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
603
604 /* set RESTART instruction */
605 jtag_add_end_state(TAP_RTI);
606 arm_jtag_set_instr(jtag_info, 0x4, NULL);
607
608 if (!set)
609 {
610 /* check for DBGACK and SYSCOMP set (others don't care) */
611
612 /* NB! These are constants that must be available until after next jtag_execute() and
613 we evaluate the values upon first execution in lieu of setting up these constants
614 during early setup.
615 */
616 buf_set_u32(check_value, 0, 32, 0x9);
617 buf_set_u32(check_mask, 0, 32, 0x9);
618 set=1;
619 }
620
621 /* read debug status register */
622 embeddedice_read_reg_w_check(dbg_stat, check_value, check_value);
623
624 return ERROR_OK;
625 }
626
627 int arm7_9_target_request_data(target_t *target, u32 size, u8 *buffer)
628 {
629 armv4_5_common_t *armv4_5 = target->arch_info;
630 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
631 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
632 u32 *data;
633 int i;
634
635 data = malloc(size * (sizeof(u32)));
636
637 embeddedice_receive(jtag_info, data, size);
638
639 for (i = 0; i < size; i++)
640 {
641 h_u32_to_le(buffer + (i * 4), data[i]);
642 }
643
644 free(data);
645
646 return ERROR_OK;
647 }
648
649 int arm7_9_handle_target_request(void *priv)
650 {
651 target_t *target = priv;
652 armv4_5_common_t *armv4_5 = target->arch_info;
653 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
654 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
655 reg_t *dcc_control = &arm7_9->eice_cache->reg_list[EICE_COMMS_CTRL];
656
657 if (!target->dbg_msg_enabled)
658 return ERROR_OK;
659
660 if (target->state == TARGET_RUNNING)
661 {
662 /* read DCC control register */
663 embeddedice_read_reg(dcc_control);
664 jtag_execute_queue();
665
666 /* check W bit */
667 if (buf_get_u32(dcc_control->value, 1, 1) == 1)
668 {
669 u32 request;
670
671 embeddedice_receive(jtag_info, &request, 1);
672 target_request(target, request);
673 }
674 }
675
676 return ERROR_OK;
677 }
678
679 int arm7_9_poll(target_t *target)
680 {
681 int retval;
682 armv4_5_common_t *armv4_5 = target->arch_info;
683 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
684 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
685
686 if (arm7_9->reinit_embeddedice)
687 {
688 arm7_9_reinit_embeddedice(target);
689 }
690
691 /* read debug status register */
692 embeddedice_read_reg(dbg_stat);
693 if ((retval = jtag_execute_queue()) != ERROR_OK)
694 {
695 return retval;
696 }
697
698 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))
699 {
700 DEBUG("DBGACK set, dbg_state->value: 0x%x", buf_get_u32(dbg_stat->value, 0, 32));
701 if (target->state == TARGET_UNKNOWN)
702 {
703 target->state = TARGET_RUNNING;
704 WARNING("DBGACK set while target was in unknown state. Reset or initialize target.");
705 }
706 if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET))
707 {
708 target->state = TARGET_HALTED;
709 if ((retval = arm7_9_debug_entry(target)) != ERROR_OK)
710 return retval;
711
712 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
713 }
714 if (target->state == TARGET_DEBUG_RUNNING)
715 {
716 target->state = TARGET_HALTED;
717 if ((retval = arm7_9_debug_entry(target)) != ERROR_OK)
718 return retval;
719
720 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
721 }
722 if (target->state != TARGET_HALTED)
723 {
724 WARNING("DBGACK set, but the target did not end up in the halted stated %d", target->state);
725 }
726 }
727 else
728 {
729 if (target->state != TARGET_DEBUG_RUNNING)
730 target->state = TARGET_RUNNING;
731 }
732
733 return ERROR_OK;
734 }
735
736 int arm7_9_assert_reset(target_t *target)
737 {
738 int retval;
739
740 DEBUG("target->state: %s", target_state_strings[target->state]);
741
742 if (target->state == TARGET_HALTED || target->state == TARGET_UNKNOWN)
743 {
744 /* if the target wasn't running, there might be working areas allocated */
745 target_free_all_working_areas(target);
746
747 /* assert SRST and TRST */
748 /* system would get ouf sync if we didn't reset test-logic, too */
749 if ((retval = jtag_add_reset(1, 1)) != ERROR_OK)
750 {
751 if (retval == ERROR_JTAG_RESET_CANT_SRST)
752 {
753 WARNING("can't assert srst");
754 return retval;
755 }
756 else
757 {
758 ERROR("unknown error");
759 exit(-1);
760 }
761 }
762 jtag_add_sleep(5000);
763 if ((retval = jtag_add_reset(0, 1)) != ERROR_OK)
764 {
765 if (retval == ERROR_JTAG_RESET_WOULD_ASSERT_TRST)
766 {
767 retval = jtag_add_reset(1, 1);
768 }
769 }
770 }
771 else
772 {
773 if ((retval = jtag_add_reset(0, 1)) != ERROR_OK)
774 {
775 if (retval == ERROR_JTAG_RESET_WOULD_ASSERT_TRST)
776 {
777 retval = jtag_add_reset(1, 1);
778 }
779
780 if (retval == ERROR_JTAG_RESET_CANT_SRST)
781 {
782 WARNING("can't assert srst");
783 return retval;
784 }
785 else if (retval != ERROR_OK)
786 {
787 ERROR("unknown error");
788 exit(-1);
789 }
790 }
791 }
792
793 target->state = TARGET_RESET;
794 jtag_add_sleep(50000);
795
796 armv4_5_invalidate_core_regs(target);
797
798 return ERROR_OK;
799
800 }
801
802 int arm7_9_deassert_reset(target_t *target)
803 {
804 DEBUG("target->state: %s", target_state_strings[target->state]);
805
806 /* deassert reset lines */
807 jtag_add_reset(0, 0);
808
809 return ERROR_OK;
810 }
811
812 int arm7_9_clear_halt(target_t *target)
813 {
814 armv4_5_common_t *armv4_5 = target->arch_info;
815 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
816 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
817
818 /* we used DBGRQ only if we didn't come out of reset */
819 if (!arm7_9->debug_entry_from_reset && arm7_9->use_dbgrq)
820 {
821 /* program EmbeddedICE Debug Control Register to deassert DBGRQ
822 */
823 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
824 embeddedice_store_reg(dbg_ctrl);
825 }
826 else
827 {
828 if (arm7_9->debug_entry_from_reset && arm7_9->has_vector_catch)
829 {
830 /* if we came out of reset, and vector catch is supported, we used
831 * vector catch to enter debug state
832 * restore the register in that case
833 */
834 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH]);
835 }
836 else
837 {
838 /* restore registers if watchpoint unit 0 was in use
839 */
840 if (arm7_9->wp0_used)
841 {
842 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
843 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);
844 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK]);
845 }
846 /* control value always has to be restored, as it was either disabled,
847 * or enabled with possibly different bits
848 */
849 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]);
850 }
851 }
852
853 return ERROR_OK;
854 }
855
856 int arm7_9_soft_reset_halt(struct target_s *target)
857 {
858 armv4_5_common_t *armv4_5 = target->arch_info;
859 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
860 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
861 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
862 int i;
863 int retval;
864
865 if ((retval=target->type->halt(target))!=ERROR_OK)
866 return retval;
867
868 for (i=0; i<10; i++)
869 {
870 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) != 0)
871 break;
872 embeddedice_read_reg(dbg_stat);
873 if ((retval=jtag_execute_queue())!=ERROR_OK)
874 return retval;
875 /* do not eat all CPU, time out after 1 se*/
876 usleep(100*1000);
877
878 }
879 if (i==10)
880 {
881 ERROR("Failed to halt CPU after 1 sec");
882 return ERROR_TARGET_TIMEOUT;
883 }
884 target->state = TARGET_HALTED;
885
886 /* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS
887 * ensure that DBGRQ is cleared
888 */
889 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
890 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
891 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 1);
892 embeddedice_store_reg(dbg_ctrl);
893
894 arm7_9_clear_halt(target);
895
896 /* if the target is in Thumb state, change to ARM state */
897 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_ITBIT, 1))
898 {
899 u32 r0_thumb, pc_thumb;
900 DEBUG("target entered debug from Thumb state, changing to ARM");
901 /* Entered debug from Thumb mode */
902 armv4_5->core_state = ARMV4_5_STATE_THUMB;
903 arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb);
904 }
905
906 /* all register content is now invalid */
907 armv4_5_invalidate_core_regs(target);
908
909 /* SVC, ARM state, IRQ and FIQ disabled */
910 buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
911 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
912 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
913
914 /* start fetching from 0x0 */
915 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
916 armv4_5->core_cache->reg_list[15].dirty = 1;
917 armv4_5->core_cache->reg_list[15].valid = 1;
918
919 armv4_5->core_mode = ARMV4_5_MODE_SVC;
920 armv4_5->core_state = ARMV4_5_STATE_ARM;
921
922 /* reset registers */
923 for (i = 0; i <= 14; i++)
924 {
925 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32, 0xffffffff);
926 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 1;
927 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid = 1;
928 }
929
930 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
931
932 return ERROR_OK;
933 }
934
935 int arm7_9_prepare_reset_halt(target_t *target)
936 {
937 armv4_5_common_t *armv4_5 = target->arch_info;
938 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
939
940 /* poll the target, and resume if it was currently halted */
941 arm7_9_poll(target);
942 if (target->state == TARGET_HALTED)
943 {
944 arm7_9_resume(target, 1, 0x0, 0, 1);
945 }
946
947 if (arm7_9->has_vector_catch)
948 {
949 /* program vector catch register to catch reset vector */
950 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH], 0x1);
951 }
952 else
953 {
954 /* program watchpoint unit to match on reset vector address */
955 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0x3);
956 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0x0);
957 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x100);
958 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xf7);
959 }
960
961 return ERROR_OK;
962 }
963
964 int arm7_9_halt(target_t *target)
965 {
966 armv4_5_common_t *armv4_5 = target->arch_info;
967 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
968 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
969
970 DEBUG("target->state: %s", target_state_strings[target->state]);
971
972 if (target->state == TARGET_HALTED)
973 {
974 WARNING("target was already halted");
975 return ERROR_OK;
976 }
977
978 if (target->state == TARGET_UNKNOWN)
979 {
980 WARNING("target was in unknown state when halt was requested");
981 }
982
983 if (target->state == TARGET_RESET)
984 {
985 if ((jtag_reset_config & RESET_SRST_PULLS_TRST) && jtag_srst)
986 {
987 ERROR("can't request a halt while in reset if nSRST pulls nTRST");
988 return ERROR_TARGET_FAILURE;
989 }
990 else
991 {
992 /* we came here in a reset_halt or reset_init sequence
993 * debug entry was already prepared in arm7_9_prepare_reset_halt()
994 */
995 target->debug_reason = DBG_REASON_DBGRQ;
996
997 return ERROR_OK;
998 }
999 }
1000
1001 if (arm7_9->use_dbgrq)
1002 {
1003 /* program EmbeddedICE Debug Control Register to assert DBGRQ
1004 */
1005 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 1);
1006 embeddedice_store_reg(dbg_ctrl);
1007 }
1008 else
1009 {
1010 /* program watchpoint unit to match on any address
1011 */
1012 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
1013 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
1014 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x100);
1015 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xf7);
1016 }
1017
1018 target->debug_reason = DBG_REASON_DBGRQ;
1019
1020 return ERROR_OK;
1021 }
1022
1023 int arm7_9_debug_entry(target_t *target)
1024 {
1025 int i;
1026 u32 context[16];
1027 u32* context_p[16];
1028 u32 r0_thumb, pc_thumb;
1029 u32 cpsr;
1030 int retval;
1031 /* get pointers to arch-specific information */
1032 armv4_5_common_t *armv4_5 = target->arch_info;
1033 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1034 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
1035 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1036
1037 #ifdef _DEBUG_ARM7_9_
1038 DEBUG("-");
1039 #endif
1040
1041 if (arm7_9->pre_debug_entry)
1042 arm7_9->pre_debug_entry(target);
1043
1044 /* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS
1045 * ensure that DBGRQ is cleared
1046 */
1047 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
1048 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
1049 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 1);
1050 embeddedice_store_reg(dbg_ctrl);
1051
1052 arm7_9_clear_halt(target);
1053
1054 if ((retval = jtag_execute_queue()) != ERROR_OK)
1055 {
1056 switch (retval)
1057 {
1058 case ERROR_JTAG_QUEUE_FAILED:
1059 ERROR("JTAG queue failed while writing EmbeddedICE control register");
1060 exit(-1);
1061 break;
1062 default:
1063 break;
1064 }
1065 }
1066
1067 if ((retval = arm7_9->examine_debug_reason(target)) != ERROR_OK)
1068 return retval;
1069
1070
1071 if (target->state != TARGET_HALTED)
1072 {
1073 WARNING("target not halted");
1074 return ERROR_TARGET_NOT_HALTED;
1075 }
1076
1077 /* if the target is in Thumb state, change to ARM state */
1078 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_ITBIT, 1))
1079 {
1080 DEBUG("target entered debug from Thumb state");
1081 /* Entered debug from Thumb mode */
1082 armv4_5->core_state = ARMV4_5_STATE_THUMB;
1083 arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb);
1084 DEBUG("r0_thumb: 0x%8.8x, pc_thumb: 0x%8.8x", r0_thumb, pc_thumb);
1085 }
1086 else
1087 {
1088 DEBUG("target entered debug from ARM state");
1089 /* Entered debug from ARM mode */
1090 armv4_5->core_state = ARMV4_5_STATE_ARM;
1091 }
1092
1093 for (i = 0; i < 16; i++)
1094 context_p[i] = &context[i];
1095 /* save core registers (r0 - r15 of current core mode) */
1096 arm7_9->read_core_regs(target, 0xffff, context_p);
1097
1098 arm7_9->read_xpsr(target, &cpsr, 0);
1099
1100 if ((retval = jtag_execute_queue()) != ERROR_OK)
1101 return retval;
1102
1103 /* if the core has been executing in Thumb state, set the T bit */
1104 if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1105 cpsr |= 0x20;
1106
1107 buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32, cpsr);
1108 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 0;
1109 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
1110
1111 armv4_5->core_mode = cpsr & 0x1f;
1112
1113 if (armv4_5_mode_to_number(armv4_5->core_mode) == -1)
1114 {
1115 target->state = TARGET_UNKNOWN;
1116 ERROR("cpsr contains invalid mode value - communication failure");
1117 return ERROR_TARGET_FAILURE;
1118 }
1119
1120 DEBUG("target entered debug state in %s mode", armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)]);
1121
1122 if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1123 {
1124 DEBUG("thumb state, applying fixups");
1125 context[0] = r0_thumb;
1126 context[15] = pc_thumb;
1127 } else if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1128 {
1129 /* adjust value stored by STM */
1130 context[15] -= 3 * 4;
1131 }
1132
1133 if ((target->debug_reason == DBG_REASON_BREAKPOINT)
1134 || (target->debug_reason == DBG_REASON_SINGLESTEP)
1135 || (target->debug_reason == DBG_REASON_WATCHPOINT)
1136 || (target->debug_reason == DBG_REASON_WPTANDBKPT)
1137 || ((target->debug_reason == DBG_REASON_DBGRQ) && (arm7_9->use_dbgrq == 0)))
1138 context[15] -= 3 * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2);
1139 else if (target->debug_reason == DBG_REASON_DBGRQ)
1140 context[15] -= arm7_9->dbgreq_adjust_pc * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2);
1141 else
1142 {
1143 ERROR("unknown debug reason: %i", target->debug_reason);
1144 }
1145
1146
1147 for (i=0; i<=15; i++)
1148 {
1149 DEBUG("r%i: 0x%8.8x", i, context[i]);
1150 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32, context[i]);
1151 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 0;
1152 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid = 1;
1153 }
1154
1155 DEBUG("entered debug state at PC 0x%x", context[15]);
1156
1157 /* exceptions other than USR & SYS have a saved program status register */
1158 if ((armv4_5_mode_to_number(armv4_5->core_mode) != ARMV4_5_MODE_USR) && (armv4_5_mode_to_number(armv4_5->core_mode) != ARMV4_5_MODE_SYS))
1159 {
1160 u32 spsr;
1161 arm7_9->read_xpsr(target, &spsr, 1);
1162 jtag_execute_queue();
1163 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).value, 0, 32, spsr);
1164 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).dirty = 0;
1165 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).valid = 1;
1166 }
1167
1168 /* r0 and r15 (pc) have to be restored later */
1169 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).valid;
1170 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15).valid;
1171
1172 if ((retval = jtag_execute_queue()) != ERROR_OK)
1173 return retval;
1174
1175 if (arm7_9->post_debug_entry)
1176 arm7_9->post_debug_entry(target);
1177
1178 return ERROR_OK;
1179 }
1180
1181 int arm7_9_full_context(target_t *target)
1182 {
1183 int i;
1184 int retval;
1185 armv4_5_common_t *armv4_5 = target->arch_info;
1186 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1187
1188 DEBUG("-");
1189
1190 if (target->state != TARGET_HALTED)
1191 {
1192 WARNING("target not halted");
1193 return ERROR_TARGET_NOT_HALTED;
1194 }
1195
1196 /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
1197 * SYS shares registers with User, so we don't touch SYS
1198 */
1199 for(i = 0; i < 6; i++)
1200 {
1201 u32 mask = 0;
1202 u32* reg_p[16];
1203 int j;
1204 int valid = 1;
1205
1206 /* check if there are invalid registers in the current mode
1207 */
1208 for (j = 0; j <= 16; j++)
1209 {
1210 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid == 0)
1211 valid = 0;
1212 }
1213
1214 if (!valid)
1215 {
1216 u32 tmp_cpsr;
1217
1218 /* change processor mode (and mask T bit) */
1219 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1220 tmp_cpsr |= armv4_5_number_to_mode(i);
1221 tmp_cpsr &= ~0x20;
1222 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1223
1224 for (j = 0; j < 15; j++)
1225 {
1226 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid == 0)
1227 {
1228 reg_p[j] = (u32*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).value;
1229 mask |= 1 << j;
1230 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid = 1;
1231 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).dirty = 0;
1232 }
1233 }
1234
1235 /* if only the PSR is invalid, mask is all zeroes */
1236 if (mask)
1237 arm7_9->read_core_regs(target, mask, reg_p);
1238
1239 /* check if the PSR has to be read */
1240 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).valid == 0)
1241 {
1242 arm7_9->read_xpsr(target, (u32*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).value, 1);
1243 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).valid = 1;
1244 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).dirty = 0;
1245 }
1246 }
1247 }
1248
1249 /* restore processor mode (mask T bit) */
1250 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
1251
1252 if ((retval = jtag_execute_queue()) != ERROR_OK)
1253 {
1254 ERROR("JTAG failure");
1255 exit(-1);
1256 }
1257 return ERROR_OK;
1258 }
1259
1260 int arm7_9_restore_context(target_t *target)
1261 {
1262 armv4_5_common_t *armv4_5 = target->arch_info;
1263 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1264 reg_t *reg;
1265 armv4_5_core_reg_t *reg_arch_info;
1266 enum armv4_5_mode current_mode = armv4_5->core_mode;
1267 int i, j;
1268 int dirty;
1269 int mode_change;
1270
1271 DEBUG("-");
1272
1273 if (target->state != TARGET_HALTED)
1274 {
1275 WARNING("target not halted");
1276 return ERROR_TARGET_NOT_HALTED;
1277 }
1278
1279 if (arm7_9->pre_restore_context)
1280 arm7_9->pre_restore_context(target);
1281
1282 /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
1283 * SYS shares registers with User, so we don't touch SYS
1284 */
1285 for (i = 0; i < 6; i++)
1286 {
1287 DEBUG("examining %s mode", armv4_5_mode_strings[i]);
1288 dirty = 0;
1289 mode_change = 0;
1290 /* check if there are dirty registers in the current mode
1291 */
1292 for (j = 0; j <= 16; j++)
1293 {
1294 reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j);
1295 reg_arch_info = reg->arch_info;
1296 if (reg->dirty == 1)
1297 {
1298 if (reg->valid == 1)
1299 {
1300 dirty = 1;
1301 DEBUG("examining dirty reg: %s", reg->name);
1302 if ((reg_arch_info->mode != ARMV4_5_MODE_ANY)
1303 && (reg_arch_info->mode != current_mode)
1304 && !((reg_arch_info->mode == ARMV4_5_MODE_USR) && (armv4_5->core_mode == ARMV4_5_MODE_SYS))
1305 && !((reg_arch_info->mode == ARMV4_5_MODE_SYS) && (armv4_5->core_mode == ARMV4_5_MODE_USR)))
1306 {
1307 mode_change = 1;
1308 DEBUG("require mode change");
1309 }
1310 }
1311 else
1312 {
1313 ERROR("BUG: dirty register '%s', but no valid data", reg->name);
1314 }
1315 }
1316 }
1317
1318 if (dirty)
1319 {
1320 u32 mask = 0x0;
1321 int num_regs = 0;
1322 u32 regs[16];
1323
1324 if (mode_change)
1325 {
1326 u32 tmp_cpsr;
1327
1328 /* change processor mode (mask T bit) */
1329 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1330 tmp_cpsr |= armv4_5_number_to_mode(i);
1331 tmp_cpsr &= ~0x20;
1332 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1333 current_mode = armv4_5_number_to_mode(i);
1334 }
1335
1336 for (j = 0; j <= 14; j++)
1337 {
1338 reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j);
1339 reg_arch_info = reg->arch_info;
1340
1341
1342 if (reg->dirty == 1)
1343 {
1344 regs[j] = buf_get_u32(reg->value, 0, 32);
1345 mask |= 1 << j;
1346 num_regs++;
1347 reg->dirty = 0;
1348 reg->valid = 1;
1349 DEBUG("writing register %i of mode %s with value 0x%8.8x", j, armv4_5_mode_strings[i], regs[j]);
1350 }
1351 }
1352
1353 if (mask)
1354 {
1355 arm7_9->write_core_regs(target, mask, regs);
1356 }
1357
1358 reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16);
1359 reg_arch_info = reg->arch_info;
1360 if ((reg->dirty) && (reg_arch_info->mode != ARMV4_5_MODE_ANY))
1361 {
1362 DEBUG("writing SPSR of mode %i with value 0x%8.8x", i, buf_get_u32(reg->value, 0, 32));
1363 arm7_9->write_xpsr(target, buf_get_u32(reg->value, 0, 32), 1);
1364 }
1365 }
1366 }
1367
1368 if ((armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty == 0) && (armv4_5->core_mode != current_mode))
1369 {
1370 /* restore processor mode (mask T bit) */
1371 u32 tmp_cpsr;
1372
1373 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1374 tmp_cpsr |= armv4_5_number_to_mode(i);
1375 tmp_cpsr &= ~0x20;
1376 DEBUG("writing lower 8 bit of cpsr with value 0x%2.2x", tmp_cpsr);
1377 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1378 }
1379 else if (armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty == 1)
1380 {
1381 /* CPSR has been changed, full restore necessary (mask T bit) */
1382 DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
1383 arm7_9->write_xpsr(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32) & ~0x20, 0);
1384 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 0;
1385 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
1386 }
1387
1388 /* restore PC */
1389 DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1390 arm7_9->write_pc(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1391 armv4_5->core_cache->reg_list[15].dirty = 0;
1392
1393 if (arm7_9->post_restore_context)
1394 arm7_9->post_restore_context(target);
1395
1396 return ERROR_OK;
1397 }
1398
1399 int arm7_9_restart_core(struct target_s *target)
1400 {
1401 armv4_5_common_t *armv4_5 = target->arch_info;
1402 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1403 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
1404
1405 /* set RESTART instruction */
1406 jtag_add_end_state(TAP_RTI);
1407 arm_jtag_set_instr(jtag_info, 0x4, NULL);
1408
1409 jtag_add_runtest(1, TAP_RTI);
1410 if ((jtag_execute_queue()) != ERROR_OK)
1411 {
1412 exit(-1);
1413 }
1414
1415 return ERROR_OK;
1416 }
1417
1418 void arm7_9_enable_watchpoints(struct target_s *target)
1419 {
1420 watchpoint_t *watchpoint = target->watchpoints;
1421
1422 while (watchpoint)
1423 {
1424 if (watchpoint->set == 0)
1425 arm7_9_set_watchpoint(target, watchpoint);
1426 watchpoint = watchpoint->next;
1427 }
1428 }
1429
1430 void arm7_9_enable_breakpoints(struct target_s *target)
1431 {
1432 breakpoint_t *breakpoint = target->breakpoints;
1433
1434 /* set any pending breakpoints */
1435 while (breakpoint)
1436 {
1437 if (breakpoint->set == 0)
1438 arm7_9_set_breakpoint(target, breakpoint);
1439 breakpoint = breakpoint->next;
1440 }
1441 }
1442
1443 void arm7_9_disable_bkpts_and_wpts(struct target_s *target)
1444 {
1445 breakpoint_t *breakpoint = target->breakpoints;
1446 watchpoint_t *watchpoint = target->watchpoints;
1447
1448 /* set any pending breakpoints */
1449 while (breakpoint)
1450 {
1451 if (breakpoint->set != 0)
1452 arm7_9_unset_breakpoint(target, breakpoint);
1453 breakpoint = breakpoint->next;
1454 }
1455
1456 while (watchpoint)
1457 {
1458 if (watchpoint->set != 0)
1459 arm7_9_unset_watchpoint(target, watchpoint);
1460 watchpoint = watchpoint->next;
1461 }
1462 }
1463
1464 int arm7_9_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution)
1465 {
1466 armv4_5_common_t *armv4_5 = target->arch_info;
1467 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1468 breakpoint_t *breakpoint = target->breakpoints;
1469 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1470 int err;
1471
1472 DEBUG("-");
1473
1474 if (target->state != TARGET_HALTED)
1475 {
1476 WARNING("target not halted");
1477 return ERROR_TARGET_NOT_HALTED;
1478 }
1479
1480 if (!debug_execution)
1481 {
1482 target_free_all_working_areas(target);
1483 }
1484
1485 /* current = 1: continue on current pc, otherwise continue at <address> */
1486 if (!current)
1487 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
1488
1489 /* the front-end may request us not to handle breakpoints */
1490 if (handle_breakpoints)
1491 {
1492 if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
1493 {
1494 DEBUG("unset breakpoint at 0x%8.8x", breakpoint->address);
1495 arm7_9_unset_breakpoint(target, breakpoint);
1496
1497 DEBUG("enable single-step");
1498 arm7_9->enable_single_step(target);
1499
1500 target->debug_reason = DBG_REASON_SINGLESTEP;
1501
1502 arm7_9_restore_context(target);
1503
1504 if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1505 arm7_9->branch_resume(target);
1506 else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1507 {
1508 arm7_9->branch_resume_thumb(target);
1509 }
1510 else
1511 {
1512 ERROR("unhandled core state");
1513 exit(-1);
1514 }
1515
1516 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
1517 embeddedice_write_reg(dbg_ctrl, buf_get_u32(dbg_ctrl->value, 0, dbg_ctrl->size));
1518 err = arm7_9_execute_sys_speed(target);
1519
1520 DEBUG("disable single-step");
1521 arm7_9->disable_single_step(target);
1522
1523 if (err != ERROR_OK)
1524 {
1525 arm7_9_set_breakpoint(target, breakpoint);
1526 target->state = TARGET_UNKNOWN;
1527 return err;
1528 }
1529
1530 arm7_9_debug_entry(target);
1531 DEBUG("new PC after step: 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1532
1533 DEBUG("set breakpoint at 0x%8.8x", breakpoint->address);
1534 arm7_9_set_breakpoint(target, breakpoint);
1535 }
1536 }
1537
1538 /* enable any pending breakpoints and watchpoints */
1539 arm7_9_enable_breakpoints(target);
1540 arm7_9_enable_watchpoints(target);
1541
1542 arm7_9_restore_context(target);
1543
1544 if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1545 {
1546 arm7_9->branch_resume(target);
1547 }
1548 else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1549 {
1550 arm7_9->branch_resume_thumb(target);
1551 }
1552 else
1553 {
1554 ERROR("unhandled core state");
1555 exit(-1);
1556 }
1557
1558 /* deassert DBGACK and INTDIS */
1559 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
1560 /* INTDIS only when we really resume, not during debug execution */
1561 if (!debug_execution)
1562 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 0);
1563 embeddedice_write_reg(dbg_ctrl, buf_get_u32(dbg_ctrl->value, 0, dbg_ctrl->size));
1564
1565 arm7_9_restart_core(target);
1566
1567 target->debug_reason = DBG_REASON_NOTHALTED;
1568
1569 if (!debug_execution)
1570 {
1571 /* registers are now invalid */
1572 armv4_5_invalidate_core_regs(target);
1573 target->state = TARGET_RUNNING;
1574 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1575 }
1576 else
1577 {
1578 target->state = TARGET_DEBUG_RUNNING;
1579 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
1580 }
1581
1582 DEBUG("target resumed");
1583
1584 return ERROR_OK;
1585 }
1586
1587 void arm7_9_enable_eice_step(target_t *target)
1588 {
1589 armv4_5_common_t *armv4_5 = target->arch_info;
1590 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1591
1592 /* setup an inverse breakpoint on the current PC
1593 * - comparator 1 matches the current address
1594 * - rangeout from comparator 1 is connected to comparator 0 rangein
1595 * - comparator 0 matches any address, as long as rangein is low */
1596 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
1597 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
1598 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x100);
1599 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0x77);
1600 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1601 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0);
1602 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffff);
1603 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
1604 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], 0xf7);
1605 }
1606
1607 void arm7_9_disable_eice_step(target_t *target)
1608 {
1609 armv4_5_common_t *armv4_5 = target->arch_info;
1610 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1611
1612 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
1613 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);
1614 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]);
1615 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK]);
1616 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE]);
1617 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK]);
1618 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK]);
1619 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK]);
1620 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE]);
1621 }
1622
1623 int arm7_9_step(struct target_s *target, int current, u32 address, int handle_breakpoints)
1624 {
1625 armv4_5_common_t *armv4_5 = target->arch_info;
1626 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1627 breakpoint_t *breakpoint = NULL;
1628 int err;
1629
1630 if (target->state != TARGET_HALTED)
1631 {
1632 WARNING("target not halted");
1633 return ERROR_TARGET_NOT_HALTED;
1634 }
1635
1636 /* current = 1: continue on current pc, otherwise continue at <address> */
1637 if (!current)
1638 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
1639
1640 /* the front-end may request us not to handle breakpoints */
1641 if (handle_breakpoints)
1642 if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
1643 arm7_9_unset_breakpoint(target, breakpoint);
1644
1645 target->debug_reason = DBG_REASON_SINGLESTEP;
1646
1647 arm7_9_restore_context(target);
1648
1649 arm7_9->enable_single_step(target);
1650
1651 if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1652 {
1653 arm7_9->branch_resume(target);
1654 }
1655 else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1656 {
1657 arm7_9->branch_resume_thumb(target);
1658 }
1659 else
1660 {
1661 ERROR("unhandled core state");
1662 exit(-1);
1663 }
1664
1665 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1666
1667 err = arm7_9_execute_sys_speed(target);
1668 arm7_9->disable_single_step(target);
1669
1670 /* registers are now invalid */
1671 armv4_5_invalidate_core_regs(target);
1672
1673 if (err != ERROR_OK)
1674 {
1675 target->state = TARGET_UNKNOWN;
1676 } else {
1677 arm7_9_debug_entry(target);
1678 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
1679 DEBUG("target stepped");
1680 }
1681
1682 if (breakpoint)
1683 arm7_9_set_breakpoint(target, breakpoint);
1684
1685 return err;
1686
1687 }
1688
1689 int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mode)
1690 {
1691 u32* reg_p[16];
1692 u32 value;
1693 int retval;
1694 armv4_5_common_t *armv4_5 = target->arch_info;
1695 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1696 enum armv4_5_mode reg_mode = ((armv4_5_core_reg_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode;
1697
1698 if ((num < 0) || (num > 16))
1699 return ERROR_INVALID_ARGUMENTS;
1700
1701 if ((mode != ARMV4_5_MODE_ANY)
1702 && (mode != armv4_5->core_mode)
1703 && (reg_mode != ARMV4_5_MODE_ANY))
1704 {
1705 u32 tmp_cpsr;
1706
1707 /* change processor mode (mask T bit) */
1708 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1709 tmp_cpsr |= mode;
1710 tmp_cpsr &= ~0x20;
1711 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1712 }
1713
1714 if ((num >= 0) && (num <= 15))
1715 {
1716 /* read a normal core register */
1717 reg_p[num] = &value;
1718
1719 arm7_9->read_core_regs(target, 1 << num, reg_p);
1720 }
1721 else
1722 {
1723 /* read a program status register
1724 * if the register mode is MODE_ANY, we read the cpsr, otherwise a spsr
1725 */
1726 armv4_5_core_reg_t *arch_info = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info;
1727 int spsr = (arch_info->mode == ARMV4_5_MODE_ANY) ? 0 : 1;
1728
1729 arm7_9->read_xpsr(target, &value, spsr);
1730 }
1731
1732 if ((retval = jtag_execute_queue()) != ERROR_OK)
1733 {
1734 ERROR("JTAG failure");
1735 exit(-1);
1736 }
1737
1738 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
1739 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
1740 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).value, 0, 32, value);
1741
1742 if ((mode != ARMV4_5_MODE_ANY)
1743 && (mode != armv4_5->core_mode)
1744 && (reg_mode != ARMV4_5_MODE_ANY)) {
1745 /* restore processor mode (mask T bit) */
1746 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
1747 }
1748
1749 return ERROR_OK;
1750
1751 }
1752
1753 int arm7_9_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mode, u32 value)
1754 {
1755 u32 reg[16];
1756 armv4_5_common_t *armv4_5 = target->arch_info;
1757 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1758 enum armv4_5_mode reg_mode = ((armv4_5_core_reg_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode;
1759
1760 if ((num < 0) || (num > 16))
1761 return ERROR_INVALID_ARGUMENTS;
1762
1763 if ((mode != ARMV4_5_MODE_ANY)
1764 && (mode != armv4_5->core_mode)
1765 && (reg_mode != ARMV4_5_MODE_ANY)) {
1766 u32 tmp_cpsr;
1767
1768 /* change processor mode (mask T bit) */
1769 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1770 tmp_cpsr |= mode;
1771 tmp_cpsr &= ~0x20;
1772 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1773 }
1774
1775 if ((num >= 0) && (num <= 15))
1776 {
1777 /* write a normal core register */
1778 reg[num] = value;
1779
1780 arm7_9->write_core_regs(target, 1 << num, reg);
1781 }
1782 else
1783 {
1784 /* write a program status register
1785 * if the register mode is MODE_ANY, we write the cpsr, otherwise a spsr
1786 */
1787 armv4_5_core_reg_t *arch_info = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info;
1788 int spsr = (arch_info->mode == ARMV4_5_MODE_ANY) ? 0 : 1;
1789
1790 /* if we're writing the CPSR, mask the T bit */
1791 if (!spsr)
1792 value &= ~0x20;
1793
1794 arm7_9->write_xpsr(target, value, spsr);
1795 }
1796
1797 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
1798 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
1799
1800 if ((mode != ARMV4_5_MODE_ANY)
1801 && (mode != armv4_5->core_mode)
1802 && (reg_mode != ARMV4_5_MODE_ANY)) {
1803 /* restore processor mode (mask T bit) */
1804 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
1805 }
1806
1807 return jtag_execute_queue();
1808 }
1809
1810 int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1811 {
1812 armv4_5_common_t *armv4_5 = target->arch_info;
1813 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1814
1815 u32 reg[16];
1816 int num_accesses = 0;
1817 int thisrun_accesses;
1818 int i;
1819 u32 cpsr;
1820 int retval;
1821 int last_reg = 0;
1822
1823 DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
1824
1825 if (target->state != TARGET_HALTED)
1826 {
1827 WARNING("target not halted");
1828 return ERROR_TARGET_NOT_HALTED;
1829 }
1830
1831 /* sanitize arguments */
1832 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
1833 return ERROR_INVALID_ARGUMENTS;
1834
1835 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1836 return ERROR_TARGET_UNALIGNED_ACCESS;
1837
1838 /* load the base register with the address of the first word */
1839 reg[0] = address;
1840 arm7_9->write_core_regs(target, 0x1, reg);
1841
1842 switch (size)
1843 {
1844 case 4:
1845 while (num_accesses < count)
1846 {
1847 u32 reg_list;
1848 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1849 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1850
1851 if (last_reg <= thisrun_accesses)
1852 last_reg = thisrun_accesses;
1853
1854 arm7_9->load_word_regs(target, reg_list);
1855
1856 /* fast memory reads are only safe when the target is running
1857 * from a sufficiently high clock (32 kHz is usually too slow)
1858 */
1859 if (arm7_9->fast_memory_access)
1860 arm7_9_execute_fast_sys_speed(target);
1861 else
1862 arm7_9_execute_sys_speed(target);
1863
1864 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 4);
1865
1866 /* advance buffer, count number of accesses */
1867 buffer += thisrun_accesses * 4;
1868 num_accesses += thisrun_accesses;
1869 }
1870 break;
1871 case 2:
1872 while (num_accesses < count)
1873 {
1874 u32 reg_list;
1875 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1876 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1877
1878 for (i = 1; i <= thisrun_accesses; i++)
1879 {
1880 if (i > last_reg)
1881 last_reg = i;
1882 arm7_9->load_hword_reg(target, i);
1883 /* fast memory reads are only safe when the target is running
1884 * from a sufficiently high clock (32 kHz is usually too slow)
1885 */
1886 if (arm7_9->fast_memory_access)
1887 arm7_9_execute_fast_sys_speed(target);
1888 else
1889 arm7_9_execute_sys_speed(target);
1890 }
1891
1892 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 2);
1893
1894 /* advance buffer, count number of accesses */
1895 buffer += thisrun_accesses * 2;
1896 num_accesses += thisrun_accesses;
1897 }
1898 break;
1899 case 1:
1900 while (num_accesses < count)
1901 {
1902 u32 reg_list;
1903 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1904 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1905
1906 for (i = 1; i <= thisrun_accesses; i++)
1907 {
1908 if (i > last_reg)
1909 last_reg = i;
1910 arm7_9->load_byte_reg(target, i);
1911 /* fast memory reads are only safe when the target is running
1912 * from a sufficiently high clock (32 kHz is usually too slow)
1913 */
1914 if (arm7_9->fast_memory_access)
1915 arm7_9_execute_fast_sys_speed(target);
1916 else
1917 arm7_9_execute_sys_speed(target);
1918 }
1919
1920 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 1);
1921
1922 /* advance buffer, count number of accesses */
1923 buffer += thisrun_accesses * 1;
1924 num_accesses += thisrun_accesses;
1925 }
1926 break;
1927 default:
1928 ERROR("BUG: we shouldn't get here");
1929 exit(-1);
1930 break;
1931 }
1932
1933 for (i=0; i<=last_reg; i++)
1934 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid;
1935
1936 arm7_9->read_xpsr(target, &cpsr, 0);
1937 if ((retval = jtag_execute_queue()) != ERROR_OK)
1938 {
1939 ERROR("JTAG error while reading cpsr");
1940 return ERROR_TARGET_DATA_ABORT;
1941 }
1942
1943 if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))
1944 {
1945 WARNING("memory read caused data abort (address: 0x%8.8x, size: 0x%x, count: 0x%x)", address, size, count);
1946
1947 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
1948
1949 return ERROR_TARGET_DATA_ABORT;
1950 }
1951
1952 return ERROR_OK;
1953 }
1954
1955 int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1956 {
1957 armv4_5_common_t *armv4_5 = target->arch_info;
1958 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1959 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1960
1961 u32 reg[16];
1962 int num_accesses = 0;
1963 int thisrun_accesses;
1964 int i;
1965 u32 cpsr;
1966 int retval;
1967 int last_reg = 0;
1968
1969 #ifdef _DEBUG_ARM7_9_
1970 DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
1971 #endif
1972
1973 if (target->state != TARGET_HALTED)
1974 {
1975 WARNING("target not halted");
1976 return ERROR_TARGET_NOT_HALTED;
1977 }
1978
1979 /* sanitize arguments */
1980 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
1981 return ERROR_INVALID_ARGUMENTS;
1982
1983 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1984 return ERROR_TARGET_UNALIGNED_ACCESS;
1985
1986 /* load the base register with the address of the first word */
1987 reg[0] = address;
1988 arm7_9->write_core_regs(target, 0x1, reg);
1989
1990 /* Clear DBGACK, to make sure memory fetches work as expected */
1991 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
1992 embeddedice_store_reg(dbg_ctrl);
1993
1994 switch (size)
1995 {
1996 case 4:
1997 while (num_accesses < count)
1998 {
1999 u32 reg_list;
2000 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
2001 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2002
2003 for (i = 1; i <= thisrun_accesses; i++)
2004 {
2005 if (i > last_reg)
2006 last_reg = i;
2007 reg[i] = target_buffer_get_u32(target, buffer);
2008 buffer += 4;
2009 }
2010
2011 arm7_9->write_core_regs(target, reg_list, reg);
2012
2013 arm7_9->store_word_regs(target, reg_list);
2014
2015 /* fast memory writes are only safe when the target is running
2016 * from a sufficiently high clock (32 kHz is usually too slow)
2017 */
2018 if (arm7_9->fast_memory_access)
2019 arm7_9_execute_fast_sys_speed(target);
2020 else
2021 arm7_9_execute_sys_speed(target);
2022
2023 num_accesses += thisrun_accesses;
2024 }
2025 break;
2026 case 2:
2027 while (num_accesses < count)
2028 {
2029 u32 reg_list;
2030 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
2031 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2032
2033 for (i = 1; i <= thisrun_accesses; i++)
2034 {
2035 if (i > last_reg)
2036 last_reg = i;
2037 reg[i] = target_buffer_get_u16(target, buffer) & 0xffff;
2038 buffer += 2;
2039 }
2040
2041 arm7_9->write_core_regs(target, reg_list, reg);
2042
2043 for (i = 1; i <= thisrun_accesses; i++)
2044 {
2045 arm7_9->store_hword_reg(target, i);
2046
2047 /* fast memory writes are only safe when the target is running
2048 * from a sufficiently high clock (32 kHz is usually too slow)
2049 */
2050 if (arm7_9->fast_memory_access)
2051 arm7_9_execute_fast_sys_speed(target);
2052 else
2053 arm7_9_execute_sys_speed(target);
2054 }
2055
2056 num_accesses += thisrun_accesses;
2057 }
2058 break;
2059 case 1:
2060 while (num_accesses < count)
2061 {
2062 u32 reg_list;
2063 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
2064 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2065
2066 for (i = 1; i <= thisrun_accesses; i++)
2067 {
2068 if (i > last_reg)
2069 last_reg = i;
2070 reg[i] = *buffer++ & 0xff;
2071 }
2072
2073 arm7_9->write_core_regs(target, reg_list, reg);
2074
2075 for (i = 1; i <= thisrun_accesses; i++)
2076 {
2077 arm7_9->store_byte_reg(target, i);
2078 /* fast memory writes are only safe when the target is running
2079 * from a sufficiently high clock (32 kHz is usually too slow)
2080 */
2081 if (arm7_9->fast_memory_access)
2082 arm7_9_execute_fast_sys_speed(target);
2083 else
2084 arm7_9_execute_sys_speed(target);
2085 }
2086
2087 num_accesses += thisrun_accesses;
2088 }
2089 break;
2090 default:
2091 ERROR("BUG: we shouldn't get here");
2092 exit(-1);
2093 break;
2094 }
2095
2096 /* Re-Set DBGACK */
2097 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
2098 embeddedice_store_reg(dbg_ctrl);
2099
2100 for (i=0; i<=last_reg; i++)
2101 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid;
2102
2103 arm7_9->read_xpsr(target, &cpsr, 0);
2104 if ((retval = jtag_execute_queue()) != ERROR_OK)
2105 {
2106 ERROR("JTAG error while reading cpsr");
2107 return ERROR_TARGET_DATA_ABORT;
2108 }
2109
2110 if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))
2111 {
2112 WARNING("memory write caused data abort (address: 0x%8.8x, size: 0x%x, count: 0x%x)", address, size, count);
2113
2114 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
2115
2116 return ERROR_TARGET_DATA_ABORT;
2117 }
2118
2119 return ERROR_OK;
2120 }
2121
2122 int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer)
2123 {
2124 armv4_5_common_t *armv4_5 = target->arch_info;
2125 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
2126 enum armv4_5_state core_state = armv4_5->core_state;
2127 u32 r0 = buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32);
2128 u32 r1 = buf_get_u32(armv4_5->core_cache->reg_list[1].value, 0, 32);
2129 u32 pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
2130 int i;
2131
2132 u32 dcc_code[] =
2133 {
2134 /* MRC TST BNE MRC STR B */
2135 0xee101e10, 0xe3110001, 0x0afffffc, 0xee111e10, 0xe4801004, 0xeafffff9
2136 };
2137
2138 if (!arm7_9->dcc_downloads)
2139 return target->type->write_memory(target, address, 4, count, buffer);
2140
2141 /* regrab previously allocated working_area, or allocate a new one */
2142 if (!arm7_9->dcc_working_area)
2143 {
2144 u8 dcc_code_buf[6 * 4];
2145
2146 /* make sure we have a working area */
2147 if (target_alloc_working_area(target, 24, &arm7_9->dcc_working_area) != ERROR_OK)
2148 {
2149 INFO("no working area available, falling back to memory writes");
2150 return target->type->write_memory(target, address, 4, count, buffer);
2151 }
2152
2153 /* copy target instructions to target endianness */
2154 for (i = 0; i < 6; i++)
2155 {
2156 target_buffer_set_u32(target, dcc_code_buf + i*4, dcc_code[i]);
2157 }
2158
2159 /* write DCC code to working area */
2160 target->type->write_memory(target, arm7_9->dcc_working_area->address, 4, 6, dcc_code_buf);
2161 }
2162
2163 buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, address);
2164 armv4_5->core_cache->reg_list[0].valid = 1;
2165 armv4_5->core_cache->reg_list[0].dirty = 1;
2166 armv4_5->core_state = ARMV4_5_STATE_ARM;
2167
2168 arm7_9_resume(target, 0, arm7_9->dcc_working_area->address, 1, 1);
2169
2170 int little=target->endianness==TARGET_LITTLE_ENDIAN;
2171 if (count>2)
2172 {
2173 /* Handle first & last using standard embeddedice_write_reg and the middle ones w/the
2174 core function repeated.
2175 */
2176 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
2177 buffer+=4;
2178
2179 embeddedice_reg_t *ice_reg = arm7_9->eice_cache->reg_list[EICE_COMMS_DATA].arch_info;
2180 u8 reg_addr = ice_reg->addr & 0x1f;
2181 int chain_pos = ice_reg->jtag_info->chain_pos;
2182 /* we want the compiler to duplicate the code, which it does not
2183 * do automatically.
2184 */
2185 if (little)
2186 {
2187 for (i = 1; i < count - 1; i++)
2188 {
2189 embeddedice_write_reg_inner(chain_pos, reg_addr, fast_target_buffer_get_u32(buffer, little));
2190 buffer += 4;
2191 }
2192 } else
2193 {
2194 for (i = 1; i < count - 1; i++)
2195 {
2196 embeddedice_write_reg_inner(chain_pos, reg_addr, fast_target_buffer_get_u32(buffer, little));
2197 buffer += 4;
2198 }
2199 }
2200 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
2201 } else
2202 {
2203 for (i = 0; i < count; i++)
2204 {
2205 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
2206 buffer += 4;
2207 }
2208 }
2209
2210 target->type->halt(target);
2211
2212 for (i=0; i<100; i++)
2213 {
2214 target->type->poll(target);
2215 if (target->state == TARGET_HALTED)
2216 break;
2217 usleep(1000); /* sleep 1ms */
2218 }
2219 if (i == 100)
2220 {
2221 ERROR("bulk write timed out, target not halted");
2222 return ERROR_TARGET_TIMEOUT;
2223 }
2224
2225 /* restore target state */
2226 buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, r0);
2227 armv4_5->core_cache->reg_list[0].valid = 1;
2228 armv4_5->core_cache->reg_list[0].dirty = 1;
2229 buf_set_u32(armv4_5->core_cache->reg_list[1].value, 0, 32, r1);
2230 armv4_5->core_cache->reg_list[1].valid = 1;
2231 armv4_5->core_cache->reg_list[1].dirty = 1;
2232 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, pc);
2233 armv4_5->core_cache->reg_list[15].valid = 1;
2234 armv4_5->core_cache->reg_list[15].dirty = 1;
2235 armv4_5->core_state = core_state;
2236
2237 return ERROR_OK;
2238 }
2239
2240 int arm7_9_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum)
2241 {
2242 working_area_t *crc_algorithm;
2243 armv4_5_algorithm_t armv4_5_info;
2244 reg_param_t reg_params[2];
2245 int retval;
2246
2247 u32 arm7_9_crc_code[] = {
2248 0xE1A02000, /* mov r2, r0 */
2249 0xE3E00000, /* mov r0, #0xffffffff */
2250 0xE1A03001, /* mov r3, r1 */
2251 0xE3A04000, /* mov r4, #0 */
2252 0xEA00000B, /* b ncomp */
2253 /* nbyte: */
2254 0xE7D21004, /* ldrb r1, [r2, r4] */
2255 0xE59F7030, /* ldr r7, CRC32XOR */
2256 0xE0200C01, /* eor r0, r0, r1, asl 24 */
2257 0xE3A05000, /* mov r5, #0 */
2258 /* loop: */
2259 0xE3500000, /* cmp r0, #0 */
2260 0xE1A06080, /* mov r6, r0, asl #1 */
2261 0xE2855001, /* add r5, r5, #1 */
2262 0xE1A00006, /* mov r0, r6 */
2263 0xB0260007, /* eorlt r0, r6, r7 */
2264 0xE3550008, /* cmp r5, #8 */
2265 0x1AFFFFF8, /* bne loop */
2266 0xE2844001, /* add r4, r4, #1 */
2267 /* ncomp: */
2268 0xE1540003, /* cmp r4, r3 */
2269 0x1AFFFFF1, /* bne nbyte */
2270 /* end: */
2271 0xEAFFFFFE, /* b end */
2272 0x04C11DB7 /* CRC32XOR: .word 0x04C11DB7 */
2273 };
2274
2275 int i;
2276
2277 if (target_alloc_working_area(target, sizeof(arm7_9_crc_code), &crc_algorithm) != ERROR_OK)
2278 {
2279 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
2280 }
2281
2282 /* convert flash writing code into a buffer in target endianness */
2283 for (i = 0; i < (sizeof(arm7_9_crc_code)/sizeof(u32)); i++)
2284 target_write_u32(target, crc_algorithm->address + i*sizeof(u32), arm7_9_crc_code[i]);
2285
2286 armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
2287 armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
2288 armv4_5_info.core_state = ARMV4_5_STATE_ARM;
2289
2290 init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT);
2291 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
2292
2293 buf_set_u32(reg_params[0].value, 0, 32, address);
2294 buf_set_u32(reg_params[1].value, 0, 32, count);
2295
2296 if ((retval = target->type->run_algorithm(target, 0, NULL, 2, reg_params,
2297 crc_algorithm->address, crc_algorithm->address + (sizeof(arm7_9_crc_code) - 8), 20000, &armv4_5_info)) != ERROR_OK)
2298 {
2299 ERROR("error executing arm7_9 crc algorithm");
2300 destroy_reg_param(&reg_params[0]);
2301 destroy_reg_param(&reg_params[1]);
2302 target_free_working_area(target, crc_algorithm);
2303 return retval;
2304 }
2305
2306 *checksum = buf_get_u32(reg_params[0].value, 0, 32);
2307
2308 destroy_reg_param(&reg_params[0]);
2309 destroy_reg_param(&reg_params[1]);
2310
2311 target_free_working_area(target, crc_algorithm);
2312
2313 return ERROR_OK;
2314 }
2315
2316 int arm7_9_register_commands(struct command_context_s *cmd_ctx)
2317 {
2318 command_t *arm7_9_cmd;
2319
2320 arm7_9_cmd = register_command(cmd_ctx, NULL, "arm7_9", NULL, COMMAND_ANY, "arm7/9 specific commands");
2321
2322 register_command(cmd_ctx, arm7_9_cmd, "write_xpsr", handle_arm7_9_write_xpsr_command, COMMAND_EXEC, "write program status register <value> <not cpsr|spsr>");
2323 register_command(cmd_ctx, arm7_9_cmd, "write_xpsr_im8", handle_arm7_9_write_xpsr_im8_command, COMMAND_EXEC, "write program status register <8bit immediate> <rotate> <not cpsr|spsr>");
2324
2325 register_command(cmd_ctx, arm7_9_cmd, "write_core_reg", handle_arm7_9_write_core_reg_command, COMMAND_EXEC, "write core register <num> <mode> <value>");
2326
2327 register_command(cmd_ctx, arm7_9_cmd, "sw_bkpts", handle_arm7_9_sw_bkpts_command, COMMAND_EXEC, "support for software breakpoints <enable|disable>");
2328 register_command(cmd_ctx, arm7_9_cmd, "force_hw_bkpts", handle_arm7_9_force_hw_bkpts_command, COMMAND_EXEC, "use hardware breakpoints for all breakpoints (disables sw breakpoint support) <enable|disable>");
2329 register_command(cmd_ctx, arm7_9_cmd, "dbgrq", handle_arm7_9_dbgrq_command,
2330 COMMAND_ANY, "use EmbeddedICE dbgrq instead of breakpoint for target halt requests <enable|disable>");
2331 register_command(cmd_ctx, arm7_9_cmd, "fast_writes", handle_arm7_9_fast_memory_access_command,
2332 COMMAND_ANY, "(deprecated, see: arm7_9 fast_memory_access)");
2333 register_command(cmd_ctx, arm7_9_cmd, "fast_memory_access", handle_arm7_9_fast_memory_access_command,
2334 COMMAND_ANY, "use fast memory accesses instead of slower but potentially unsafe slow accesses <enable|disable>");
2335 register_command(cmd_ctx, arm7_9_cmd, "dcc_downloads", handle_arm7_9_dcc_downloads_command,
2336 COMMAND_ANY, "use DCC downloads for larger memory writes <enable|disable>");
2337
2338 armv4_5_register_commands(cmd_ctx);
2339
2340 etm_register_commands(cmd_ctx);
2341
2342 return ERROR_OK;
2343 }
2344
2345 int handle_arm7_9_write_xpsr_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2346 {
2347 u32 value;
2348 int spsr;
2349 int retval;
2350 target_t *target = get_current_target(cmd_ctx);
2351 armv4_5_common_t *armv4_5;
2352 arm7_9_common_t *arm7_9;
2353
2354 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2355 {
2356 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2357 return ERROR_OK;
2358 }
2359
2360 if (target->state != TARGET_HALTED)
2361 {
2362 command_print(cmd_ctx, "can't write registers while running");
2363 return ERROR_OK;
2364 }
2365
2366 if (argc < 2)
2367 {
2368 command_print(cmd_ctx, "usage: write_xpsr <value> <not cpsr|spsr>");
2369 return ERROR_OK;
2370 }
2371
2372 value = strtoul(args[0], NULL, 0);
2373 spsr = strtol(args[1], NULL, 0);
2374
2375 /* if we're writing the CPSR, mask the T bit */
2376 if (!spsr)
2377 value &= ~0x20;
2378
2379 arm7_9->write_xpsr(target, value, spsr);
2380 if ((retval = jtag_execute_queue()) != ERROR_OK)
2381 {
2382 ERROR("JTAG error while writing to xpsr");
2383 return retval;
2384 }
2385
2386 return ERROR_OK;
2387 }
2388
2389 int handle_arm7_9_write_xpsr_im8_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2390 {
2391 u32 value;
2392 int rotate;
2393 int spsr;
2394 int retval;
2395 target_t *target = get_current_target(cmd_ctx);
2396 armv4_5_common_t *armv4_5;
2397 arm7_9_common_t *arm7_9;
2398
2399 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2400 {
2401 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2402 return ERROR_OK;
2403 }
2404
2405 if (target->state != TARGET_HALTED)
2406 {
2407 command_print(cmd_ctx, "can't write registers while running");
2408 return ERROR_OK;
2409 }
2410
2411 if (argc < 3)
2412 {
2413 command_print(cmd_ctx, "usage: write_xpsr_im8 <im8> <rotate> <not cpsr|spsr>");
2414 return ERROR_OK;
2415 }
2416
2417 value = strtoul(args[0], NULL, 0);
2418 rotate = strtol(args[1], NULL, 0);
2419 spsr = strtol(args[2], NULL, 0);
2420
2421 arm7_9->write_xpsr_im8(target, value, rotate, spsr);
2422 if ((retval = jtag_execute_queue()) != ERROR_OK)
2423 {
2424 ERROR("JTAG error while writing 8-bit immediate to xpsr");
2425 return retval;
2426 }
2427
2428 return ERROR_OK;
2429 }
2430
2431 int handle_arm7_9_write_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2432 {
2433 u32 value;
2434 u32 mode;
2435 int num;
2436 target_t *target = get_current_target(cmd_ctx);
2437 armv4_5_common_t *armv4_5;
2438 arm7_9_common_t *arm7_9;
2439
2440 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2441 {
2442 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2443 return ERROR_OK;
2444 }
2445
2446 if (target->state != TARGET_HALTED)
2447 {
2448 command_print(cmd_ctx, "can't write registers while running");
2449 return ERROR_OK;
2450 }
2451
2452 if (argc < 3)
2453 {
2454 command_print(cmd_ctx, "usage: write_core_reg <num> <mode> <value>");
2455 return ERROR_OK;
2456 }
2457
2458 num = strtol(args[0], NULL, 0);
2459 mode = strtoul(args[1], NULL, 0);
2460 value = strtoul(args[2], NULL, 0);
2461
2462 arm7_9_write_core_reg(target, num, mode, value);
2463
2464 return ERROR_OK;
2465 }
2466
2467 int handle_arm7_9_sw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2468 {
2469 target_t *target = get_current_target(cmd_ctx);
2470 armv4_5_common_t *armv4_5;
2471 arm7_9_common_t *arm7_9;
2472
2473 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2474 {
2475 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2476 return ERROR_OK;
2477 }
2478
2479 if (argc == 0)
2480 {
2481 command_print(cmd_ctx, "software breakpoints %s", (arm7_9->sw_bkpts_enabled) ? "enabled" : "disabled");
2482 return ERROR_OK;
2483 }
2484
2485 if (strcmp("enable", args[0]) == 0)
2486 {
2487 if (arm7_9->sw_bkpts_use_wp)
2488 {
2489 arm7_9_enable_sw_bkpts(target);
2490 }
2491 else
2492 {
2493 arm7_9->sw_bkpts_enabled = 1;
2494 }
2495 }
2496 else if (strcmp("disable", args[0]) == 0)
2497 {
2498 if (arm7_9->sw_bkpts_use_wp)
2499 {
2500 arm7_9_disable_sw_bkpts(target);
2501 }
2502 else
2503 {
2504 arm7_9->sw_bkpts_enabled = 0;
2505 }
2506 }
2507 else
2508 {
2509 command_print(cmd_ctx, "usage: arm7_9 sw_bkpts <enable|disable>");
2510 }
2511
2512 command_print(cmd_ctx, "software breakpoints %s", (arm7_9->sw_bkpts_enabled) ? "enabled" : "disabled");
2513
2514 return ERROR_OK;
2515 }
2516
2517 int handle_arm7_9_force_hw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2518 {
2519 target_t *target = get_current_target(cmd_ctx);
2520 armv4_5_common_t *armv4_5;
2521 arm7_9_common_t *arm7_9;
2522
2523 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2524 {
2525 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2526 return ERROR_OK;
2527 }
2528
2529 if ((argc >= 1) && (strcmp("enable", args[0]) == 0))
2530 {
2531 arm7_9->force_hw_bkpts = 1;
2532 if (arm7_9->sw_bkpts_use_wp)
2533 {
2534 arm7_9_disable_sw_bkpts(target);
2535 }
2536 }
2537 else if ((argc >= 1) && (strcmp("disable", args[0]) == 0))
2538 {
2539 arm7_9->force_hw_bkpts = 0;
2540 }
2541 else
2542 {
2543 command_print(cmd_ctx, "usage: arm7_9 force_hw_bkpts <enable|disable>");
2544 }
2545
2546 command_print(cmd_ctx, "force hardware breakpoints %s", (arm7_9->force_hw_bkpts) ? "enabled" : "disabled");
2547
2548 return ERROR_OK;
2549 }
2550
2551 int handle_arm7_9_dbgrq_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2552 {
2553 target_t *target = get_current_target(cmd_ctx);
2554 armv4_5_common_t *armv4_5;
2555 arm7_9_common_t *arm7_9;
2556
2557 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2558 {
2559 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2560 return ERROR_OK;
2561 }
2562
2563 if (argc > 0)
2564 {
2565 if (strcmp("enable", args[0]) == 0)
2566 {
2567 arm7_9->use_dbgrq = 1;
2568 }
2569 else if (strcmp("disable", args[0]) == 0)
2570 {
2571 arm7_9->use_dbgrq = 0;
2572 }
2573 else
2574 {
2575 command_print(cmd_ctx, "usage: arm7_9 dbgrq <enable|disable>");
2576 }
2577 }
2578
2579 command_print(cmd_ctx, "use of EmbeddedICE dbgrq instead of breakpoint for target halt %s", (arm7_9->use_dbgrq) ? "enabled" : "disabled");
2580
2581 return ERROR_OK;
2582 }
2583
2584 int handle_arm7_9_fast_memory_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2585 {
2586 target_t *target = get_current_target(cmd_ctx);
2587 armv4_5_common_t *armv4_5;
2588 arm7_9_common_t *arm7_9;
2589
2590 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2591 {
2592 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2593 return ERROR_OK;
2594 }
2595
2596 if (argc > 0)
2597 {
2598 if (strcmp("enable", args[0]) == 0)
2599 {
2600 arm7_9->fast_memory_access = 1;
2601 }
2602 else if (strcmp("disable", args[0]) == 0)
2603 {
2604 arm7_9->fast_memory_access = 0;
2605 }
2606 else
2607 {
2608 command_print(cmd_ctx, "usage: arm7_9 fast_memory_access <enable|disable>");
2609 }
2610 }
2611
2612 command_print(cmd_ctx, "fast memory access is %s", (arm7_9->fast_memory_access) ? "enabled" : "disabled");
2613
2614 return ERROR_OK;
2615 }
2616
2617 int handle_arm7_9_dcc_downloads_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2618 {
2619 target_t *target = get_current_target(cmd_ctx);
2620 armv4_5_common_t *armv4_5;
2621 arm7_9_common_t *arm7_9;
2622
2623 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2624 {
2625 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2626 return ERROR_OK;
2627 }
2628
2629 if (argc > 0)
2630 {
2631 if (strcmp("enable", args[0]) == 0)
2632 {
2633 arm7_9->dcc_downloads = 1;
2634 }
2635 else if (strcmp("disable", args[0]) == 0)
2636 {
2637 arm7_9->dcc_downloads = 0;
2638 }
2639 else
2640 {
2641 command_print(cmd_ctx, "usage: arm7_9 dcc_downloads <enable|disable>");
2642 }
2643 }
2644
2645 command_print(cmd_ctx, "dcc downloads are %s", (arm7_9->dcc_downloads) ? "enabled" : "disabled");
2646
2647 return ERROR_OK;
2648 }
2649
2650 int arm7_9_init_arch_info(target_t *target, arm7_9_common_t *arm7_9)
2651 {
2652 armv4_5_common_t *armv4_5 = &arm7_9->armv4_5_common;
2653
2654 arm7_9->common_magic = ARM7_9_COMMON_MAGIC;
2655
2656 arm_jtag_setup_connection(&arm7_9->jtag_info);
2657 arm7_9->wp_available = 2;
2658 arm7_9->wp0_used = 0;
2659 arm7_9->wp1_used = 0;
2660 arm7_9->force_hw_bkpts = 0;
2661 arm7_9->use_dbgrq = 0;
2662
2663 arm7_9->etm_ctx = NULL;
2664 arm7_9->has_single_step = 0;
2665 arm7_9->has_monitor_mode = 0;
2666 arm7_9->has_vector_catch = 0;
2667
2668 arm7_9->reinit_embeddedice = 0;
2669
2670 arm7_9->debug_entry_from_reset = 0;
2671
2672 arm7_9->dcc_working_area = NULL;
2673
2674 arm7_9->fast_memory_access = 0;
2675 arm7_9->dcc_downloads = 0;
2676
2677 jtag_register_event_callback(arm7_9_jtag_callback, target);
2678
2679 armv4_5->arch_info = arm7_9;
2680 armv4_5->read_core_reg = arm7_9_read_core_reg;
2681 armv4_5->write_core_reg = arm7_9_write_core_reg;
2682 armv4_5->full_context = arm7_9_full_context;
2683
2684 armv4_5_init_arch_info(target, armv4_5);
2685
2686 target_register_timer_callback(arm7_9_handle_target_request, 1, 1, target);
2687
2688 return ERROR_OK;
2689 }