src/target/arm720t.c

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2009 by Øyvind Harboe                                   *
   6  *   oyvind.harboe@zylin.com                                               *
   7  *                                                                         *
   8  *   This program is free software; you can redistribute it and/or modify  *
   9  *   it under the terms of the GNU General Public License as published by  *
  10  *   the Free Software Foundation; either version 2 of the License, or     *
  11  *   (at your option) any later version.                                   *
  12  *                                                                         *
  13  *   This program is distributed in the hope that it will be useful,       *
  14  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  15  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  16  *   GNU General Public License for more details.                          *
  17  *                                                                         *
  18  *   You should have received a copy of the GNU General Public License     *
  19  *   along with this program; if not, write to the                         *
  20  *   Free Software Foundation, Inc.,                                       *
  21  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  22  ***************************************************************************/
  23 #ifdef HAVE_CONFIG_H
  24 #include "config.h"
  25 #endif
  26
  27 #include "arm720t.h"
  28 #include <helper/time_support.h>
  29 #include "target_type.h"
  30 #include "register.h"
  31 #include "arm_opcodes.h"
  32
  33
  34 /*
  35  * ARM720 is an ARM7TDMI-S with MMU and ETM7.  For information, see
  36  * ARM DDI 0229C especially Chapter 9 about debug support.
  37  */
  38
  39 #if 0
  40 #define _DEBUG_INSTRUCTION_EXECUTION_
  41 #endif
  42
  43 static int arm720t_scan_cp15(struct target *target,
  44                 uint32_t out, uint32_t *in, int instruction, int clock)
  45 {
  46         int retval;
  47         struct arm720t_common *arm720t = target_to_arm720(target);
  48         struct arm_jtag *jtag_info;
  49         struct scan_field fields[2];
  50         uint8_t out_buf[4];
  51         uint8_t instruction_buf = instruction;
  52
  53         jtag_info = &arm720t->arm7_9_common.jtag_info;
  54
  55         buf_set_u32(out_buf, 0, 32, flip_u32(out, 32));
  56
  57         jtag_set_end_state(TAP_DRPAUSE);
  58         if ((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
  59         {
  60                 return retval;
  61         }
  62         if ((retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL)) != ERROR_OK)
  63         {
  64                 return retval;
  65         }
  66
  67         fields[0].tap = jtag_info->tap;
  68         fields[0].num_bits = 1;
  69         fields[0].out_value = &instruction_buf;
  70         fields[0].in_value = NULL;
  71
  72         fields[1].tap = jtag_info->tap;
  73         fields[1].num_bits = 32;
  74         fields[1].out_value = out_buf;
  75         fields[1].in_value = NULL;
  76
  77         if (in)
  78         {
  79                 fields[1].in_value = (uint8_t *)in;
  80                 jtag_add_dr_scan(2, fields, jtag_get_end_state());
  81                 jtag_add_callback(arm7flip32, (jtag_callback_data_t)in);
  82         } else
  83         {
  84                 jtag_add_dr_scan(2, fields, jtag_get_end_state());
  85         }
  86
  87         if (clock)
  88                 jtag_add_runtest(0, jtag_get_end_state());
  89
  90 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
  91         if ((retval = jtag_execute_queue()) != ERROR_OK)
  92         {
  93                 return retval;
  94         }
  95
  96         if (in)
  97                 LOG_DEBUG("out: %8.8x, in: %8.8x, instruction: %i, clock: %i", out, *in, instruction, clock);
  98         else
  99                 LOG_DEBUG("out: %8.8x, instruction: %i, clock: %i", out, instruction, clock);
 100 #else
 101                 LOG_DEBUG("out: %8.8" PRIx32 ", instruction: %i, clock: %i", out, instruction, clock);
 102 #endif
 103
 104         return ERROR_OK;
 105 }
 106
 107 static int arm720t_read_cp15(struct target *target, uint32_t opcode, uint32_t *value)
 108 {
 109         /* fetch CP15 opcode */
 110         arm720t_scan_cp15(target, opcode, NULL, 1, 1);
 111         /* "DECODE" stage */
 112         arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 1);
 113         /* "EXECUTE" stage (1) */
 114         arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 0);
 115         arm720t_scan_cp15(target, 0x0, NULL, 0, 1);
 116         /* "EXECUTE" stage (2) */
 117         arm720t_scan_cp15(target, 0x0, NULL, 0, 1);
 118         /* "EXECUTE" stage (3), CDATA is read */
 119         arm720t_scan_cp15(target, ARMV4_5_NOP, value, 1, 1);
 120
 121         return ERROR_OK;
 122 }
 123
 124 static int arm720t_write_cp15(struct target *target, uint32_t opcode, uint32_t value)
 125 {
 126         /* fetch CP15 opcode */
 127         arm720t_scan_cp15(target, opcode, NULL, 1, 1);
 128         /* "DECODE" stage */
 129         arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 1);
 130         /* "EXECUTE" stage (1) */
 131         arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 0);
 132         arm720t_scan_cp15(target, 0x0, NULL, 0, 1);
 133         /* "EXECUTE" stage (2) */
 134         arm720t_scan_cp15(target, value, NULL, 0, 1);
 135         arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 1);
 136
 137         return ERROR_OK;
 138 }
 139
 140 static uint32_t arm720t_get_ttb(struct target *target)
 141 {
 142         uint32_t ttb = 0x0;
 143
 144         arm720t_read_cp15(target, 0xee120f10, &ttb);
 145         jtag_execute_queue();
 146
 147         ttb &= 0xffffc000;
 148
 149         return ttb;
 150 }
 151
 152 static void arm720t_disable_mmu_caches(struct target *target,
 153                 int mmu, int d_u_cache, int i_cache)
 154 {
 155         uint32_t cp15_control;
 156
 157         /* read cp15 control register */
 158         arm720t_read_cp15(target, 0xee110f10, &cp15_control);
 159         jtag_execute_queue();
 160
 161         if (mmu)
 162                 cp15_control &= ~0x1U;
 163
 164         if (d_u_cache || i_cache)
 165                 cp15_control &= ~0x4U;
 166
 167         arm720t_write_cp15(target, 0xee010f10, cp15_control);
 168 }
 169
 170 static void arm720t_enable_mmu_caches(struct target *target,
 171                 int mmu, int d_u_cache, int i_cache)
 172 {
 173         uint32_t cp15_control;
 174
 175         /* read cp15 control register */
 176         arm720t_read_cp15(target, 0xee110f10, &cp15_control);
 177         jtag_execute_queue();
 178
 179         if (mmu)
 180                 cp15_control |= 0x1U;
 181
 182         if (d_u_cache || i_cache)
 183                 cp15_control |= 0x4U;
 184
 185         arm720t_write_cp15(target, 0xee010f10, cp15_control);
 186 }
 187
 188 static void arm720t_post_debug_entry(struct target *target)
 189 {
 190         struct arm720t_common *arm720t = target_to_arm720(target);
 191
 192         /* examine cp15 control reg */
 193         arm720t_read_cp15(target, 0xee110f10, &arm720t->cp15_control_reg);
 194         jtag_execute_queue();
 195         LOG_DEBUG("cp15_control_reg: %8.8" PRIx32 "", arm720t->cp15_control_reg);
 196
 197         arm720t->armv4_5_mmu.mmu_enabled = (arm720t->cp15_control_reg & 0x1U) ? 1 : 0;
 198         arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm720t->cp15_control_reg & 0x4U) ? 1 : 0;
 199         arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
 200
 201         /* save i/d fault status and address register */
 202         arm720t_read_cp15(target, 0xee150f10, &arm720t->fsr_reg);
 203         arm720t_read_cp15(target, 0xee160f10, &arm720t->far_reg);
 204         jtag_execute_queue();
 205 }
 206
 207 static void arm720t_pre_restore_context(struct target *target)
 208 {
 209         struct arm720t_common *arm720t = target_to_arm720(target);
 210
 211         /* restore i/d fault status and address register */
 212         arm720t_write_cp15(target, 0xee050f10, arm720t->fsr_reg);
 213         arm720t_write_cp15(target, 0xee060f10, arm720t->far_reg);
 214 }
 215
 216 static int arm720t_verify_pointer(struct command_context *cmd_ctx,
 217                 struct arm720t_common *arm720t)
 218 {
 219         if (arm720t->common_magic != ARM720T_COMMON_MAGIC) {
 220                 command_print(cmd_ctx, "target is not an ARM720");
 221                 return ERROR_TARGET_INVALID;
 222         }
 223         return ERROR_OK;
 224 }
 225
 226 static int arm720t_arch_state(struct target *target)
 227 {
 228         struct arm720t_common *arm720t = target_to_arm720(target);
 229         struct arm *armv4_5;
 230
 231         static const char *state[] =
 232         {
 233                 "disabled", "enabled"
 234         };
 235
 236         armv4_5 = &arm720t->arm7_9_common.armv4_5_common;
 237
 238         arm_arch_state(target);
 239         LOG_USER("MMU: %s, Cache: %s",
 240                          state[arm720t->armv4_5_mmu.mmu_enabled],
 241                          state[arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled]);
 242
 243         return ERROR_OK;
 244 }
 245
 246 static int arm720_mmu(struct target *target, int *enabled)
 247 {
 248         if (target->state != TARGET_HALTED) {
 249                 LOG_ERROR("%s: target not halted", __func__);
 250                 return ERROR_TARGET_INVALID;
 251         }
 252
 253         *enabled = target_to_arm720(target)->armv4_5_mmu.mmu_enabled;
 254         return ERROR_OK;
 255 }
 256
 257 static int arm720_virt2phys(struct target *target,
 258                 uint32_t virtual, uint32_t *physical)
 259 {
 260         int type;
 261         uint32_t cb;
 262         int domain;
 263         uint32_t ap;
 264         struct arm720t_common *arm720t = target_to_arm720(target);
 265
 266         uint32_t ret = armv4_5_mmu_translate_va(target, &arm720t->armv4_5_mmu, virtual, &type, &cb, &domain, &ap);
 267         if (type == -1)
 268         {
 269                 return ret;
 270         }
 271         *physical = ret;
 272         return ERROR_OK;
 273 }
 274
 275 static int arm720t_read_memory(struct target *target,
 276                 uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
 277 {
 278         int retval;
 279         struct arm720t_common *arm720t = target_to_arm720(target);
 280
 281         /* disable cache, but leave MMU enabled */
 282         if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
 283                 arm720t_disable_mmu_caches(target, 0, 1, 0);
 284
 285         retval = arm7_9_read_memory(target, address, size, count, buffer);
 286
 287         if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
 288                 arm720t_enable_mmu_caches(target, 0, 1, 0);
 289
 290         return retval;
 291 }
 292
 293 static int arm720t_read_phys_memory(struct target *target,
 294                 uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
 295 {
 296         struct arm720t_common *arm720t = target_to_arm720(target);
 297
 298         return armv4_5_mmu_read_physical(target, &arm720t->armv4_5_mmu, address, size, count, buffer);
 299 }
 300
 301 static int arm720t_write_phys_memory(struct target *target,
 302                 uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
 303 {
 304         struct arm720t_common *arm720t = target_to_arm720(target);
 305
 306         return armv4_5_mmu_write_physical(target, &arm720t->armv4_5_mmu, address, size, count, buffer);
 307 }
 308
 309 static int arm720t_soft_reset_halt(struct target *target)
 310 {
 311         int retval = ERROR_OK;
 312         struct arm720t_common *arm720t = target_to_arm720(target);
 313         struct reg *dbg_stat = &arm720t->arm7_9_common
 314                         .eice_cache->reg_list[EICE_DBG_STAT];
 315         struct arm *armv4_5 = &arm720t->arm7_9_common
 316                         .armv4_5_common;
 317
 318         if ((retval = target_halt(target)) != ERROR_OK)
 319         {
 320                 return retval;
 321         }
 322
 323         long long then = timeval_ms();
 324         int timeout;
 325         while (!(timeout = ((timeval_ms()-then) > 1000)))
 326         {
 327                 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
 328                 {
 329                         embeddedice_read_reg(dbg_stat);
 330                         if ((retval = jtag_execute_queue()) != ERROR_OK)
 331                         {
 332                                 return retval;
 333                         }
 334                 } else
 335                 {
 336                         break;
 337                 }
 338                 if (debug_level >= 3)
 339                 {
 340                         alive_sleep(100);
 341                 } else
 342                 {
 343                         keep_alive();
 344                 }
 345         }
 346         if (timeout)
 347         {
 348                 LOG_ERROR("Failed to halt CPU after 1 sec");
 349                 return ERROR_TARGET_TIMEOUT;
 350         }
 351
 352         target->state = TARGET_HALTED;
 353
 354         /* SVC, ARM state, IRQ and FIQ disabled */
 355         uint32_t cpsr;
 356
 357         cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 32);
 358         cpsr &= ~0xff;
 359         cpsr |= 0xd3;
 360         arm_set_cpsr(armv4_5, cpsr);
 361         armv4_5->cpsr->dirty = 1;
 362
 363         /* start fetching from 0x0 */
 364         buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
 365         armv4_5->core_cache->reg_list[15].dirty = 1;
 366         armv4_5->core_cache->reg_list[15].valid = 1;
 367
 368         arm720t_disable_mmu_caches(target, 1, 1, 1);
 369         arm720t->armv4_5_mmu.mmu_enabled = 0;
 370         arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
 371         arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
 372
 373         if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
 374         {
 375                 return retval;
 376         }
 377
 378         return ERROR_OK;
 379 }
 380
 381 static int arm720t_init_target(struct command_context *cmd_ctx, struct target *target)
 382 {
 383         return arm7tdmi_init_target(cmd_ctx, target);
 384 }
 385
 386 /* FIXME remove forward decls */
 387 static int arm720t_mrc(struct target *target, int cpnum,
 388                 uint32_t op1, uint32_t op2,
 389                 uint32_t CRn, uint32_t CRm,
 390                 uint32_t *value);
 391 static int arm720t_mcr(struct target *target, int cpnum,
 392                 uint32_t op1, uint32_t op2,
 393                 uint32_t CRn, uint32_t CRm,
 394                 uint32_t value);
 395
 396 static int arm720t_init_arch_info(struct target *target,
 397                 struct arm720t_common *arm720t, struct jtag_tap *tap)
 398 {
 399         struct arm7_9_common *arm7_9 = &arm720t->arm7_9_common;
 400
 401         arm7_9->armv4_5_common.mrc = arm720t_mrc;
 402         arm7_9->armv4_5_common.mcr = arm720t_mcr;
 403
 404         arm7tdmi_init_arch_info(target, arm7_9, tap);
 405
 406         arm720t->common_magic = ARM720T_COMMON_MAGIC;
 407
 408         arm7_9->post_debug_entry = arm720t_post_debug_entry;
 409         arm7_9->pre_restore_context = arm720t_pre_restore_context;
 410
 411         arm720t->armv4_5_mmu.armv4_5_cache.ctype = -1;
 412         arm720t->armv4_5_mmu.get_ttb = arm720t_get_ttb;
 413         arm720t->armv4_5_mmu.read_memory = arm7_9_read_memory;
 414         arm720t->armv4_5_mmu.write_memory = arm7_9_write_memory;
 415         arm720t->armv4_5_mmu.disable_mmu_caches = arm720t_disable_mmu_caches;
 416         arm720t->armv4_5_mmu.enable_mmu_caches = arm720t_enable_mmu_caches;
 417         arm720t->armv4_5_mmu.has_tiny_pages = 0;
 418         arm720t->armv4_5_mmu.mmu_enabled = 0;
 419
 420         return ERROR_OK;
 421 }
 422
 423 static int arm720t_target_create(struct target *target, Jim_Interp *interp)
 424 {
 425         struct arm720t_common *arm720t = calloc(1, sizeof(*arm720t));
 426
 427         arm720t->arm7_9_common.armv4_5_common.is_armv4 = true;
 428         return arm720t_init_arch_info(target, arm720t, target->tap);
 429 }
 430
 431 COMMAND_HANDLER(arm720t_handle_cp15_command)
 432 {
 433         int retval;
 434         struct target *target = get_current_target(CMD_CTX);
 435         struct arm720t_common *arm720t = target_to_arm720(target);
 436         struct arm_jtag *jtag_info;
 437
 438         retval = arm720t_verify_pointer(CMD_CTX, arm720t);
 439         if (retval != ERROR_OK)
 440                 return retval;
 441
 442         jtag_info = &arm720t->arm7_9_common.jtag_info;
 443
 444         if (target->state != TARGET_HALTED)
 445         {
 446                 command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
 447                 return ERROR_OK;
 448         }
 449
 450         /* one or more argument, access a single register (write if second argument is given */
 451         if (CMD_ARGC >= 1)
 452         {
 453                 uint32_t opcode;
 454                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], opcode);
 455
 456                 if (CMD_ARGC == 1)
 457                 {
 458                         uint32_t value;
 459                         if ((retval = arm720t_read_cp15(target, opcode, &value)) != ERROR_OK)
 460                         {
 461                                 command_print(CMD_CTX, "couldn't access cp15 with opcode 0x%8.8" PRIx32 "", opcode);
 462                                 return ERROR_OK;
 463                         }
 464
 465                         if ((retval = jtag_execute_queue()) != ERROR_OK)
 466                         {
 467                                 return retval;
 468                         }
 469
 470                         command_print(CMD_CTX, "0x%8.8" PRIx32 ": 0x%8.8" PRIx32 "", opcode, value);
 471                 }
 472                 else if (CMD_ARGC == 2)
 473                 {
 474                         uint32_t value;
 475                         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
 476
 477                         if ((retval = arm720t_write_cp15(target, opcode, value)) != ERROR_OK)
 478                         {
 479                                 command_print(CMD_CTX, "couldn't access cp15 with opcode 0x%8.8" PRIx32 "", opcode);
 480                                 return ERROR_OK;
 481                         }
 482                         command_print(CMD_CTX, "0x%8.8" PRIx32 ": 0x%8.8" PRIx32 "", opcode, value);
 483                 }
 484         }
 485
 486         return ERROR_OK;
 487 }
 488
 489 static int arm720t_mrc(struct target *target, int cpnum,
 490                 uint32_t op1, uint32_t op2,
 491                 uint32_t CRn, uint32_t CRm,
 492                 uint32_t *value)
 493 {
 494         if (cpnum!=15)
 495         {
 496                 LOG_ERROR("Only cp15 is supported");
 497                 return ERROR_FAIL;
 498         }
 499
 500         /* read "to" r0 */
 501         return arm720t_read_cp15(target,
 502                         ARMV4_5_MRC(cpnum, op1, 0, CRn, CRm, op2),
 503                         value);
 504
 505 }
 506
 507 static int arm720t_mcr(struct target *target, int cpnum,
 508                 uint32_t op1, uint32_t op2,
 509                 uint32_t CRn, uint32_t CRm,
 510                 uint32_t value)
 511 {
 512         if (cpnum!=15)
 513         {
 514                 LOG_ERROR("Only cp15 is supported");
 515                 return ERROR_FAIL;
 516         }
 517
 518         /* write "from" r0 */
 519         return arm720t_write_cp15(target,
 520                         ARMV4_5_MCR(cpnum, op1, 0, CRn, CRm, op2),
 521                         value);
 522 }
 523
 524 static const struct command_registration arm720t_exec_command_handlers[] = {
 525         {
 526                 .name = "cp15",
 527                 .handler = arm720t_handle_cp15_command,
 528                 .mode = COMMAND_EXEC,
 529                 /* prefer using less error-prone "arm mcr" or "arm mrc" */
 530                 .help = "display/modify cp15 register using ARM opcode"
 531                         " (DEPRECATED)",
 532                 .usage = "instruction [value]",
 533         },
 534         COMMAND_REGISTRATION_DONE
 535 };
 536
 537 static const struct command_registration arm720t_command_handlers[] = {
 538         {
 539                 .chain = arm7_9_command_handlers,
 540         },
 541         {
 542                 .name = "arm720t",
 543                 .mode = COMMAND_ANY,
 544                 .help = "arm720t command group",
 545                 .chain = arm720t_exec_command_handlers,
 546         },
 547         COMMAND_REGISTRATION_DONE
 548 };
 549
 550 /** Holds methods for ARM720 targets. */
 551 struct target_type arm720t_target =
 552 {
 553         .name = "arm720t",
 554
 555         .poll = arm7_9_poll,
 556         .arch_state = arm720t_arch_state,
 557
 558         .halt = arm7_9_halt,
 559         .resume = arm7_9_resume,
 560         .step = arm7_9_step,
 561
 562         .assert_reset = arm7_9_assert_reset,
 563         .deassert_reset = arm7_9_deassert_reset,
 564         .soft_reset_halt = arm720t_soft_reset_halt,
 565
 566         .get_gdb_reg_list = arm_get_gdb_reg_list,
 567
 568         .read_memory = arm720t_read_memory,
 569         .write_memory = arm7_9_write_memory,
 570         .read_phys_memory = arm720t_read_phys_memory,
 571         .write_phys_memory = arm720t_write_phys_memory,
 572         .mmu = arm720_mmu,
 573         .virt2phys = arm720_virt2phys,
 574
 575         .bulk_write_memory = arm7_9_bulk_write_memory,
 576
 577         .checksum_memory = arm_checksum_memory,
 578         .blank_check_memory = arm_blank_check_memory,
 579
 580         .run_algorithm = armv4_5_run_algorithm,
 581
 582         .add_breakpoint = arm7_9_add_breakpoint,
 583         .remove_breakpoint = arm7_9_remove_breakpoint,
 584         .add_watchpoint = arm7_9_add_watchpoint,
 585         .remove_watchpoint = arm7_9_remove_watchpoint,
 586
 587         .commands = arm720t_command_handlers,
 588         .target_create = arm720t_target_create,
 589         .init_target = arm720t_init_target,
 590         .examine = arm7_9_examine,
 591         .check_reset = arm7_9_check_reset,
 592 };