src/target/arm720t.c

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2009 by Øyvind Harboe                                   *
   6  *   oyvind.harboe@zylin.com                                               *
   7  *                                                                         *
   8  *   This program is free software; you can redistribute it and/or modify  *
   9  *   it under the terms of the GNU General Public License as published by  *
  10  *   the Free Software Foundation; either version 2 of the License, or     *
  11  *   (at your option) any later version.                                   *
  12  *                                                                         *
  13  *   This program is distributed in the hope that it will be useful,       *
  14  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  15  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  16  *   GNU General Public License for more details.                          *
  17  *                                                                         *
  18  *   You should have received a copy of the GNU General Public License     *
  19  *   along with this program; if not, write to the                         *
  20  *   Free Software Foundation, Inc.,                                       *
  21  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  22  ***************************************************************************/
  23 #ifdef HAVE_CONFIG_H
  24 #include "config.h"
  25 #endif
  26
  27 #include "arm720t.h"
  28 #include <helper/time_support.h>
  29 #include "target_type.h"
  30 #include "register.h"
  31 #include "arm_opcodes.h"
  32
  33
  34 /*
  35  * ARM720 is an ARM7TDMI-S with MMU and ETM7.  For information, see
  36  * ARM DDI 0229C especially Chapter 9 about debug support.
  37  */
  38
  39 #if 0
  40 #define _DEBUG_INSTRUCTION_EXECUTION_
  41 #endif
  42
  43 static int arm720t_scan_cp15(struct target *target,
  44                 uint32_t out, uint32_t *in, int instruction, int clock_arg)
  45 {
  46         int retval;
  47         struct arm720t_common *arm720t = target_to_arm720(target);
  48         struct arm_jtag *jtag_info;
  49         struct scan_field fields[2];
  50         uint8_t out_buf[4];
  51         uint8_t instruction_buf = instruction;
  52
  53         jtag_info = &arm720t->arm7_9_common.jtag_info;
  54
  55         buf_set_u32(out_buf, 0, 32, flip_u32(out, 32));
  56
  57         if ((retval = arm_jtag_scann(jtag_info, 0xf, TAP_DRPAUSE)) != ERROR_OK)
  58         {
  59                 return retval;
  60         }
  61         if ((retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_DRPAUSE)) != ERROR_OK)
  62         {
  63                 return retval;
  64         }
  65
  66         fields[0].num_bits = 1;
  67         fields[0].out_value = &instruction_buf;
  68         fields[0].in_value = NULL;
  69
  70         fields[1].num_bits = 32;
  71         fields[1].out_value = out_buf;
  72         fields[1].in_value = NULL;
  73
  74         if (in)
  75         {
  76                 fields[1].in_value = (uint8_t *)in;
  77                 jtag_add_dr_scan(jtag_info->tap, 2, fields, TAP_DRPAUSE);
  78                 jtag_add_callback(arm7flip32, (jtag_callback_data_t)in);
  79         } else
  80         {
  81                 jtag_add_dr_scan(jtag_info->tap, 2, fields, TAP_DRPAUSE);
  82         }
  83
  84         if (clock_arg)
  85                 jtag_add_runtest(0, TAP_DRPAUSE);
  86
  87 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
  88         if ((retval = jtag_execute_queue()) != ERROR_OK)
  89         {
  90                 return retval;
  91         }
  92
  93         if (in)
  94                 LOG_DEBUG("out: %8.8x, in: %8.8x, instruction: %i, clock: %i", out, *in, instruction, clock);
  95         else
  96                 LOG_DEBUG("out: %8.8x, instruction: %i, clock: %i", out, instruction, clock_arg);
  97 #else
  98                 LOG_DEBUG("out: %8.8" PRIx32 ", instruction: %i, clock: %i", out, instruction, clock_arg);
  99 #endif
 100
 101         return ERROR_OK;
 102 }
 103
 104 static int arm720t_read_cp15(struct target *target, uint32_t opcode, uint32_t *value)
 105 {
 106         /* fetch CP15 opcode */
 107         arm720t_scan_cp15(target, opcode, NULL, 1, 1);
 108         /* "DECODE" stage */
 109         arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 1);
 110         /* "EXECUTE" stage (1) */
 111         arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 0);
 112         arm720t_scan_cp15(target, 0x0, NULL, 0, 1);
 113         /* "EXECUTE" stage (2) */
 114         arm720t_scan_cp15(target, 0x0, NULL, 0, 1);
 115         /* "EXECUTE" stage (3), CDATA is read */
 116         arm720t_scan_cp15(target, ARMV4_5_NOP, value, 1, 1);
 117
 118         return ERROR_OK;
 119 }
 120
 121 static int arm720t_write_cp15(struct target *target, uint32_t opcode, uint32_t value)
 122 {
 123         /* fetch CP15 opcode */
 124         arm720t_scan_cp15(target, opcode, NULL, 1, 1);
 125         /* "DECODE" stage */
 126         arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 1);
 127         /* "EXECUTE" stage (1) */
 128         arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 0);
 129         arm720t_scan_cp15(target, 0x0, NULL, 0, 1);
 130         /* "EXECUTE" stage (2) */
 131         arm720t_scan_cp15(target, value, NULL, 0, 1);
 132         arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 1);
 133
 134         return ERROR_OK;
 135 }
 136
 137 static int arm720t_get_ttb(struct target *target, uint32_t *result)
 138 {
 139         uint32_t ttb = 0x0;
 140
 141         int retval;
 142
 143         retval = arm720t_read_cp15(target, 0xee120f10, &ttb);
 144         if (retval != ERROR_OK)
 145                 return retval;
 146         retval = jtag_execute_queue();
 147         if (retval != ERROR_OK)
 148                 return retval;
 149
 150         ttb &= 0xffffc000;
 151
 152         *result = ttb;
 153
 154         return ERROR_OK;
 155 }
 156
 157 static int arm720t_disable_mmu_caches(struct target *target,
 158                 int mmu, int d_u_cache, int i_cache)
 159 {
 160         uint32_t cp15_control;
 161         int retval;
 162
 163         /* read cp15 control register */
 164         retval = arm720t_read_cp15(target, 0xee110f10, &cp15_control);
 165         if (retval != ERROR_OK)
 166                 return retval;
 167         retval = jtag_execute_queue();
 168         if (retval != ERROR_OK)
 169                 return retval;
 170
 171         if (mmu)
 172                 cp15_control &= ~0x1U;
 173
 174         if (d_u_cache || i_cache)
 175                 cp15_control &= ~0x4U;
 176
 177         retval = arm720t_write_cp15(target, 0xee010f10, cp15_control);
 178         return retval;
 179 }
 180
 181 static int arm720t_enable_mmu_caches(struct target *target,
 182                 int mmu, int d_u_cache, int i_cache)
 183 {
 184         uint32_t cp15_control;
 185         int retval;
 186
 187         /* read cp15 control register */
 188         retval = arm720t_read_cp15(target, 0xee110f10, &cp15_control);
 189         if (retval != ERROR_OK)
 190                 return retval;
 191         retval = jtag_execute_queue();
 192         if (retval != ERROR_OK)
 193                 return retval;
 194
 195         if (mmu)
 196                 cp15_control |= 0x1U;
 197
 198         if (d_u_cache || i_cache)
 199                 cp15_control |= 0x4U;
 200
 201         retval = arm720t_write_cp15(target, 0xee010f10, cp15_control);
 202         return retval;
 203 }
 204
 205 static void arm720t_post_debug_entry(struct target *target)
 206 {
 207         struct arm720t_common *arm720t = target_to_arm720(target);
 208
 209         /* examine cp15 control reg */
 210         arm720t_read_cp15(target, 0xee110f10, &arm720t->cp15_control_reg);
 211         jtag_execute_queue();
 212         LOG_DEBUG("cp15_control_reg: %8.8" PRIx32 "", arm720t->cp15_control_reg);
 213
 214         arm720t->armv4_5_mmu.mmu_enabled = (arm720t->cp15_control_reg & 0x1U) ? 1 : 0;
 215         arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm720t->cp15_control_reg & 0x4U) ? 1 : 0;
 216         arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
 217
 218         /* save i/d fault status and address register */
 219         arm720t_read_cp15(target, 0xee150f10, &arm720t->fsr_reg);
 220         arm720t_read_cp15(target, 0xee160f10, &arm720t->far_reg);
 221         jtag_execute_queue();
 222 }
 223
 224 static void arm720t_pre_restore_context(struct target *target)
 225 {
 226         struct arm720t_common *arm720t = target_to_arm720(target);
 227
 228         /* restore i/d fault status and address register */
 229         arm720t_write_cp15(target, 0xee050f10, arm720t->fsr_reg);
 230         arm720t_write_cp15(target, 0xee060f10, arm720t->far_reg);
 231 }
 232
 233 static int arm720t_verify_pointer(struct command_context *cmd_ctx,
 234                 struct arm720t_common *arm720t)
 235 {
 236         if (arm720t->common_magic != ARM720T_COMMON_MAGIC) {
 237                 command_print(cmd_ctx, "target is not an ARM720");
 238                 return ERROR_TARGET_INVALID;
 239         }
 240         return ERROR_OK;
 241 }
 242
 243 static int arm720t_arch_state(struct target *target)
 244 {
 245         struct arm720t_common *arm720t = target_to_arm720(target);
 246         struct arm *armv4_5;
 247
 248         static const char *state[] =
 249         {
 250                 "disabled", "enabled"
 251         };
 252
 253         armv4_5 = &arm720t->arm7_9_common.armv4_5_common;
 254
 255         arm_arch_state(target);
 256         LOG_USER("MMU: %s, Cache: %s",
 257                          state[arm720t->armv4_5_mmu.mmu_enabled],
 258                          state[arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled]);
 259
 260         return ERROR_OK;
 261 }
 262
 263 static int arm720_mmu(struct target *target, int *enabled)
 264 {
 265         if (target->state != TARGET_HALTED) {
 266                 LOG_ERROR("%s: target not halted", __func__);
 267                 return ERROR_TARGET_INVALID;
 268         }
 269
 270         *enabled = target_to_arm720(target)->armv4_5_mmu.mmu_enabled;
 271         return ERROR_OK;
 272 }
 273
 274 static int arm720_virt2phys(struct target *target,
 275                 uint32_t virtual, uint32_t *physical)
 276 {
 277         uint32_t cb;
 278         struct arm720t_common *arm720t = target_to_arm720(target);
 279
 280         uint32_t ret;
 281         int retval = armv4_5_mmu_translate_va(target,
 282                         &arm720t->armv4_5_mmu, virtual, &cb, &ret);
 283         if (retval != ERROR_OK)
 284                 return retval;
 285         *physical = ret;
 286         return ERROR_OK;
 287 }
 288
 289 static int arm720t_read_memory(struct target *target,
 290                 uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
 291 {
 292         int retval;
 293         struct arm720t_common *arm720t = target_to_arm720(target);
 294
 295         /* disable cache, but leave MMU enabled */
 296         if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
 297         {
 298                 retval = arm720t_disable_mmu_caches(target, 0, 1, 0);
 299                 if (retval != ERROR_OK)
 300                         return retval;
 301         }
 302         retval = arm7_9_read_memory(target, address, size, count, buffer);
 303
 304         if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
 305         {
 306                 retval = arm720t_enable_mmu_caches(target, 0, 1, 0);
 307                 if (retval != ERROR_OK)
 308                         return retval;
 309         }
 310
 311         return retval;
 312 }
 313
 314 static int arm720t_read_phys_memory(struct target *target,
 315                 uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
 316 {
 317         struct arm720t_common *arm720t = target_to_arm720(target);
 318
 319         return armv4_5_mmu_read_physical(target, &arm720t->armv4_5_mmu, address, size, count, buffer);
 320 }
 321
 322 static int arm720t_write_phys_memory(struct target *target,
 323                 uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
 324 {
 325         struct arm720t_common *arm720t = target_to_arm720(target);
 326
 327         return armv4_5_mmu_write_physical(target, &arm720t->armv4_5_mmu, address, size, count, buffer);
 328 }
 329
 330 static int arm720t_soft_reset_halt(struct target *target)
 331 {
 332         int retval = ERROR_OK;
 333         struct arm720t_common *arm720t = target_to_arm720(target);
 334         struct reg *dbg_stat = &arm720t->arm7_9_common
 335                         .eice_cache->reg_list[EICE_DBG_STAT];
 336         struct arm *armv4_5 = &arm720t->arm7_9_common
 337                         .armv4_5_common;
 338
 339         if ((retval = target_halt(target)) != ERROR_OK)
 340         {
 341                 return retval;
 342         }
 343
 344         long long then = timeval_ms();
 345         int timeout;
 346         while (!(timeout = ((timeval_ms()-then) > 1000)))
 347         {
 348                 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
 349                 {
 350                         embeddedice_read_reg(dbg_stat);
 351                         if ((retval = jtag_execute_queue()) != ERROR_OK)
 352                         {
 353                                 return retval;
 354                         }
 355                 } else
 356                 {
 357                         break;
 358                 }
 359                 if (debug_level >= 3)
 360                 {
 361                         alive_sleep(100);
 362                 } else
 363                 {
 364                         keep_alive();
 365                 }
 366         }
 367         if (timeout)
 368         {
 369                 LOG_ERROR("Failed to halt CPU after 1 sec");
 370                 return ERROR_TARGET_TIMEOUT;
 371         }
 372
 373         target->state = TARGET_HALTED;
 374
 375         /* SVC, ARM state, IRQ and FIQ disabled */
 376         uint32_t cpsr;
 377
 378         cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 32);
 379         cpsr &= ~0xff;
 380         cpsr |= 0xd3;
 381         arm_set_cpsr(armv4_5, cpsr);
 382         armv4_5->cpsr->dirty = 1;
 383
 384         /* start fetching from 0x0 */
 385         buf_set_u32(armv4_5->pc->value, 0, 32, 0x0);
 386         armv4_5->pc->dirty = 1;
 387         armv4_5->pc->valid = 1;
 388
 389         retval = arm720t_disable_mmu_caches(target, 1, 1, 1);
 390         if (retval != ERROR_OK)
 391                 return retval;
 392         arm720t->armv4_5_mmu.mmu_enabled = 0;
 393         arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
 394         arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
 395
 396         if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
 397         {
 398                 return retval;
 399         }
 400
 401         return ERROR_OK;
 402 }
 403
 404 static int arm720t_init_target(struct command_context *cmd_ctx, struct target *target)
 405 {
 406         return arm7tdmi_init_target(cmd_ctx, target);
 407 }
 408
 409 /* FIXME remove forward decls */
 410 static int arm720t_mrc(struct target *target, int cpnum,
 411                 uint32_t op1, uint32_t op2,
 412                 uint32_t CRn, uint32_t CRm,
 413                 uint32_t *value);
 414 static int arm720t_mcr(struct target *target, int cpnum,
 415                 uint32_t op1, uint32_t op2,
 416                 uint32_t CRn, uint32_t CRm,
 417                 uint32_t value);
 418
 419 static int arm720t_init_arch_info(struct target *target,
 420                 struct arm720t_common *arm720t, struct jtag_tap *tap)
 421 {
 422         struct arm7_9_common *arm7_9 = &arm720t->arm7_9_common;
 423
 424         arm7_9->armv4_5_common.mrc = arm720t_mrc;
 425         arm7_9->armv4_5_common.mcr = arm720t_mcr;
 426
 427         arm7tdmi_init_arch_info(target, arm7_9, tap);
 428
 429         arm720t->common_magic = ARM720T_COMMON_MAGIC;
 430
 431         arm7_9->post_debug_entry = arm720t_post_debug_entry;
 432         arm7_9->pre_restore_context = arm720t_pre_restore_context;
 433
 434         arm720t->armv4_5_mmu.armv4_5_cache.ctype = -1;
 435         arm720t->armv4_5_mmu.get_ttb = arm720t_get_ttb;
 436         arm720t->armv4_5_mmu.read_memory = arm7_9_read_memory;
 437         arm720t->armv4_5_mmu.write_memory = arm7_9_write_memory;
 438         arm720t->armv4_5_mmu.disable_mmu_caches = arm720t_disable_mmu_caches;
 439         arm720t->armv4_5_mmu.enable_mmu_caches = arm720t_enable_mmu_caches;
 440         arm720t->armv4_5_mmu.has_tiny_pages = 0;
 441         arm720t->armv4_5_mmu.mmu_enabled = 0;
 442
 443         return ERROR_OK;
 444 }
 445
 446 static int arm720t_target_create(struct target *target, Jim_Interp *interp)
 447 {
 448         struct arm720t_common *arm720t = calloc(1, sizeof(*arm720t));
 449
 450         arm720t->arm7_9_common.armv4_5_common.is_armv4 = true;
 451         return arm720t_init_arch_info(target, arm720t, target->tap);
 452 }
 453
 454 COMMAND_HANDLER(arm720t_handle_cp15_command)
 455 {
 456         int retval;
 457         struct target *target = get_current_target(CMD_CTX);
 458         struct arm720t_common *arm720t = target_to_arm720(target);
 459         struct arm_jtag *jtag_info;
 460
 461         retval = arm720t_verify_pointer(CMD_CTX, arm720t);
 462         if (retval != ERROR_OK)
 463                 return retval;
 464
 465         jtag_info = &arm720t->arm7_9_common.jtag_info;
 466
 467         if (target->state != TARGET_HALTED)
 468         {
 469                 command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
 470                 return ERROR_OK;
 471         }
 472
 473         /* one or more argument, access a single register (write if second argument is given */
 474         if (CMD_ARGC >= 1)
 475         {
 476                 uint32_t opcode;
 477                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], opcode);
 478
 479                 if (CMD_ARGC == 1)
 480                 {
 481                         uint32_t value;
 482                         if ((retval = arm720t_read_cp15(target, opcode, &value)) != ERROR_OK)
 483                         {
 484                                 command_print(CMD_CTX, "couldn't access cp15 with opcode 0x%8.8" PRIx32 "", opcode);
 485                                 return ERROR_OK;
 486                         }
 487
 488                         if ((retval = jtag_execute_queue()) != ERROR_OK)
 489                         {
 490                                 return retval;
 491                         }
 492
 493                         command_print(CMD_CTX, "0x%8.8" PRIx32 ": 0x%8.8" PRIx32 "", opcode, value);
 494                 }
 495                 else if (CMD_ARGC == 2)
 496                 {
 497                         uint32_t value;
 498                         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
 499
 500                         if ((retval = arm720t_write_cp15(target, opcode, value)) != ERROR_OK)
 501                         {
 502                                 command_print(CMD_CTX, "couldn't access cp15 with opcode 0x%8.8" PRIx32 "", opcode);
 503                                 return ERROR_OK;
 504                         }
 505                         command_print(CMD_CTX, "0x%8.8" PRIx32 ": 0x%8.8" PRIx32 "", opcode, value);
 506                 }
 507         }
 508
 509         return ERROR_OK;
 510 }
 511
 512 static int arm720t_mrc(struct target *target, int cpnum,
 513                 uint32_t op1, uint32_t op2,
 514                 uint32_t CRn, uint32_t CRm,
 515                 uint32_t *value)
 516 {
 517         if (cpnum!=15)
 518         {
 519                 LOG_ERROR("Only cp15 is supported");
 520                 return ERROR_FAIL;
 521         }
 522
 523         /* read "to" r0 */
 524         return arm720t_read_cp15(target,
 525                         ARMV4_5_MRC(cpnum, op1, 0, CRn, CRm, op2),
 526                         value);
 527
 528 }
 529
 530 static int arm720t_mcr(struct target *target, int cpnum,
 531                 uint32_t op1, uint32_t op2,
 532                 uint32_t CRn, uint32_t CRm,
 533                 uint32_t value)
 534 {
 535         if (cpnum!=15)
 536         {
 537                 LOG_ERROR("Only cp15 is supported");
 538                 return ERROR_FAIL;
 539         }
 540
 541         /* write "from" r0 */
 542         return arm720t_write_cp15(target,
 543                         ARMV4_5_MCR(cpnum, op1, 0, CRn, CRm, op2),
 544                         value);
 545 }
 546
 547 static const struct command_registration arm720t_exec_command_handlers[] = {
 548         {
 549                 .name = "cp15",
 550                 .handler = arm720t_handle_cp15_command,
 551                 .mode = COMMAND_EXEC,
 552                 /* prefer using less error-prone "arm mcr" or "arm mrc" */
 553                 .help = "display/modify cp15 register using ARM opcode"
 554                         " (DEPRECATED)",
 555                 .usage = "instruction [value]",
 556         },
 557         COMMAND_REGISTRATION_DONE
 558 };
 559
 560 static const struct command_registration arm720t_command_handlers[] = {
 561         {
 562                 .chain = arm7_9_command_handlers,
 563         },
 564         {
 565                 .name = "arm720t",
 566                 .mode = COMMAND_ANY,
 567                 .help = "arm720t command group",
 568                 .chain = arm720t_exec_command_handlers,
 569         },
 570         COMMAND_REGISTRATION_DONE
 571 };
 572
 573 /** Holds methods for ARM720 targets. */
 574 struct target_type arm720t_target =
 575 {
 576         .name = "arm720t",
 577
 578         .poll = arm7_9_poll,
 579         .arch_state = arm720t_arch_state,
 580
 581         .halt = arm7_9_halt,
 582         .resume = arm7_9_resume,
 583         .step = arm7_9_step,
 584
 585         .assert_reset = arm7_9_assert_reset,
 586         .deassert_reset = arm7_9_deassert_reset,
 587         .soft_reset_halt = arm720t_soft_reset_halt,
 588
 589         .get_gdb_reg_list = arm_get_gdb_reg_list,
 590
 591         .read_memory = arm720t_read_memory,
 592         .write_memory = arm7_9_write_memory,
 593         .read_phys_memory = arm720t_read_phys_memory,
 594         .write_phys_memory = arm720t_write_phys_memory,
 595         .mmu = arm720_mmu,
 596         .virt2phys = arm720_virt2phys,
 597
 598         .bulk_write_memory = arm7_9_bulk_write_memory,
 599
 600         .checksum_memory = arm_checksum_memory,
 601         .blank_check_memory = arm_blank_check_memory,
 602
 603         .run_algorithm = armv4_5_run_algorithm,
 604
 605         .add_breakpoint = arm7_9_add_breakpoint,
 606         .remove_breakpoint = arm7_9_remove_breakpoint,
 607         .add_watchpoint = arm7_9_add_watchpoint,
 608         .remove_watchpoint = arm7_9_remove_watchpoint,
 609
 610         .commands = arm720t_command_handlers,
 611         .target_create = arm720t_target_create,
 612         .init_target = arm720t_init_target,
 613         .examine = arm7_9_examine,
 614         .check_reset = arm7_9_check_reset,
 615 };