1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
27 #include "time_support.h"
33 #define _DEBUG_INSTRUCTION_EXECUTION_
37 int arm720t_register_commands(struct command_context_s
*cmd_ctx
);
39 int arm720t_handle_cp15_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
40 int arm720t_handle_virt2phys_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
41 int arm720t_handle_md_phys_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
42 int arm720t_handle_mw_phys_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
44 /* forward declarations */
45 int arm720t_target_create(struct target_s
*target
,Jim_Interp
*interp
);
46 int arm720t_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
);
47 int arm720t_quit(void);
48 int arm720t_arch_state(struct target_s
*target
);
49 int arm720t_read_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
);
50 int arm720t_write_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
);
51 int arm720t_soft_reset_halt(struct target_s
*target
);
53 target_type_t arm720t_target
=
58 .arch_state
= arm720t_arch_state
,
61 .resume
= arm7_9_resume
,
64 .assert_reset
= arm7_9_assert_reset
,
65 .deassert_reset
= arm7_9_deassert_reset
,
66 .soft_reset_halt
= arm720t_soft_reset_halt
,
68 .get_gdb_reg_list
= armv4_5_get_gdb_reg_list
,
70 .read_memory
= arm720t_read_memory
,
71 .write_memory
= arm720t_write_memory
,
72 .bulk_write_memory
= arm7_9_bulk_write_memory
,
73 .checksum_memory
= arm7_9_checksum_memory
,
74 .blank_check_memory
= arm7_9_blank_check_memory
,
76 .run_algorithm
= armv4_5_run_algorithm
,
78 .add_breakpoint
= arm7_9_add_breakpoint
,
79 .remove_breakpoint
= arm7_9_remove_breakpoint
,
80 .add_watchpoint
= arm7_9_add_watchpoint
,
81 .remove_watchpoint
= arm7_9_remove_watchpoint
,
83 .register_commands
= arm720t_register_commands
,
84 .target_create
= arm720t_target_create
,
85 .init_target
= arm720t_init_target
,
86 .examine
= arm7tdmi_examine
,
90 int arm720t_scan_cp15(target_t
*target
, u32 out
, u32
*in
, int instruction
, int clock
)
92 int retval
= ERROR_OK
;
93 armv4_5_common_t
*armv4_5
= target
->arch_info
;
94 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
95 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
96 scan_field_t fields
[2];
98 u8 instruction_buf
= instruction
;
100 buf_set_u32(out_buf
, 0, 32, flip_u32(out
, 32));
102 jtag_add_end_state(TAP_DRPAUSE
);
103 if((retval
= arm_jtag_scann(jtag_info
, 0xf)) != ERROR_OK
)
107 if((retval
= arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
)) != ERROR_OK
)
112 fields
[0].tap
= jtag_info
->tap
;
113 fields
[0].num_bits
= 1;
114 fields
[0].out_value
= &instruction_buf
;
115 fields
[0].in_value
= NULL
;
116 fields
[0].in_handler
= NULL
;
118 fields
[1].tap
= jtag_info
->tap
;
119 fields
[1].num_bits
= 32;
120 fields
[1].out_value
= out_buf
;
121 fields
[1].in_value
= NULL
;
122 fields
[1].in_handler
= NULL
;
126 fields
[1].in_value
= tmp
;
127 jtag_add_dr_scan_now(2, fields
, TAP_INVALID
);
128 *in
=flip_u32(le_to_h_u32(tmp
), 32);
131 jtag_add_dr_scan(2, fields
, TAP_INVALID
);
135 jtag_add_runtest(0, TAP_INVALID
);
137 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
138 if((retval
= jtag_execute_queue()) != ERROR_OK
)
144 LOG_DEBUG("out: %8.8x, in: %8.8x, instruction: %i, clock: %i", out
, *in
, instruction
, clock
);
146 LOG_DEBUG("out: %8.8x, instruction: %i, clock: %i", out
, instruction
, clock
);
148 LOG_DEBUG("out: %8.8x, instruction: %i, clock: %i", out
, instruction
, clock
);
154 int arm720t_read_cp15(target_t
*target
, u32 opcode
, u32
*value
)
156 /* fetch CP15 opcode */
157 arm720t_scan_cp15(target
, opcode
, NULL
, 1, 1);
159 arm720t_scan_cp15(target
, ARMV4_5_NOP
, NULL
, 1, 1);
160 /* "EXECUTE" stage (1) */
161 arm720t_scan_cp15(target
, ARMV4_5_NOP
, NULL
, 1, 0);
162 arm720t_scan_cp15(target
, 0x0, NULL
, 0, 1);
163 /* "EXECUTE" stage (2) */
164 arm720t_scan_cp15(target
, 0x0, NULL
, 0, 1);
165 /* "EXECUTE" stage (3), CDATA is read */
166 arm720t_scan_cp15(target
, ARMV4_5_NOP
, value
, 1, 1);
171 int arm720t_write_cp15(target_t
*target
, u32 opcode
, u32 value
)
173 /* fetch CP15 opcode */
174 arm720t_scan_cp15(target
, opcode
, NULL
, 1, 1);
176 arm720t_scan_cp15(target
, ARMV4_5_NOP
, NULL
, 1, 1);
177 /* "EXECUTE" stage (1) */
178 arm720t_scan_cp15(target
, ARMV4_5_NOP
, NULL
, 1, 0);
179 arm720t_scan_cp15(target
, 0x0, NULL
, 0, 1);
180 /* "EXECUTE" stage (2) */
181 arm720t_scan_cp15(target
, value
, NULL
, 0, 1);
182 arm720t_scan_cp15(target
, ARMV4_5_NOP
, NULL
, 1, 1);
187 u32
arm720t_get_ttb(target_t
*target
)
191 arm720t_read_cp15(target
, 0xee120f10, &ttb
);
192 jtag_execute_queue();
199 void arm720t_disable_mmu_caches(target_t
*target
, int mmu
, int d_u_cache
, int i_cache
)
203 /* read cp15 control register */
204 arm720t_read_cp15(target
, 0xee110f10, &cp15_control
);
205 jtag_execute_queue();
208 cp15_control
&= ~0x1U
;
210 if (d_u_cache
|| i_cache
)
211 cp15_control
&= ~0x4U
;
213 arm720t_write_cp15(target
, 0xee010f10, cp15_control
);
216 void arm720t_enable_mmu_caches(target_t
*target
, int mmu
, int d_u_cache
, int i_cache
)
220 /* read cp15 control register */
221 arm720t_read_cp15(target
, 0xee110f10, &cp15_control
);
222 jtag_execute_queue();
225 cp15_control
|= 0x1U
;
227 if (d_u_cache
|| i_cache
)
228 cp15_control
|= 0x4U
;
230 arm720t_write_cp15(target
, 0xee010f10, cp15_control
);
233 void arm720t_post_debug_entry(target_t
*target
)
235 armv4_5_common_t
*armv4_5
= target
->arch_info
;
236 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
237 arm7tdmi_common_t
*arm7tdmi
= arm7_9
->arch_info
;
238 arm720t_common_t
*arm720t
= arm7tdmi
->arch_info
;
240 /* examine cp15 control reg */
241 arm720t_read_cp15(target
, 0xee110f10, &arm720t
->cp15_control_reg
);
242 jtag_execute_queue();
243 LOG_DEBUG("cp15_control_reg: %8.8x", arm720t
->cp15_control_reg
);
245 arm720t
->armv4_5_mmu
.mmu_enabled
= (arm720t
->cp15_control_reg
& 0x1U
) ? 1 : 0;
246 arm720t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= (arm720t
->cp15_control_reg
& 0x4U
) ? 1 : 0;
247 arm720t
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= 0;
249 /* save i/d fault status and address register */
250 arm720t_read_cp15(target
, 0xee150f10, &arm720t
->fsr_reg
);
251 arm720t_read_cp15(target
, 0xee160f10, &arm720t
->far_reg
);
252 jtag_execute_queue();
255 void arm720t_pre_restore_context(target_t
*target
)
257 armv4_5_common_t
*armv4_5
= target
->arch_info
;
258 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
259 arm7tdmi_common_t
*arm7tdmi
= arm7_9
->arch_info
;
260 arm720t_common_t
*arm720t
= arm7tdmi
->arch_info
;
262 /* restore i/d fault status and address register */
263 arm720t_write_cp15(target
, 0xee050f10, arm720t
->fsr_reg
);
264 arm720t_write_cp15(target
, 0xee060f10, arm720t
->far_reg
);
267 int arm720t_get_arch_pointers(target_t
*target
, armv4_5_common_t
**armv4_5_p
, arm7_9_common_t
**arm7_9_p
, arm7tdmi_common_t
**arm7tdmi_p
, arm720t_common_t
**arm720t_p
)
269 armv4_5_common_t
*armv4_5
= target
->arch_info
;
270 arm7_9_common_t
*arm7_9
;
271 arm7tdmi_common_t
*arm7tdmi
;
272 arm720t_common_t
*arm720t
;
274 if (armv4_5
->common_magic
!= ARMV4_5_COMMON_MAGIC
)
279 arm7_9
= armv4_5
->arch_info
;
280 if (arm7_9
->common_magic
!= ARM7_9_COMMON_MAGIC
)
285 arm7tdmi
= arm7_9
->arch_info
;
286 if (arm7tdmi
->common_magic
!= ARM7TDMI_COMMON_MAGIC
)
291 arm720t
= arm7tdmi
->arch_info
;
292 if (arm720t
->common_magic
!= ARM720T_COMMON_MAGIC
)
297 *armv4_5_p
= armv4_5
;
299 *arm7tdmi_p
= arm7tdmi
;
300 *arm720t_p
= arm720t
;
305 int arm720t_arch_state(struct target_s
*target
)
307 armv4_5_common_t
*armv4_5
= target
->arch_info
;
308 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
309 arm7tdmi_common_t
*arm7tdmi
= arm7_9
->arch_info
;
310 arm720t_common_t
*arm720t
= arm7tdmi
->arch_info
;
314 "disabled", "enabled"
317 if (armv4_5
->common_magic
!= ARMV4_5_COMMON_MAGIC
)
319 LOG_ERROR("BUG: called for a non-ARMv4/5 target");
323 LOG_USER("target halted in %s state due to %s, current mode: %s\n"
324 "cpsr: 0x%8.8x pc: 0x%8.8x\n"
325 "MMU: %s, Cache: %s",
326 armv4_5_state_strings
[armv4_5
->core_state
],
327 Jim_Nvp_value2name_simple( nvp_target_debug_reason
, target
->debug_reason
)->name
,
328 armv4_5_mode_strings
[armv4_5_mode_to_number(armv4_5
->core_mode
)],
329 buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32),
330 buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32),
331 state
[arm720t
->armv4_5_mmu
.mmu_enabled
],
332 state
[arm720t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
]);
337 int arm720t_read_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
)
340 armv4_5_common_t
*armv4_5
= target
->arch_info
;
341 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
342 arm7tdmi_common_t
*arm7tdmi
= arm7_9
->arch_info
;
343 arm720t_common_t
*arm720t
= arm7tdmi
->arch_info
;
345 /* disable cache, but leave MMU enabled */
346 if (arm720t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
)
347 arm720t_disable_mmu_caches(target
, 0, 1, 0);
349 retval
= arm7_9_read_memory(target
, address
, size
, count
, buffer
);
351 if (arm720t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
)
352 arm720t_enable_mmu_caches(target
, 0, 1, 0);
357 int arm720t_write_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
)
361 if ((retval
= arm7_9_write_memory(target
, address
, size
, count
, buffer
)) != ERROR_OK
)
367 int arm720t_soft_reset_halt(struct target_s
*target
)
369 int retval
= ERROR_OK
;
370 armv4_5_common_t
*armv4_5
= target
->arch_info
;
371 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
372 arm7tdmi_common_t
*arm7tdmi
= arm7_9
->arch_info
;
373 arm720t_common_t
*arm720t
= arm7tdmi
->arch_info
;
374 reg_t
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
376 if ((retval
= target_halt(target
)) != ERROR_OK
)
381 long long then
=timeval_ms();
383 while (!(timeout
=((timeval_ms()-then
)>1000)))
385 if (buf_get_u32(dbg_stat
->value
, EICE_DBG_STATUS_DBGACK
, 1) == 0)
387 embeddedice_read_reg(dbg_stat
);
388 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
406 LOG_ERROR("Failed to halt CPU after 1 sec");
407 return ERROR_TARGET_TIMEOUT
;
410 target
->state
= TARGET_HALTED
;
412 /* SVC, ARM state, IRQ and FIQ disabled */
413 buf_set_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8, 0xd3);
414 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].dirty
= 1;
415 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].valid
= 1;
417 /* start fetching from 0x0 */
418 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, 0x0);
419 armv4_5
->core_cache
->reg_list
[15].dirty
= 1;
420 armv4_5
->core_cache
->reg_list
[15].valid
= 1;
422 armv4_5
->core_mode
= ARMV4_5_MODE_SVC
;
423 armv4_5
->core_state
= ARMV4_5_STATE_ARM
;
425 arm720t_disable_mmu_caches(target
, 1, 1, 1);
426 arm720t
->armv4_5_mmu
.mmu_enabled
= 0;
427 arm720t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= 0;
428 arm720t
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= 0;
430 if ((retval
= target_call_event_callbacks(target
, TARGET_EVENT_HALTED
)) != ERROR_OK
)
438 int arm720t_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
)
440 arm7tdmi_init_target(cmd_ctx
, target
);
445 int arm720t_quit(void)
450 int arm720t_init_arch_info(target_t
*target
, arm720t_common_t
*arm720t
, jtag_tap_t
*tap
)
452 arm7tdmi_common_t
*arm7tdmi
= &arm720t
->arm7tdmi_common
;
453 arm7_9_common_t
*arm7_9
= &arm7tdmi
->arm7_9_common
;
455 arm7tdmi_init_arch_info(target
, arm7tdmi
, tap
);
457 arm7tdmi
->arch_info
= arm720t
;
458 arm720t
->common_magic
= ARM720T_COMMON_MAGIC
;
460 arm7_9
->post_debug_entry
= arm720t_post_debug_entry
;
461 arm7_9
->pre_restore_context
= arm720t_pre_restore_context
;
463 arm720t
->armv4_5_mmu
.armv4_5_cache
.ctype
= -1;
464 arm720t
->armv4_5_mmu
.get_ttb
= arm720t_get_ttb
;
465 arm720t
->armv4_5_mmu
.read_memory
= arm7_9_read_memory
;
466 arm720t
->armv4_5_mmu
.write_memory
= arm7_9_write_memory
;
467 arm720t
->armv4_5_mmu
.disable_mmu_caches
= arm720t_disable_mmu_caches
;
468 arm720t
->armv4_5_mmu
.enable_mmu_caches
= arm720t_enable_mmu_caches
;
469 arm720t
->armv4_5_mmu
.has_tiny_pages
= 0;
470 arm720t
->armv4_5_mmu
.mmu_enabled
= 0;
475 int arm720t_target_create(struct target_s
*target
, Jim_Interp
*interp
)
477 arm720t_common_t
*arm720t
= calloc(1,sizeof(arm720t_common_t
));
479 arm720t_init_arch_info(target
, arm720t
, target
->tap
);
484 int arm720t_register_commands(struct command_context_s
*cmd_ctx
)
487 command_t
*arm720t_cmd
;
490 retval
= arm7tdmi_register_commands(cmd_ctx
);
492 arm720t_cmd
= register_command(cmd_ctx
, NULL
, "arm720t", NULL
, COMMAND_ANY
, "arm720t specific commands");
494 register_command(cmd_ctx
, arm720t_cmd
, "cp15", arm720t_handle_cp15_command
, COMMAND_EXEC
, "display/modify cp15 register <opcode> [value]");
495 register_command(cmd_ctx
, arm720t_cmd
, "virt2phys", arm720t_handle_virt2phys_command
, COMMAND_EXEC
, "translate va to pa <va>");
497 register_command(cmd_ctx
, arm720t_cmd
, "mdw_phys", arm720t_handle_md_phys_command
, COMMAND_EXEC
, "display memory words <physical addr> [count]");
498 register_command(cmd_ctx
, arm720t_cmd
, "mdh_phys", arm720t_handle_md_phys_command
, COMMAND_EXEC
, "display memory half-words <physical addr> [count]");
499 register_command(cmd_ctx
, arm720t_cmd
, "mdb_phys", arm720t_handle_md_phys_command
, COMMAND_EXEC
, "display memory bytes <physical addr> [count]");
501 register_command(cmd_ctx
, arm720t_cmd
, "mww_phys", arm720t_handle_mw_phys_command
, COMMAND_EXEC
, "write memory word <physical addr> <value>");
502 register_command(cmd_ctx
, arm720t_cmd
, "mwh_phys", arm720t_handle_mw_phys_command
, COMMAND_EXEC
, "write memory half-word <physical addr> <value>");
503 register_command(cmd_ctx
, arm720t_cmd
, "mwb_phys", arm720t_handle_mw_phys_command
, COMMAND_EXEC
, "write memory byte <physical addr> <value>");
508 int arm720t_handle_cp15_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
511 target_t
*target
= get_current_target(cmd_ctx
);
512 armv4_5_common_t
*armv4_5
;
513 arm7_9_common_t
*arm7_9
;
514 arm7tdmi_common_t
*arm7tdmi
;
515 arm720t_common_t
*arm720t
;
516 arm_jtag_t
*jtag_info
;
518 if (arm720t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm7tdmi
, &arm720t
) != ERROR_OK
)
520 command_print(cmd_ctx
, "current target isn't an ARM720t target");
524 jtag_info
= &arm7_9
->jtag_info
;
526 if (target
->state
!= TARGET_HALTED
)
528 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
532 /* one or more argument, access a single register (write if second argument is given */
535 u32 opcode
= strtoul(args
[0], NULL
, 0);
540 if ((retval
= arm720t_read_cp15(target
, opcode
, &value
)) != ERROR_OK
)
542 command_print(cmd_ctx
, "couldn't access cp15 with opcode 0x%8.8x", opcode
);
546 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
551 command_print(cmd_ctx
, "0x%8.8x: 0x%8.8x", opcode
, value
);
555 u32 value
= strtoul(args
[1], NULL
, 0);
556 if ((retval
= arm720t_write_cp15(target
, opcode
, value
)) != ERROR_OK
)
558 command_print(cmd_ctx
, "couldn't access cp15 with opcode 0x%8.8x", opcode
);
561 command_print(cmd_ctx
, "0x%8.8x: 0x%8.8x", opcode
, value
);
568 int arm720t_handle_virt2phys_command(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
)
570 target_t
*target
= get_current_target(cmd_ctx
);
571 armv4_5_common_t
*armv4_5
;
572 arm7_9_common_t
*arm7_9
;
573 arm7tdmi_common_t
*arm7tdmi
;
574 arm720t_common_t
*arm720t
;
575 arm_jtag_t
*jtag_info
;
577 if (arm720t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm7tdmi
, &arm720t
) != ERROR_OK
)
579 command_print(cmd_ctx
, "current target isn't an ARM720t target");
583 jtag_info
= &arm7_9
->jtag_info
;
585 if (target
->state
!= TARGET_HALTED
)
587 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
591 return armv4_5_mmu_handle_virt2phys_command(cmd_ctx
, cmd
, args
, argc
, target
, &arm720t
->armv4_5_mmu
);
594 int arm720t_handle_md_phys_command(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
)
596 target_t
*target
= get_current_target(cmd_ctx
);
597 armv4_5_common_t
*armv4_5
;
598 arm7_9_common_t
*arm7_9
;
599 arm7tdmi_common_t
*arm7tdmi
;
600 arm720t_common_t
*arm720t
;
601 arm_jtag_t
*jtag_info
;
603 if (arm720t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm7tdmi
, &arm720t
) != ERROR_OK
)
605 command_print(cmd_ctx
, "current target isn't an ARM720t target");
609 jtag_info
= &arm7_9
->jtag_info
;
611 if (target
->state
!= TARGET_HALTED
)
613 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
617 return armv4_5_mmu_handle_md_phys_command(cmd_ctx
, cmd
, args
, argc
, target
, &arm720t
->armv4_5_mmu
);
620 int arm720t_handle_mw_phys_command(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
)
622 target_t
*target
= get_current_target(cmd_ctx
);
623 armv4_5_common_t
*armv4_5
;
624 arm7_9_common_t
*arm7_9
;
625 arm7tdmi_common_t
*arm7tdmi
;
626 arm720t_common_t
*arm720t
;
627 arm_jtag_t
*jtag_info
;
629 if (arm720t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm7tdmi
, &arm720t
) != ERROR_OK
)
631 command_print(cmd_ctx
, "current target isn't an ARM720t target");
635 jtag_info
= &arm7_9
->jtag_info
;
637 if (target
->state
!= TARGET_HALTED
)
639 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
643 return armv4_5_mmu_handle_mw_phys_command(cmd_ctx
, cmd
, args
, argc
, target
, &arm720t
->armv4_5_mmu
);
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