src/target/arm720t.c

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20 #ifdef HAVE_CONFIG_H
  21 #include "config.h"
  22 #endif
  23
  24 #include "arm720t.h"
  25 #include "jtag.h"
  26 #include "log.h"
  27 #include "time_support.h"
  28
  29 #include <stdlib.h>
  30 #include <string.h>
  31
  32 #if 0
  33 #define _DEBUG_INSTRUCTION_EXECUTION_
  34 #endif
  35
  36 /* cli handling */
  37 int arm720t_register_commands(struct command_context_s *cmd_ctx);
  38
  39 int arm720t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  40 int arm720t_handle_virt2phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  41 int arm720t_handle_md_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  42 int arm720t_handle_mw_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  43
  44 /* forward declarations */
  45 int arm720t_target_create(struct target_s *target,Jim_Interp *interp);
  46 int arm720t_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
  47 int arm720t_quit(void);
  48 int arm720t_arch_state(struct target_s *target);
  49 int arm720t_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
  50 int arm720t_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
  51 int arm720t_soft_reset_halt(struct target_s *target);
  52
  53 target_type_t arm720t_target =
  54 {
  55         .name = "arm720t",
  56
  57         .poll = arm7_9_poll,
  58         .arch_state = arm720t_arch_state,
  59
  60         .halt = arm7_9_halt,
  61         .resume = arm7_9_resume,
  62         .step = arm7_9_step,
  63
  64         .assert_reset = arm7_9_assert_reset,
  65         .deassert_reset = arm7_9_deassert_reset,
  66         .soft_reset_halt = arm720t_soft_reset_halt,
  67
  68         .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
  69
  70         .read_memory = arm720t_read_memory,
  71         .write_memory = arm720t_write_memory,
  72         .bulk_write_memory = arm7_9_bulk_write_memory,
  73         .checksum_memory = arm7_9_checksum_memory,
  74         .blank_check_memory = arm7_9_blank_check_memory,
  75
  76         .run_algorithm = armv4_5_run_algorithm,
  77
  78         .add_breakpoint = arm7_9_add_breakpoint,
  79         .remove_breakpoint = arm7_9_remove_breakpoint,
  80         .add_watchpoint = arm7_9_add_watchpoint,
  81         .remove_watchpoint = arm7_9_remove_watchpoint,
  82
  83         .register_commands = arm720t_register_commands,
  84         .target_create = arm720t_target_create,
  85         .init_target = arm720t_init_target,
  86         .examine = arm7tdmi_examine,
  87         .quit = arm720t_quit
  88 };
  89
  90 int arm720t_scan_cp15(target_t *target, u32 out, u32 *in, int instruction, int clock)
  91 {
  92         int retval = ERROR_OK;
  93         armv4_5_common_t *armv4_5 = target->arch_info;
  94         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  95         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
  96         scan_field_t fields[2];
  97         u8 out_buf[4];
  98         u8 instruction_buf = instruction;
  99
 100         buf_set_u32(out_buf, 0, 32, flip_u32(out, 32));
 101
 102         jtag_add_end_state(TAP_DRPAUSE);
 103         if((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
 104         {
 105                 return retval;
 106         }
 107         if((retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL)) != ERROR_OK)
 108         {
 109                 return retval;
 110         }
 111
 112         fields[0].tap = jtag_info->tap;
 113         fields[0].num_bits = 1;
 114         fields[0].out_value = &instruction_buf;
 115         fields[0].in_value = NULL;
 116
 117         fields[1].tap = jtag_info->tap;
 118         fields[1].num_bits = 32;
 119         fields[1].out_value = out_buf;
 120         fields[1].in_value = NULL;
 121
 122         if (in)
 123         {
 124                 u8 tmp[4];
 125                 fields[1].in_value = tmp;
 126                 jtag_add_dr_scan_now(2, fields, TAP_INVALID);
 127                 *in=flip_u32(le_to_h_u32(tmp), 32);
 128         } else
 129         {
 130                 jtag_add_dr_scan(2, fields, TAP_INVALID);
 131         }
 132
 133         if (clock)
 134                 jtag_add_runtest(0, TAP_INVALID);
 135
 136 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 137         if((retval = jtag_execute_queue()) != ERROR_OK)
 138         {
 139                 return retval;
 140         }
 141
 142         if (in)
 143                 LOG_DEBUG("out: %8.8x, in: %8.8x, instruction: %i, clock: %i", out, *in, instruction, clock);
 144         else
 145                 LOG_DEBUG("out: %8.8x, instruction: %i, clock: %i", out, instruction, clock);
 146 #else
 147                 LOG_DEBUG("out: %8.8x, instruction: %i, clock: %i", out, instruction, clock);
 148 #endif
 149
 150         return ERROR_OK;
 151 }
 152
 153 int arm720t_read_cp15(target_t *target, u32 opcode, u32 *value)
 154 {
 155         /* fetch CP15 opcode */
 156         arm720t_scan_cp15(target, opcode, NULL, 1, 1);
 157         /* "DECODE" stage */
 158         arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 1);
 159         /* "EXECUTE" stage (1) */
 160         arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 0);
 161         arm720t_scan_cp15(target, 0x0, NULL, 0, 1);
 162         /* "EXECUTE" stage (2) */
 163         arm720t_scan_cp15(target, 0x0, NULL, 0, 1);
 164         /* "EXECUTE" stage (3), CDATA is read */
 165         arm720t_scan_cp15(target, ARMV4_5_NOP, value, 1, 1);
 166
 167         return ERROR_OK;
 168 }
 169
 170 int arm720t_write_cp15(target_t *target, u32 opcode, u32 value)
 171 {
 172         /* fetch CP15 opcode */
 173         arm720t_scan_cp15(target, opcode, NULL, 1, 1);
 174         /* "DECODE" stage */
 175         arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 1);
 176         /* "EXECUTE" stage (1) */
 177         arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 0);
 178         arm720t_scan_cp15(target, 0x0, NULL, 0, 1);
 179         /* "EXECUTE" stage (2) */
 180         arm720t_scan_cp15(target, value, NULL, 0, 1);
 181         arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 1);
 182
 183         return ERROR_OK;
 184 }
 185
 186 u32 arm720t_get_ttb(target_t *target)
 187 {
 188         u32 ttb = 0x0;
 189
 190         arm720t_read_cp15(target, 0xee120f10, &ttb);
 191         jtag_execute_queue();
 192
 193         ttb &= 0xffffc000;
 194
 195         return ttb;
 196 }
 197
 198 void arm720t_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
 199 {
 200         u32 cp15_control;
 201
 202         /* read cp15 control register */
 203         arm720t_read_cp15(target, 0xee110f10, &cp15_control);
 204         jtag_execute_queue();
 205
 206         if (mmu)
 207                 cp15_control &= ~0x1U;
 208
 209         if (d_u_cache || i_cache)
 210                 cp15_control &= ~0x4U;
 211
 212         arm720t_write_cp15(target, 0xee010f10, cp15_control);
 213 }
 214
 215 void arm720t_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
 216 {
 217         u32 cp15_control;
 218
 219         /* read cp15 control register */
 220         arm720t_read_cp15(target, 0xee110f10, &cp15_control);
 221         jtag_execute_queue();
 222
 223         if (mmu)
 224                 cp15_control |= 0x1U;
 225
 226         if (d_u_cache || i_cache)
 227                 cp15_control |= 0x4U;
 228
 229         arm720t_write_cp15(target, 0xee010f10, cp15_control);
 230 }
 231
 232 void arm720t_post_debug_entry(target_t *target)
 233 {
 234         armv4_5_common_t *armv4_5 = target->arch_info;
 235         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 236         arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;
 237         arm720t_common_t *arm720t = arm7tdmi->arch_info;
 238
 239         /* examine cp15 control reg */
 240         arm720t_read_cp15(target, 0xee110f10, &arm720t->cp15_control_reg);
 241         jtag_execute_queue();
 242         LOG_DEBUG("cp15_control_reg: %8.8x", arm720t->cp15_control_reg);
 243
 244         arm720t->armv4_5_mmu.mmu_enabled = (arm720t->cp15_control_reg & 0x1U) ? 1 : 0;
 245         arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm720t->cp15_control_reg & 0x4U) ? 1 : 0;
 246         arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
 247
 248         /* save i/d fault status and address register */
 249         arm720t_read_cp15(target, 0xee150f10, &arm720t->fsr_reg);
 250         arm720t_read_cp15(target, 0xee160f10, &arm720t->far_reg);
 251         jtag_execute_queue();
 252 }
 253
 254 void arm720t_pre_restore_context(target_t *target)
 255 {
 256         armv4_5_common_t *armv4_5 = target->arch_info;
 257         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 258         arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;
 259         arm720t_common_t *arm720t = arm7tdmi->arch_info;
 260
 261         /* restore i/d fault status and address register */
 262         arm720t_write_cp15(target, 0xee050f10, arm720t->fsr_reg);
 263         arm720t_write_cp15(target, 0xee060f10, arm720t->far_reg);
 264 }
 265
 266 int arm720t_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p, arm7tdmi_common_t **arm7tdmi_p, arm720t_common_t **arm720t_p)
 267 {
 268         armv4_5_common_t *armv4_5 = target->arch_info;
 269         arm7_9_common_t *arm7_9;
 270         arm7tdmi_common_t *arm7tdmi;
 271         arm720t_common_t *arm720t;
 272
 273         if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
 274         {
 275                 return -1;
 276         }
 277
 278         arm7_9 = armv4_5->arch_info;
 279         if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
 280         {
 281                 return -1;
 282         }
 283
 284         arm7tdmi = arm7_9->arch_info;
 285         if (arm7tdmi->common_magic != ARM7TDMI_COMMON_MAGIC)
 286         {
 287                 return -1;
 288         }
 289
 290         arm720t = arm7tdmi->arch_info;
 291         if (arm720t->common_magic != ARM720T_COMMON_MAGIC)
 292         {
 293                 return -1;
 294         }
 295
 296         *armv4_5_p = armv4_5;
 297         *arm7_9_p = arm7_9;
 298         *arm7tdmi_p = arm7tdmi;
 299         *arm720t_p = arm720t;
 300
 301         return ERROR_OK;
 302 }
 303
 304 int arm720t_arch_state(struct target_s *target)
 305 {
 306         armv4_5_common_t *armv4_5 = target->arch_info;
 307         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 308         arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;
 309         arm720t_common_t *arm720t = arm7tdmi->arch_info;
 310
 311         char *state[] =
 312         {
 313                 "disabled", "enabled"
 314         };
 315
 316         if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
 317         {
 318                 LOG_ERROR("BUG: called for a non-ARMv4/5 target");
 319                 exit(-1);
 320         }
 321
 322         LOG_USER("target halted in %s state due to %s, current mode: %s\n"
 323                         "cpsr: 0x%8.8x pc: 0x%8.8x\n"
 324                         "MMU: %s, Cache: %s",
 325                          armv4_5_state_strings[armv4_5->core_state],
 326                          Jim_Nvp_value2name_simple( nvp_target_debug_reason, target->debug_reason )->name ,
 327                          armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)],
 328                          buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
 329                          buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
 330                          state[arm720t->armv4_5_mmu.mmu_enabled],
 331                          state[arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled]);
 332
 333         return ERROR_OK;
 334 }
 335
 336 int arm720t_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
 337 {
 338         int retval;
 339         armv4_5_common_t *armv4_5 = target->arch_info;
 340         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 341         arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;
 342         arm720t_common_t *arm720t = arm7tdmi->arch_info;
 343
 344         /* disable cache, but leave MMU enabled */
 345         if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
 346                 arm720t_disable_mmu_caches(target, 0, 1, 0);
 347
 348         retval = arm7_9_read_memory(target, address, size, count, buffer);
 349
 350         if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
 351                 arm720t_enable_mmu_caches(target, 0, 1, 0);
 352
 353         return retval;
 354 }
 355
 356 int arm720t_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
 357 {
 358         int retval;
 359
 360         if ((retval = arm7_9_write_memory(target, address, size, count, buffer)) != ERROR_OK)
 361                 return retval;
 362
 363         return retval;
 364 }
 365
 366 int arm720t_soft_reset_halt(struct target_s *target)
 367 {
 368         int retval = ERROR_OK;
 369         armv4_5_common_t *armv4_5 = target->arch_info;
 370         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 371         arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;
 372         arm720t_common_t *arm720t = arm7tdmi->arch_info;
 373         reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 374
 375         if ((retval = target_halt(target)) != ERROR_OK)
 376         {
 377                 return retval;
 378         }
 379
 380         long long then=timeval_ms();
 381         int timeout;
 382         while (!(timeout=((timeval_ms()-then)>1000)))
 383         {
 384                 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
 385                 {
 386                         embeddedice_read_reg(dbg_stat);
 387                         if ((retval = jtag_execute_queue()) != ERROR_OK)
 388                         {
 389                                 return retval;
 390                         }
 391                 } else
 392                 {
 393                         break;
 394                 }
 395                 if (debug_level>=3)
 396                 {
 397                         alive_sleep(100);
 398                 } else
 399                 {
 400                         keep_alive();
 401                 }
 402         }
 403         if (timeout)
 404         {
 405                 LOG_ERROR("Failed to halt CPU after 1 sec");
 406                 return ERROR_TARGET_TIMEOUT;
 407         }
 408
 409         target->state = TARGET_HALTED;
 410
 411         /* SVC, ARM state, IRQ and FIQ disabled */
 412         buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
 413         armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
 414         armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
 415
 416         /* start fetching from 0x0 */
 417         buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
 418         armv4_5->core_cache->reg_list[15].dirty = 1;
 419         armv4_5->core_cache->reg_list[15].valid = 1;
 420
 421         armv4_5->core_mode = ARMV4_5_MODE_SVC;
 422         armv4_5->core_state = ARMV4_5_STATE_ARM;
 423
 424         arm720t_disable_mmu_caches(target, 1, 1, 1);
 425         arm720t->armv4_5_mmu.mmu_enabled = 0;
 426         arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
 427         arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
 428
 429         if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
 430         {
 431                 return retval;
 432         }
 433
 434         return ERROR_OK;
 435 }
 436
 437 int arm720t_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
 438 {
 439         arm7tdmi_init_target(cmd_ctx, target);
 440
 441         return ERROR_OK;
 442 }
 443
 444 int arm720t_quit(void)
 445 {
 446         return ERROR_OK;
 447 }
 448
 449 int arm720t_init_arch_info(target_t *target, arm720t_common_t *arm720t, jtag_tap_t *tap)
 450 {
 451         arm7tdmi_common_t *arm7tdmi = &arm720t->arm7tdmi_common;
 452         arm7_9_common_t *arm7_9 = &arm7tdmi->arm7_9_common;
 453
 454         arm7tdmi_init_arch_info(target, arm7tdmi, tap);
 455
 456         arm7tdmi->arch_info = arm720t;
 457         arm720t->common_magic = ARM720T_COMMON_MAGIC;
 458
 459         arm7_9->post_debug_entry = arm720t_post_debug_entry;
 460         arm7_9->pre_restore_context = arm720t_pre_restore_context;
 461
 462         arm720t->armv4_5_mmu.armv4_5_cache.ctype = -1;
 463         arm720t->armv4_5_mmu.get_ttb = arm720t_get_ttb;
 464         arm720t->armv4_5_mmu.read_memory = arm7_9_read_memory;
 465         arm720t->armv4_5_mmu.write_memory = arm7_9_write_memory;
 466         arm720t->armv4_5_mmu.disable_mmu_caches = arm720t_disable_mmu_caches;
 467         arm720t->armv4_5_mmu.enable_mmu_caches = arm720t_enable_mmu_caches;
 468         arm720t->armv4_5_mmu.has_tiny_pages = 0;
 469         arm720t->armv4_5_mmu.mmu_enabled = 0;
 470
 471         return ERROR_OK;
 472 }
 473
 474 int arm720t_target_create(struct target_s *target, Jim_Interp *interp)
 475 {
 476         arm720t_common_t *arm720t = calloc(1,sizeof(arm720t_common_t));
 477
 478         arm720t_init_arch_info(target, arm720t, target->tap);
 479
 480         return ERROR_OK;
 481 }
 482
 483 int arm720t_register_commands(struct command_context_s *cmd_ctx)
 484 {
 485         int retval;
 486         command_t *arm720t_cmd;
 487
 488
 489         retval = arm7tdmi_register_commands(cmd_ctx);
 490
 491         arm720t_cmd = register_command(cmd_ctx, NULL, "arm720t", NULL, COMMAND_ANY, "arm720t specific commands");
 492
 493         register_command(cmd_ctx, arm720t_cmd, "cp15", arm720t_handle_cp15_command, COMMAND_EXEC, "display/modify cp15 register <opcode> [value]");
 494         register_command(cmd_ctx, arm720t_cmd, "virt2phys", arm720t_handle_virt2phys_command, COMMAND_EXEC, "translate va to pa <va>");
 495
 496         register_command(cmd_ctx, arm720t_cmd, "mdw_phys", arm720t_handle_md_phys_command, COMMAND_EXEC, "display memory words <physical addr> [count]");
 497         register_command(cmd_ctx, arm720t_cmd, "mdh_phys", arm720t_handle_md_phys_command, COMMAND_EXEC, "display memory half-words <physical addr> [count]");
 498         register_command(cmd_ctx, arm720t_cmd, "mdb_phys", arm720t_handle_md_phys_command, COMMAND_EXEC, "display memory bytes <physical addr> [count]");
 499
 500         register_command(cmd_ctx, arm720t_cmd, "mww_phys", arm720t_handle_mw_phys_command, COMMAND_EXEC, "write memory word <physical addr> <value>");
 501         register_command(cmd_ctx, arm720t_cmd, "mwh_phys", arm720t_handle_mw_phys_command, COMMAND_EXEC, "write memory half-word <physical addr> <value>");
 502         register_command(cmd_ctx, arm720t_cmd, "mwb_phys", arm720t_handle_mw_phys_command, COMMAND_EXEC, "write memory byte <physical addr> <value>");
 503
 504         return ERROR_OK;
 505 }
 506
 507 int arm720t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 508 {
 509         int retval;
 510         target_t *target = get_current_target(cmd_ctx);
 511         armv4_5_common_t *armv4_5;
 512         arm7_9_common_t *arm7_9;
 513         arm7tdmi_common_t *arm7tdmi;
 514         arm720t_common_t *arm720t;
 515         arm_jtag_t *jtag_info;
 516
 517         if (arm720t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm7tdmi, &arm720t) != ERROR_OK)
 518         {
 519                 command_print(cmd_ctx, "current target isn't an ARM720t target");
 520                 return ERROR_OK;
 521         }
 522
 523         jtag_info = &arm7_9->jtag_info;
 524
 525         if (target->state != TARGET_HALTED)
 526         {
 527                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
 528                 return ERROR_OK;
 529         }
 530
 531         /* one or more argument, access a single register (write if second argument is given */
 532         if (argc >= 1)
 533         {
 534                 u32 opcode = strtoul(args[0], NULL, 0);
 535
 536                 if (argc == 1)
 537                 {
 538                         u32 value;
 539                         if ((retval = arm720t_read_cp15(target, opcode, &value)) != ERROR_OK)
 540                         {
 541                                 command_print(cmd_ctx, "couldn't access cp15 with opcode 0x%8.8x", opcode);
 542                                 return ERROR_OK;
 543                         }
 544
 545                         if ((retval = jtag_execute_queue()) != ERROR_OK)
 546                         {
 547                                 return retval;
 548                         }
 549
 550                         command_print(cmd_ctx, "0x%8.8x: 0x%8.8x", opcode, value);
 551                 }
 552                 else if (argc == 2)
 553                 {
 554                         u32 value = strtoul(args[1], NULL, 0);
 555                         if ((retval = arm720t_write_cp15(target, opcode, value)) != ERROR_OK)
 556                         {
 557                                 command_print(cmd_ctx, "couldn't access cp15 with opcode 0x%8.8x", opcode);
 558                                 return ERROR_OK;
 559                         }
 560                         command_print(cmd_ctx, "0x%8.8x: 0x%8.8x", opcode, value);
 561                 }
 562         }
 563
 564         return ERROR_OK;
 565 }
 566
 567 int arm720t_handle_virt2phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
 568 {
 569         target_t *target = get_current_target(cmd_ctx);
 570         armv4_5_common_t *armv4_5;
 571         arm7_9_common_t *arm7_9;
 572         arm7tdmi_common_t *arm7tdmi;
 573         arm720t_common_t *arm720t;
 574         arm_jtag_t *jtag_info;
 575
 576         if (arm720t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm7tdmi, &arm720t) != ERROR_OK)
 577         {
 578                 command_print(cmd_ctx, "current target isn't an ARM720t target");
 579                 return ERROR_OK;
 580         }
 581
 582         jtag_info = &arm7_9->jtag_info;
 583
 584         if (target->state != TARGET_HALTED)
 585         {
 586                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
 587                 return ERROR_OK;
 588         }
 589
 590         return armv4_5_mmu_handle_virt2phys_command(cmd_ctx, cmd, args, argc, target, &arm720t->armv4_5_mmu);
 591 }
 592
 593 int arm720t_handle_md_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
 594 {
 595         target_t *target = get_current_target(cmd_ctx);
 596         armv4_5_common_t *armv4_5;
 597         arm7_9_common_t *arm7_9;
 598         arm7tdmi_common_t *arm7tdmi;
 599         arm720t_common_t *arm720t;
 600         arm_jtag_t *jtag_info;
 601
 602         if (arm720t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm7tdmi, &arm720t) != ERROR_OK)
 603         {
 604                 command_print(cmd_ctx, "current target isn't an ARM720t target");
 605                 return ERROR_OK;
 606         }
 607
 608         jtag_info = &arm7_9->jtag_info;
 609
 610         if (target->state != TARGET_HALTED)
 611         {
 612                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
 613                 return ERROR_OK;
 614         }
 615
 616         return armv4_5_mmu_handle_md_phys_command(cmd_ctx, cmd, args, argc, target, &arm720t->armv4_5_mmu);
 617 }
 618
 619 int arm720t_handle_mw_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
 620 {
 621         target_t *target = get_current_target(cmd_ctx);
 622         armv4_5_common_t *armv4_5;
 623         arm7_9_common_t *arm7_9;
 624         arm7tdmi_common_t *arm7tdmi;
 625         arm720t_common_t *arm720t;
 626         arm_jtag_t *jtag_info;
 627
 628         if (arm720t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm7tdmi, &arm720t) != ERROR_OK)
 629         {
 630                 command_print(cmd_ctx, "current target isn't an ARM720t target");
 631                 return ERROR_OK;
 632         }
 633
 634         jtag_info = &arm7_9->jtag_info;
 635
 636         if (target->state != TARGET_HALTED)
 637         {
 638                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
 639                 return ERROR_OK;
 640         }
 641
 642         return armv4_5_mmu_handle_mw_phys_command(cmd_ctx, cmd, args, argc, target, &arm720t->armv4_5_mmu);
 643 }