7f2b4038062b6d26cd1f9ad807d007112931973f
[openocd.git] / src / target / arm720t.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2009 by √ėyvind Harboe *
6 * oyvind.harboe@zylin.com *
7 * *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
12 * *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
17 * *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
23 #ifdef HAVE_CONFIG_H
24 #include "config.h"
25 #endif
26
27 #include "arm720t.h"
28 #include "time_support.h"
29 #include "target_type.h"
30
31
32 /*
33 * ARM720 is an ARM7TDMI-S with MMU and ETM7. For information, see
34 * ARM DDI 0229C especially Chapter 9 about debug support.
35 */
36
37 #if 0
38 #define _DEBUG_INSTRUCTION_EXECUTION_
39 #endif
40
41 static int arm720t_scan_cp15(target_t *target,
42 uint32_t out, uint32_t *in, int instruction, int clock)
43 {
44 int retval;
45 struct arm720t_common *arm720t = target_to_arm720(target);
46 struct arm_jtag *jtag_info;
47 struct scan_field fields[2];
48 uint8_t out_buf[4];
49 uint8_t instruction_buf = instruction;
50
51 jtag_info = &arm720t->arm7tdmi_common.arm7_9_common.jtag_info;
52
53 buf_set_u32(out_buf, 0, 32, flip_u32(out, 32));
54
55 jtag_set_end_state(TAP_DRPAUSE);
56 if ((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
57 {
58 return retval;
59 }
60 if ((retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL)) != ERROR_OK)
61 {
62 return retval;
63 }
64
65 fields[0].tap = jtag_info->tap;
66 fields[0].num_bits = 1;
67 fields[0].out_value = &instruction_buf;
68 fields[0].in_value = NULL;
69
70 fields[1].tap = jtag_info->tap;
71 fields[1].num_bits = 32;
72 fields[1].out_value = out_buf;
73 fields[1].in_value = NULL;
74
75 if (in)
76 {
77 fields[1].in_value = (uint8_t *)in;
78 jtag_add_dr_scan(2, fields, jtag_get_end_state());
79 jtag_add_callback(arm7flip32, (jtag_callback_data_t)in);
80 } else
81 {
82 jtag_add_dr_scan(2, fields, jtag_get_end_state());
83 }
84
85 if (clock)
86 jtag_add_runtest(0, jtag_get_end_state());
87
88 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
89 if ((retval = jtag_execute_queue()) != ERROR_OK)
90 {
91 return retval;
92 }
93
94 if (in)
95 LOG_DEBUG("out: %8.8x, in: %8.8x, instruction: %i, clock: %i", out, *in, instruction, clock);
96 else
97 LOG_DEBUG("out: %8.8x, instruction: %i, clock: %i", out, instruction, clock);
98 #else
99 LOG_DEBUG("out: %8.8" PRIx32 ", instruction: %i, clock: %i", out, instruction, clock);
100 #endif
101
102 return ERROR_OK;
103 }
104
105 static int arm720t_read_cp15(target_t *target, uint32_t opcode, uint32_t *value)
106 {
107 /* fetch CP15 opcode */
108 arm720t_scan_cp15(target, opcode, NULL, 1, 1);
109 /* "DECODE" stage */
110 arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 1);
111 /* "EXECUTE" stage (1) */
112 arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 0);
113 arm720t_scan_cp15(target, 0x0, NULL, 0, 1);
114 /* "EXECUTE" stage (2) */
115 arm720t_scan_cp15(target, 0x0, NULL, 0, 1);
116 /* "EXECUTE" stage (3), CDATA is read */
117 arm720t_scan_cp15(target, ARMV4_5_NOP, value, 1, 1);
118
119 return ERROR_OK;
120 }
121
122 static int arm720t_write_cp15(target_t *target, uint32_t opcode, uint32_t value)
123 {
124 /* fetch CP15 opcode */
125 arm720t_scan_cp15(target, opcode, NULL, 1, 1);
126 /* "DECODE" stage */
127 arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 1);
128 /* "EXECUTE" stage (1) */
129 arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 0);
130 arm720t_scan_cp15(target, 0x0, NULL, 0, 1);
131 /* "EXECUTE" stage (2) */
132 arm720t_scan_cp15(target, value, NULL, 0, 1);
133 arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 1);
134
135 return ERROR_OK;
136 }
137
138 static uint32_t arm720t_get_ttb(target_t *target)
139 {
140 uint32_t ttb = 0x0;
141
142 arm720t_read_cp15(target, 0xee120f10, &ttb);
143 jtag_execute_queue();
144
145 ttb &= 0xffffc000;
146
147 return ttb;
148 }
149
150 static void arm720t_disable_mmu_caches(target_t *target,
151 int mmu, int d_u_cache, int i_cache)
152 {
153 uint32_t cp15_control;
154
155 /* read cp15 control register */
156 arm720t_read_cp15(target, 0xee110f10, &cp15_control);
157 jtag_execute_queue();
158
159 if (mmu)
160 cp15_control &= ~0x1U;
161
162 if (d_u_cache || i_cache)
163 cp15_control &= ~0x4U;
164
165 arm720t_write_cp15(target, 0xee010f10, cp15_control);
166 }
167
168 static void arm720t_enable_mmu_caches(target_t *target,
169 int mmu, int d_u_cache, int i_cache)
170 {
171 uint32_t cp15_control;
172
173 /* read cp15 control register */
174 arm720t_read_cp15(target, 0xee110f10, &cp15_control);
175 jtag_execute_queue();
176
177 if (mmu)
178 cp15_control |= 0x1U;
179
180 if (d_u_cache || i_cache)
181 cp15_control |= 0x4U;
182
183 arm720t_write_cp15(target, 0xee010f10, cp15_control);
184 }
185
186 static void arm720t_post_debug_entry(target_t *target)
187 {
188 struct arm720t_common *arm720t = target_to_arm720(target);
189
190 /* examine cp15 control reg */
191 arm720t_read_cp15(target, 0xee110f10, &arm720t->cp15_control_reg);
192 jtag_execute_queue();
193 LOG_DEBUG("cp15_control_reg: %8.8" PRIx32 "", arm720t->cp15_control_reg);
194
195 arm720t->armv4_5_mmu.mmu_enabled = (arm720t->cp15_control_reg & 0x1U) ? 1 : 0;
196 arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm720t->cp15_control_reg & 0x4U) ? 1 : 0;
197 arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
198
199 /* save i/d fault status and address register */
200 arm720t_read_cp15(target, 0xee150f10, &arm720t->fsr_reg);
201 arm720t_read_cp15(target, 0xee160f10, &arm720t->far_reg);
202 jtag_execute_queue();
203 }
204
205 static void arm720t_pre_restore_context(target_t *target)
206 {
207 struct arm720t_common *arm720t = target_to_arm720(target);
208
209 /* restore i/d fault status and address register */
210 arm720t_write_cp15(target, 0xee050f10, arm720t->fsr_reg);
211 arm720t_write_cp15(target, 0xee060f10, arm720t->far_reg);
212 }
213
214 static int arm720t_verify_pointer(struct command_context_s *cmd_ctx,
215 struct arm720t_common *arm720t)
216 {
217 if (arm720t->common_magic != ARM720T_COMMON_MAGIC) {
218 command_print(cmd_ctx, "target is not an ARM720");
219 return ERROR_TARGET_INVALID;
220 }
221 return ERROR_OK;
222 }
223
224 static int arm720t_arch_state(struct target_s *target)
225 {
226 struct arm720t_common *arm720t = target_to_arm720(target);
227 struct armv4_5_common_s *armv4_5;
228
229 static const char *state[] =
230 {
231 "disabled", "enabled"
232 };
233
234 armv4_5 = &arm720t->arm7tdmi_common.arm7_9_common.armv4_5_common;
235
236 LOG_USER("target halted in %s state due to %s, current mode: %s\n"
237 "cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n"
238 "MMU: %s, Cache: %s",
239 armv4_5_state_strings[armv4_5->core_state],
240 Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name ,
241 armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)],
242 buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
243 buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
244 state[arm720t->armv4_5_mmu.mmu_enabled],
245 state[arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled]);
246
247 return ERROR_OK;
248 }
249
250 static int arm720_mmu(struct target_s *target, int *enabled)
251 {
252 if (target->state != TARGET_HALTED) {
253 LOG_ERROR("%s: target not halted", __func__);
254 return ERROR_TARGET_INVALID;
255 }
256
257 *enabled = target_to_arm720(target)->armv4_5_mmu.mmu_enabled;
258 return ERROR_OK;
259 }
260
261 static int arm720_virt2phys(struct target_s *target,
262 uint32_t virt, uint32_t *phys)
263 {
264 /** @todo Implement this! */
265 LOG_ERROR("%s: not implemented", __func__);
266 return ERROR_FAIL;
267 }
268
269 static int arm720t_read_memory(struct target_s *target,
270 uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
271 {
272 int retval;
273 struct arm720t_common *arm720t = target_to_arm720(target);
274
275 /* disable cache, but leave MMU enabled */
276 if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
277 arm720t_disable_mmu_caches(target, 0, 1, 0);
278
279 retval = arm7_9_read_memory(target, address, size, count, buffer);
280
281 if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
282 arm720t_enable_mmu_caches(target, 0, 1, 0);
283
284 return retval;
285 }
286
287 static int arm720t_read_phys_memory(struct target_s *target,
288 uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
289 {
290 struct arm720t_common *arm720t = target_to_arm720(target);
291
292 return armv4_5_mmu_read_physical(target, &arm720t->armv4_5_mmu, address, size, count, buffer);
293 }
294
295 static int arm720t_write_phys_memory(struct target_s *target,
296 uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
297 {
298 struct arm720t_common *arm720t = target_to_arm720(target);
299
300 return armv4_5_mmu_write_physical(target, &arm720t->armv4_5_mmu, address, size, count, buffer);
301 }
302
303 static int arm720t_soft_reset_halt(struct target_s *target)
304 {
305 int retval = ERROR_OK;
306 struct arm720t_common *arm720t = target_to_arm720(target);
307 struct reg *dbg_stat = &arm720t->arm7tdmi_common.arm7_9_common
308 .eice_cache->reg_list[EICE_DBG_STAT];
309 struct armv4_5_common_s *armv4_5 = &arm720t->arm7tdmi_common
310 .arm7_9_common.armv4_5_common;
311
312 if ((retval = target_halt(target)) != ERROR_OK)
313 {
314 return retval;
315 }
316
317 long long then = timeval_ms();
318 int timeout;
319 while (!(timeout = ((timeval_ms()-then) > 1000)))
320 {
321 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
322 {
323 embeddedice_read_reg(dbg_stat);
324 if ((retval = jtag_execute_queue()) != ERROR_OK)
325 {
326 return retval;
327 }
328 } else
329 {
330 break;
331 }
332 if (debug_level >= 3)
333 {
334 alive_sleep(100);
335 } else
336 {
337 keep_alive();
338 }
339 }
340 if (timeout)
341 {
342 LOG_ERROR("Failed to halt CPU after 1 sec");
343 return ERROR_TARGET_TIMEOUT;
344 }
345
346 target->state = TARGET_HALTED;
347
348 /* SVC, ARM state, IRQ and FIQ disabled */
349 buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
350 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
351 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
352
353 /* start fetching from 0x0 */
354 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
355 armv4_5->core_cache->reg_list[15].dirty = 1;
356 armv4_5->core_cache->reg_list[15].valid = 1;
357
358 armv4_5->core_mode = ARMV4_5_MODE_SVC;
359 armv4_5->core_state = ARMV4_5_STATE_ARM;
360
361 arm720t_disable_mmu_caches(target, 1, 1, 1);
362 arm720t->armv4_5_mmu.mmu_enabled = 0;
363 arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
364 arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
365
366 if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
367 {
368 return retval;
369 }
370
371 return ERROR_OK;
372 }
373
374 static int arm720t_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
375 {
376 return arm7tdmi_init_target(cmd_ctx, target);
377 }
378
379 static int arm720t_init_arch_info(target_t *target,
380 struct arm720t_common *arm720t, struct jtag_tap *tap)
381 {
382 struct arm7tdmi_common *arm7tdmi = &arm720t->arm7tdmi_common;
383 struct arm7_9_common *arm7_9 = &arm7tdmi->arm7_9_common;
384
385 arm7tdmi_init_arch_info(target, arm7tdmi, tap);
386
387 arm720t->common_magic = ARM720T_COMMON_MAGIC;
388
389 arm7_9->post_debug_entry = arm720t_post_debug_entry;
390 arm7_9->pre_restore_context = arm720t_pre_restore_context;
391
392 arm720t->armv4_5_mmu.armv4_5_cache.ctype = -1;
393 arm720t->armv4_5_mmu.get_ttb = arm720t_get_ttb;
394 arm720t->armv4_5_mmu.read_memory = arm7_9_read_memory;
395 arm720t->armv4_5_mmu.write_memory = arm7_9_write_memory;
396 arm720t->armv4_5_mmu.disable_mmu_caches = arm720t_disable_mmu_caches;
397 arm720t->armv4_5_mmu.enable_mmu_caches = arm720t_enable_mmu_caches;
398 arm720t->armv4_5_mmu.has_tiny_pages = 0;
399 arm720t->armv4_5_mmu.mmu_enabled = 0;
400
401 return ERROR_OK;
402 }
403
404 static int arm720t_target_create(struct target_s *target, Jim_Interp *interp)
405 {
406 struct arm720t_common *arm720t = calloc(1, sizeof(*arm720t));
407
408 arm720t->arm7tdmi_common.arm7_9_common.armv4_5_common.is_armv4 = true;
409 return arm720t_init_arch_info(target, arm720t, target->tap);
410 }
411
412 COMMAND_HANDLER(arm720t_handle_cp15_command)
413 {
414 int retval;
415 target_t *target = get_current_target(cmd_ctx);
416 struct arm720t_common *arm720t = target_to_arm720(target);
417 struct arm_jtag *jtag_info;
418
419 retval = arm720t_verify_pointer(cmd_ctx, arm720t);
420 if (retval != ERROR_OK)
421 return retval;
422
423 jtag_info = &arm720t->arm7tdmi_common.arm7_9_common.jtag_info;
424
425 if (target->state != TARGET_HALTED)
426 {
427 command_print(cmd_ctx, "target must be stopped for \"%s\" command", CMD_NAME);
428 return ERROR_OK;
429 }
430
431 /* one or more argument, access a single register (write if second argument is given */
432 if (argc >= 1)
433 {
434 uint32_t opcode;
435 COMMAND_PARSE_NUMBER(u32, args[0], opcode);
436
437 if (argc == 1)
438 {
439 uint32_t value;
440 if ((retval = arm720t_read_cp15(target, opcode, &value)) != ERROR_OK)
441 {
442 command_print(cmd_ctx, "couldn't access cp15 with opcode 0x%8.8" PRIx32 "", opcode);
443 return ERROR_OK;
444 }
445
446 if ((retval = jtag_execute_queue()) != ERROR_OK)
447 {
448 return retval;
449 }
450
451 command_print(cmd_ctx, "0x%8.8" PRIx32 ": 0x%8.8" PRIx32 "", opcode, value);
452 }
453 else if (argc == 2)
454 {
455 uint32_t value;
456 COMMAND_PARSE_NUMBER(u32, args[1], value);
457
458 if ((retval = arm720t_write_cp15(target, opcode, value)) != ERROR_OK)
459 {
460 command_print(cmd_ctx, "couldn't access cp15 with opcode 0x%8.8" PRIx32 "", opcode);
461 return ERROR_OK;
462 }
463 command_print(cmd_ctx, "0x%8.8" PRIx32 ": 0x%8.8" PRIx32 "", opcode, value);
464 }
465 }
466
467 return ERROR_OK;
468 }
469
470 static int arm720t_mrc(target_t *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value)
471 {
472 if (cpnum!=15)
473 {
474 LOG_ERROR("Only cp15 is supported");
475 return ERROR_FAIL;
476 }
477
478 return arm720t_read_cp15(target, mrc_opcode(cpnum, op1, op2, CRn, CRm), value);
479
480 }
481
482 static int arm720t_mcr(target_t *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value)
483 {
484 if (cpnum!=15)
485 {
486 LOG_ERROR("Only cp15 is supported");
487 return ERROR_FAIL;
488 }
489
490 return arm720t_write_cp15(target, mrc_opcode(cpnum, op1, op2, CRn, CRm), value);
491 }
492
493 static int arm720t_register_commands(struct command_context_s *cmd_ctx)
494 {
495 int retval;
496 command_t *arm720t_cmd;
497
498
499 retval = arm7_9_register_commands(cmd_ctx);
500
501 arm720t_cmd = register_command(cmd_ctx, NULL, "arm720t",
502 NULL, COMMAND_ANY,
503 "arm720t specific commands");
504
505 register_command(cmd_ctx, arm720t_cmd, "cp15",
506 arm720t_handle_cp15_command, COMMAND_EXEC,
507 "display/modify cp15 register <opcode> [value]");
508
509 return ERROR_OK;
510 }
511
512 /** Holds methods for ARM720 targets. */
513 struct target_type arm720t_target =
514 {
515 .name = "arm720t",
516
517 .poll = arm7_9_poll,
518 .arch_state = arm720t_arch_state,
519
520 .halt = arm7_9_halt,
521 .resume = arm7_9_resume,
522 .step = arm7_9_step,
523
524 .assert_reset = arm7_9_assert_reset,
525 .deassert_reset = arm7_9_deassert_reset,
526 .soft_reset_halt = arm720t_soft_reset_halt,
527
528 .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
529
530 .read_memory = arm720t_read_memory,
531 .write_memory = arm7_9_write_memory,
532 .read_phys_memory = arm720t_read_phys_memory,
533 .write_phys_memory = arm720t_write_phys_memory,
534 .mmu = arm720_mmu,
535 .virt2phys = arm720_virt2phys,
536
537 .bulk_write_memory = arm7_9_bulk_write_memory,
538 .checksum_memory = arm7_9_checksum_memory,
539 .blank_check_memory = arm7_9_blank_check_memory,
540
541 .run_algorithm = armv4_5_run_algorithm,
542
543 .add_breakpoint = arm7_9_add_breakpoint,
544 .remove_breakpoint = arm7_9_remove_breakpoint,
545 .add_watchpoint = arm7_9_add_watchpoint,
546 .remove_watchpoint = arm7_9_remove_watchpoint,
547
548 .register_commands = arm720t_register_commands,
549 .target_create = arm720t_target_create,
550 .init_target = arm720t_init_target,
551 .examine = arm7tdmi_examine,
552 .mrc = arm720t_mrc,
553 .mcr = arm720t_mcr,
554
555 };