- prepare OpenOCD for branching, created ./trunk/
[openocd.git] / src / target / arm720t.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
20 #include "config.h"
21
22 #include "arm720t.h"
23 #include "jtag.h"
24 #include "log.h"
25
26 #include <stdlib.h>
27 #include <string.h>
28
29 #if 1
30 #define _DEBUG_INSTRUCTION_EXECUTION_
31 #endif
32
33 /* cli handling */
34 int arm720t_register_commands(struct command_context_s *cmd_ctx);
35
36 int arm720t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
37 int arm720t_handle_virt2phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
38 int arm720t_handle_md_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
39 int arm720t_handle_mw_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
40
41 /* forward declarations */
42 int arm720t_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target);
43 int arm720t_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
44 int arm720t_quit();
45 int arm720t_arch_state(struct target_s *target, char *buf, int buf_size);
46 int arm720t_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
47 int arm720t_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
48 int arm720t_soft_reset_halt(struct target_s *target);
49
50 target_type_t arm720t_target =
51 {
52 .name = "arm720t",
53
54 .poll = arm7_9_poll,
55 .arch_state = arm720t_arch_state,
56
57 .halt = arm7_9_halt,
58 .resume = arm7_9_resume,
59 .step = arm7_9_step,
60
61 .assert_reset = arm7_9_assert_reset,
62 .deassert_reset = arm7_9_deassert_reset,
63 .soft_reset_halt = arm720t_soft_reset_halt,
64
65 .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
66
67 .read_memory = arm720t_read_memory,
68 .write_memory = arm720t_write_memory,
69 .bulk_write_memory = arm7_9_bulk_write_memory,
70
71 .run_algorithm = armv4_5_run_algorithm,
72
73 .add_breakpoint = arm7_9_add_breakpoint,
74 .remove_breakpoint = arm7_9_remove_breakpoint,
75 .add_watchpoint = arm7_9_add_watchpoint,
76 .remove_watchpoint = arm7_9_remove_watchpoint,
77
78 .register_commands = arm720t_register_commands,
79 .target_command = arm720t_target_command,
80 .init_target = arm720t_init_target,
81 .quit = arm720t_quit
82 };
83
84 int arm720t_scan_cp15(target_t *target, u32 out, u32 *in, int instruction, int clock)
85 {
86 armv4_5_common_t *armv4_5 = target->arch_info;
87 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
88 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
89 scan_field_t fields[2];
90 u8 out_buf[4];
91 u8 instruction_buf = instruction;
92
93 out = flip_u32(out, 32);
94 buf_set_u32(out_buf, 0, 32, out);
95
96 jtag_add_end_state(TAP_PD);
97 arm_jtag_scann(jtag_info, 0xf);
98 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr);
99
100 fields[0].device = jtag_info->chain_pos;
101 fields[0].num_bits = 1;
102 fields[0].out_value = &instruction_buf;
103 fields[0].out_mask = NULL;
104 fields[0].in_value = NULL;
105 fields[0].in_check_value = NULL;
106 fields[0].in_check_mask = NULL;
107 fields[0].in_handler = NULL;
108 fields[0].in_handler_priv = NULL;
109
110 fields[1].device = jtag_info->chain_pos;
111 fields[1].num_bits = 32;
112 fields[1].out_value = out_buf;
113 fields[1].out_mask = NULL;
114 if (in)
115 {
116 fields[1].in_value = (u8*)in;
117 fields[1].in_handler = arm_jtag_buf_to_u32_flip;
118 fields[1].in_handler_priv = in;
119 } else
120 {
121 fields[1].in_value = NULL;
122 fields[1].in_handler = NULL;
123 fields[1].in_handler_priv = NULL;
124 }
125 fields[1].in_check_value = NULL;
126 fields[1].in_check_mask = NULL;
127
128 jtag_add_dr_scan(2, fields, -1);
129
130 if (clock)
131 jtag_add_runtest(0, -1);
132
133 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
134 jtag_execute_queue();
135
136 if (in)
137 DEBUG("out: %8.8x, in: %8.8x, instruction: %i, clock: %i", out, *in, instruction, clock);
138 else
139 DEBUG("out: %8.8x, instruction: %i, clock: %i", out, instruction, clock);
140 #else
141 DEBUG("out: %8.8x, instruction: %i, clock: %i", in, out, instruction, clock);
142 #endif
143
144 return ERROR_OK;
145 }
146
147 int arm720t_read_cp15(target_t *target, u32 opcode, u32 *value)
148 {
149 /* fetch CP15 opcode */
150 arm720t_scan_cp15(target, opcode, NULL, 1, 1);
151 /* "DECODE" stage */
152 arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 1);
153 /* "EXECUTE" stage (1) */
154 arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 0);
155 arm720t_scan_cp15(target, 0x0, NULL, 0, 1);
156 /* "EXECUTE" stage (2) */
157 arm720t_scan_cp15(target, 0x0, NULL, 0, 1);
158 /* "EXECUTE" stage (3), CDATA is read */
159 arm720t_scan_cp15(target, ARMV4_5_NOP, value, 1, 1);
160
161 return ERROR_OK;
162 }
163
164 int arm720t_write_cp15(target_t *target, u32 opcode, u32 value)
165 {
166 /* fetch CP15 opcode */
167 arm720t_scan_cp15(target, opcode, NULL, 1, 1);
168 /* "DECODE" stage */
169 arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 1);
170 /* "EXECUTE" stage (1) */
171 arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 0);
172 arm720t_scan_cp15(target, 0x0, NULL, 0, 1);
173 /* "EXECUTE" stage (2) */
174 arm720t_scan_cp15(target, value, NULL, 0, 1);
175 arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 1);
176
177 return ERROR_OK;
178 }
179
180 u32 arm720t_get_ttb(target_t *target)
181 {
182 u32 ttb = 0x0;
183
184 arm720t_read_cp15(target, 0xee120f10, &ttb);
185 jtag_execute_queue();
186
187 ttb &= 0xffffc000;
188
189 return ttb;
190 }
191
192 void arm720t_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
193 {
194 u32 cp15_control;
195
196 /* read cp15 control register */
197 arm720t_read_cp15(target, 0xee110f10, &cp15_control);
198 jtag_execute_queue();
199
200 if (mmu)
201 cp15_control &= ~0x1U;
202
203 if (d_u_cache || i_cache)
204 cp15_control &= ~0x4U;
205
206 arm720t_write_cp15(target, 0xee010f10, cp15_control);
207 }
208
209 void arm720t_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
210 {
211 u32 cp15_control;
212
213 /* read cp15 control register */
214 arm720t_read_cp15(target, 0xee110f10, &cp15_control);
215 jtag_execute_queue();
216
217 if (mmu)
218 cp15_control |= 0x1U;
219
220 if (d_u_cache || i_cache)
221 cp15_control |= 0x4U;
222
223 arm720t_write_cp15(target, 0xee010f10, cp15_control);
224 }
225
226 void arm720t_post_debug_entry(target_t *target)
227 {
228 armv4_5_common_t *armv4_5 = target->arch_info;
229 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
230 arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;
231 arm720t_common_t *arm720t = arm7tdmi->arch_info;
232
233 /* examine cp15 control reg */
234 arm720t_read_cp15(target, 0xee110f10, &arm720t->cp15_control_reg);
235 jtag_execute_queue();
236 DEBUG("cp15_control_reg: %8.8x", arm720t->cp15_control_reg);
237
238 arm720t->armv4_5_mmu.mmu_enabled = (arm720t->cp15_control_reg & 0x1U) ? 1 : 0;
239 arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm720t->cp15_control_reg & 0x4U) ? 1 : 0;
240 arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
241
242 /* save i/d fault status and address register */
243 arm720t_read_cp15(target, 0xee150f10, &arm720t->fsr);
244 arm720t_read_cp15(target, 0xee160f10, &arm720t->far);
245 jtag_execute_queue();
246 }
247
248 void arm720t_pre_restore_context(target_t *target)
249 {
250 armv4_5_common_t *armv4_5 = target->arch_info;
251 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
252 arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;
253 arm720t_common_t *arm720t = arm7tdmi->arch_info;
254
255 /* restore i/d fault status and address register */
256 arm720t_write_cp15(target, 0xee050f10, arm720t->fsr);
257 arm720t_write_cp15(target, 0xee060f10, arm720t->far);
258 }
259
260 int arm720t_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p, arm7tdmi_common_t **arm7tdmi_p, arm720t_common_t **arm720t_p)
261 {
262 armv4_5_common_t *armv4_5 = target->arch_info;
263 arm7_9_common_t *arm7_9;
264 arm7tdmi_common_t *arm7tdmi;
265 arm720t_common_t *arm720t;
266
267 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
268 {
269 return -1;
270 }
271
272 arm7_9 = armv4_5->arch_info;
273 if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
274 {
275 return -1;
276 }
277
278 arm7tdmi = arm7_9->arch_info;
279 if (arm7tdmi->common_magic != ARM7TDMI_COMMON_MAGIC)
280 {
281 return -1;
282 }
283
284 arm720t = arm7tdmi->arch_info;
285 if (arm720t->common_magic != ARM720T_COMMON_MAGIC)
286 {
287 return -1;
288 }
289
290 *armv4_5_p = armv4_5;
291 *arm7_9_p = arm7_9;
292 *arm7tdmi_p = arm7tdmi;
293 *arm720t_p = arm720t;
294
295 return ERROR_OK;
296 }
297
298 int arm720t_arch_state(struct target_s *target, char *buf, int buf_size)
299 {
300 armv4_5_common_t *armv4_5 = target->arch_info;
301 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
302 arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;
303 arm720t_common_t *arm720t = arm7tdmi->arch_info;
304
305 char *state[] =
306 {
307 "disabled", "enabled"
308 };
309
310 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
311 {
312 ERROR("BUG: called for a non-ARMv4/5 target");
313 exit(-1);
314 }
315
316 snprintf(buf, buf_size,
317 "target halted in %s state due to %s, current mode: %s\n"
318 "cpsr: 0x%8.8x pc: 0x%8.8x\n"
319 "MMU: %s, Cache: %s",
320 armv4_5_state_strings[armv4_5->core_state],
321 target_debug_reason_strings[target->debug_reason],
322 armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)],
323 buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
324 buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
325 state[arm720t->armv4_5_mmu.mmu_enabled],
326 state[arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled]);
327
328 return ERROR_OK;
329 }
330
331 int arm720t_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
332 {
333 int retval;
334 armv4_5_common_t *armv4_5 = target->arch_info;
335 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
336 arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;
337 arm720t_common_t *arm720t = arm7tdmi->arch_info;
338
339 /* disable cache, but leave MMU enabled */
340 if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
341 arm720t_disable_mmu_caches(target, 0, 1, 0);
342
343 retval = arm7_9_read_memory(target, address, size, count, buffer);
344
345 if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
346 arm720t_enable_mmu_caches(target, 0, 1, 0);
347
348 return retval;
349 }
350
351 int arm720t_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
352 {
353 int retval;
354
355 if ((retval = arm7_9_write_memory(target, address, size, count, buffer)) != ERROR_OK)
356 return retval;
357
358 return retval;
359 }
360
361 int arm720t_soft_reset_halt(struct target_s *target)
362 {
363 armv4_5_common_t *armv4_5 = target->arch_info;
364 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
365 arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;
366 arm720t_common_t *arm720t = arm7tdmi->arch_info;
367 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
368
369 if (target->state == TARGET_RUNNING)
370 {
371 target->type->halt(target);
372 }
373
374 while (buf_get_u32(dbg_stat->value, EICE_DBG_CONTROL_DBGACK, 1) == 0)
375 {
376 embeddedice_read_reg(dbg_stat);
377 jtag_execute_queue();
378 }
379
380 target->state = TARGET_HALTED;
381
382 /* SVC, ARM state, IRQ and FIQ disabled */
383 buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
384 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
385 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
386
387 /* start fetching from 0x0 */
388 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
389 armv4_5->core_cache->reg_list[15].dirty = 1;
390 armv4_5->core_cache->reg_list[15].valid = 1;
391
392 armv4_5->core_mode = ARMV4_5_MODE_SVC;
393 armv4_5->core_state = ARMV4_5_STATE_ARM;
394
395 arm720t_disable_mmu_caches(target, 1, 1, 1);
396 arm720t->armv4_5_mmu.mmu_enabled = 0;
397 arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
398 arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
399
400 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
401
402 return ERROR_OK;
403 }
404
405 int arm720t_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
406 {
407 arm7tdmi_init_target(cmd_ctx, target);
408
409 return ERROR_OK;
410
411 }
412
413 int arm720t_quit()
414 {
415
416 return ERROR_OK;
417 }
418
419 int arm720t_init_arch_info(target_t *target, arm720t_common_t *arm720t, int chain_pos, char *variant)
420 {
421 arm7tdmi_common_t *arm7tdmi = &arm720t->arm7tdmi_common;
422 arm7_9_common_t *arm7_9 = &arm7tdmi->arm7_9_common;
423
424 arm7tdmi_init_arch_info(target, arm7tdmi, chain_pos, variant);
425
426 arm7tdmi->arch_info = arm720t;
427 arm720t->common_magic = ARM720T_COMMON_MAGIC;
428
429 arm7_9->post_debug_entry = arm720t_post_debug_entry;
430 arm7_9->pre_restore_context = arm720t_pre_restore_context;
431
432 arm720t->armv4_5_mmu.armv4_5_cache.ctype = -1;
433 arm720t->armv4_5_mmu.get_ttb = arm720t_get_ttb;
434 arm720t->armv4_5_mmu.read_memory = arm7_9_read_memory;
435 arm720t->armv4_5_mmu.write_memory = arm7_9_write_memory;
436 arm720t->armv4_5_mmu.disable_mmu_caches = arm720t_disable_mmu_caches;
437 arm720t->armv4_5_mmu.enable_mmu_caches = arm720t_enable_mmu_caches;
438 arm720t->armv4_5_mmu.has_tiny_pages = 0;
439 arm720t->armv4_5_mmu.mmu_enabled = 0;
440
441 return ERROR_OK;
442 }
443
444 int arm720t_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target)
445 {
446 int chain_pos;
447 char *variant = NULL;
448 arm720t_common_t *arm720t = malloc(sizeof(arm720t_common_t));
449
450 if (argc < 4)
451 {
452 ERROR("'target arm720t' requires at least one additional argument");
453 exit(-1);
454 }
455
456 chain_pos = strtoul(args[3], NULL, 0);
457
458 if (argc >= 5)
459 variant = strdup(args[4]);
460
461 DEBUG("chain_pos: %i, variant: %s", chain_pos, variant);
462
463 arm720t_init_arch_info(target, arm720t, chain_pos, variant);
464
465 return ERROR_OK;
466 }
467
468 int arm720t_register_commands(struct command_context_s *cmd_ctx)
469 {
470 int retval;
471 command_t *arm720t_cmd;
472
473
474 retval = arm7tdmi_register_commands(cmd_ctx);
475
476 arm720t_cmd = register_command(cmd_ctx, NULL, "arm720t", NULL, COMMAND_ANY, NULL);
477
478 register_command(cmd_ctx, arm720t_cmd, "cp15", arm720t_handle_cp15_command, COMMAND_EXEC, "display/modify cp15 register <opcode> [value]");
479 register_command(cmd_ctx, arm720t_cmd, "virt2phys", arm720t_handle_virt2phys_command, COMMAND_EXEC, "translate va to pa <va>");
480
481 register_command(cmd_ctx, arm720t_cmd, "mdw_phys", arm720t_handle_md_phys_command, COMMAND_EXEC, "display memory words <physical addr> [count]");
482 register_command(cmd_ctx, arm720t_cmd, "mdh_phys", arm720t_handle_md_phys_command, COMMAND_EXEC, "display memory half-words <physical addr> [count]");
483 register_command(cmd_ctx, arm720t_cmd, "mdb_phys", arm720t_handle_md_phys_command, COMMAND_EXEC, "display memory bytes <physical addr> [count]");
484
485 register_command(cmd_ctx, arm720t_cmd, "mww_phys", arm720t_handle_mw_phys_command, COMMAND_EXEC, "write memory word <physical addr> <value>");
486 register_command(cmd_ctx, arm720t_cmd, "mwh_phys", arm720t_handle_mw_phys_command, COMMAND_EXEC, "write memory half-word <physical addr> <value>");
487 register_command(cmd_ctx, arm720t_cmd, "mwb_phys", arm720t_handle_mw_phys_command, COMMAND_EXEC, "write memory byte <physical addr> <value>");
488
489 return ERROR_OK;
490 }
491
492 int arm720t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
493 {
494 int retval;
495 target_t *target = get_current_target(cmd_ctx);
496 armv4_5_common_t *armv4_5;
497 arm7_9_common_t *arm7_9;
498 arm7tdmi_common_t *arm7tdmi;
499 arm720t_common_t *arm720t;
500 arm_jtag_t *jtag_info;
501
502 if (arm720t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm7tdmi, &arm720t) != ERROR_OK)
503 {
504 command_print(cmd_ctx, "current target isn't an ARM720t target");
505 return ERROR_OK;
506 }
507
508 jtag_info = &arm7_9->jtag_info;
509
510 if (target->state != TARGET_HALTED)
511 {
512 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
513 return ERROR_OK;
514 }
515
516 /* one or more argument, access a single register (write if second argument is given */
517 if (argc >= 1)
518 {
519 u32 opcode = strtoul(args[0], NULL, 0);
520
521 if (argc == 1)
522 {
523 u32 value;
524 if ((retval = arm720t_read_cp15(target, opcode, &value)) != ERROR_OK)
525 {
526 command_print(cmd_ctx, "couldn't access cp15 with opcode 0x%8.8x", opcode);
527 return ERROR_OK;
528 }
529 jtag_execute_queue();
530
531 command_print(cmd_ctx, "0x%8.8x: 0x%8.8x", opcode, value);
532 }
533 else if (argc == 2)
534 {
535 u32 value = strtoul(args[1], NULL, 0);
536 if ((retval = arm720t_write_cp15(target, opcode, value)) != ERROR_OK)
537 {
538 command_print(cmd_ctx, "couldn't access cp15 with opcode 0x%8.8x", opcode);
539 return ERROR_OK;
540 }
541 command_print(cmd_ctx, "0x%8.8x: 0x%8.8x", opcode, value);
542 }
543 }
544
545 return ERROR_OK;
546 }
547
548 int arm720t_handle_virt2phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
549 {
550 target_t *target = get_current_target(cmd_ctx);
551 armv4_5_common_t *armv4_5;
552 arm7_9_common_t *arm7_9;
553 arm7tdmi_common_t *arm7tdmi;
554 arm720t_common_t *arm720t;
555 arm_jtag_t *jtag_info;
556
557 if (arm720t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm7tdmi, &arm720t) != ERROR_OK)
558 {
559 command_print(cmd_ctx, "current target isn't an ARM720t target");
560 return ERROR_OK;
561 }
562
563 jtag_info = &arm7_9->jtag_info;
564
565 if (target->state != TARGET_HALTED)
566 {
567 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
568 return ERROR_OK;
569 }
570
571 return armv4_5_mmu_handle_virt2phys_command(cmd_ctx, cmd, args, argc, target, &arm720t->armv4_5_mmu);
572 }
573
574 int arm720t_handle_md_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
575 {
576 target_t *target = get_current_target(cmd_ctx);
577 armv4_5_common_t *armv4_5;
578 arm7_9_common_t *arm7_9;
579 arm7tdmi_common_t *arm7tdmi;
580 arm720t_common_t *arm720t;
581 arm_jtag_t *jtag_info;
582
583 if (arm720t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm7tdmi, &arm720t) != ERROR_OK)
584 {
585 command_print(cmd_ctx, "current target isn't an ARM720t target");
586 return ERROR_OK;
587 }
588
589 jtag_info = &arm7_9->jtag_info;
590
591 if (target->state != TARGET_HALTED)
592 {
593 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
594 return ERROR_OK;
595 }
596
597 return armv4_5_mmu_handle_md_phys_command(cmd_ctx, cmd, args, argc, target, &arm720t->armv4_5_mmu);
598 }
599
600 int arm720t_handle_mw_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
601 {
602 target_t *target = get_current_target(cmd_ctx);
603 armv4_5_common_t *armv4_5;
604 arm7_9_common_t *arm7_9;
605 arm7tdmi_common_t *arm7tdmi;
606 arm720t_common_t *arm720t;
607 arm_jtag_t *jtag_info;
608
609 if (arm720t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm7tdmi, &arm720t) != ERROR_OK)
610 {
611 command_print(cmd_ctx, "current target isn't an ARM720t target");
612 return ERROR_OK;
613 }
614
615 jtag_info = &arm7_9->jtag_info;
616
617 if (target->state != TARGET_HALTED)
618 {
619 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
620 return ERROR_OK;
621 }
622
623 return armv4_5_mmu_handle_mw_phys_command(cmd_ctx, cmd, args, argc, target, &arm720t->armv4_5_mmu);
624 }
625