- Fixes '[<>]' whitespace
[openocd.git] / src / target / arm720t.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
20 #ifdef HAVE_CONFIG_H
21 #include "config.h"
22 #endif
23
24 #include "arm720t.h"
25 #include "time_support.h"
26 #include "target_type.h"
27
28
29 #if 0
30 #define _DEBUG_INSTRUCTION_EXECUTION_
31 #endif
32
33 /* cli handling */
34 int arm720t_register_commands(struct command_context_s *cmd_ctx);
35
36 int arm720t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
37 int arm720t_handle_virt2phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
38 int arm720t_handle_md_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
39 int arm720t_handle_mw_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
40
41 /* forward declarations */
42 int arm720t_target_create(struct target_s *target,Jim_Interp *interp);
43 int arm720t_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
44 int arm720t_quit(void);
45 int arm720t_arch_state(struct target_s *target);
46 int arm720t_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
47 int arm720t_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
48 int arm720t_soft_reset_halt(struct target_s *target);
49
50 target_type_t arm720t_target =
51 {
52 .name = "arm720t",
53
54 .poll = arm7_9_poll,
55 .arch_state = arm720t_arch_state,
56
57 .halt = arm7_9_halt,
58 .resume = arm7_9_resume,
59 .step = arm7_9_step,
60
61 .assert_reset = arm7_9_assert_reset,
62 .deassert_reset = arm7_9_deassert_reset,
63 .soft_reset_halt = arm720t_soft_reset_halt,
64
65 .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
66
67 .read_memory = arm720t_read_memory,
68 .write_memory = arm720t_write_memory,
69 .bulk_write_memory = arm7_9_bulk_write_memory,
70 .checksum_memory = arm7_9_checksum_memory,
71 .blank_check_memory = arm7_9_blank_check_memory,
72
73 .run_algorithm = armv4_5_run_algorithm,
74
75 .add_breakpoint = arm7_9_add_breakpoint,
76 .remove_breakpoint = arm7_9_remove_breakpoint,
77 .add_watchpoint = arm7_9_add_watchpoint,
78 .remove_watchpoint = arm7_9_remove_watchpoint,
79
80 .register_commands = arm720t_register_commands,
81 .target_create = arm720t_target_create,
82 .init_target = arm720t_init_target,
83 .examine = arm7tdmi_examine,
84 .quit = arm720t_quit
85 };
86
87 int arm720t_scan_cp15(target_t *target, uint32_t out, uint32_t *in, int instruction, int clock)
88 {
89 int retval = ERROR_OK;
90 armv4_5_common_t *armv4_5 = target->arch_info;
91 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
92 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
93 scan_field_t fields[2];
94 uint8_t out_buf[4];
95 uint8_t instruction_buf = instruction;
96
97 buf_set_u32(out_buf, 0, 32, flip_u32(out, 32));
98
99 jtag_set_end_state(TAP_DRPAUSE);
100 if ((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
101 {
102 return retval;
103 }
104 if ((retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL)) != ERROR_OK)
105 {
106 return retval;
107 }
108
109 fields[0].tap = jtag_info->tap;
110 fields[0].num_bits = 1;
111 fields[0].out_value = &instruction_buf;
112 fields[0].in_value = NULL;
113
114 fields[1].tap = jtag_info->tap;
115 fields[1].num_bits = 32;
116 fields[1].out_value = out_buf;
117 fields[1].in_value = NULL;
118
119 if (in)
120 {
121 fields[1].in_value = (uint8_t *)in;
122 jtag_add_dr_scan(2, fields, jtag_get_end_state());
123 jtag_add_callback(arm7flip32, (jtag_callback_data_t)in);
124 } else
125 {
126 jtag_add_dr_scan(2, fields, jtag_get_end_state());
127 }
128
129 if (clock)
130 jtag_add_runtest(0, jtag_get_end_state());
131
132 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
133 if ((retval = jtag_execute_queue()) != ERROR_OK)
134 {
135 return retval;
136 }
137
138 if (in)
139 LOG_DEBUG("out: %8.8x, in: %8.8x, instruction: %i, clock: %i", out, *in, instruction, clock);
140 else
141 LOG_DEBUG("out: %8.8x, instruction: %i, clock: %i", out, instruction, clock);
142 #else
143 LOG_DEBUG("out: %8.8" PRIx32 ", instruction: %i, clock: %i", out, instruction, clock);
144 #endif
145
146 return ERROR_OK;
147 }
148
149 int arm720t_read_cp15(target_t *target, uint32_t opcode, uint32_t *value)
150 {
151 /* fetch CP15 opcode */
152 arm720t_scan_cp15(target, opcode, NULL, 1, 1);
153 /* "DECODE" stage */
154 arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 1);
155 /* "EXECUTE" stage (1) */
156 arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 0);
157 arm720t_scan_cp15(target, 0x0, NULL, 0, 1);
158 /* "EXECUTE" stage (2) */
159 arm720t_scan_cp15(target, 0x0, NULL, 0, 1);
160 /* "EXECUTE" stage (3), CDATA is read */
161 arm720t_scan_cp15(target, ARMV4_5_NOP, value, 1, 1);
162
163 return ERROR_OK;
164 }
165
166 int arm720t_write_cp15(target_t *target, uint32_t opcode, uint32_t value)
167 {
168 /* fetch CP15 opcode */
169 arm720t_scan_cp15(target, opcode, NULL, 1, 1);
170 /* "DECODE" stage */
171 arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 1);
172 /* "EXECUTE" stage (1) */
173 arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 0);
174 arm720t_scan_cp15(target, 0x0, NULL, 0, 1);
175 /* "EXECUTE" stage (2) */
176 arm720t_scan_cp15(target, value, NULL, 0, 1);
177 arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 1);
178
179 return ERROR_OK;
180 }
181
182 uint32_t arm720t_get_ttb(target_t *target)
183 {
184 uint32_t ttb = 0x0;
185
186 arm720t_read_cp15(target, 0xee120f10, &ttb);
187 jtag_execute_queue();
188
189 ttb &= 0xffffc000;
190
191 return ttb;
192 }
193
194 void arm720t_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
195 {
196 uint32_t cp15_control;
197
198 /* read cp15 control register */
199 arm720t_read_cp15(target, 0xee110f10, &cp15_control);
200 jtag_execute_queue();
201
202 if (mmu)
203 cp15_control &= ~0x1U;
204
205 if (d_u_cache || i_cache)
206 cp15_control &= ~0x4U;
207
208 arm720t_write_cp15(target, 0xee010f10, cp15_control);
209 }
210
211 void arm720t_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
212 {
213 uint32_t cp15_control;
214
215 /* read cp15 control register */
216 arm720t_read_cp15(target, 0xee110f10, &cp15_control);
217 jtag_execute_queue();
218
219 if (mmu)
220 cp15_control |= 0x1U;
221
222 if (d_u_cache || i_cache)
223 cp15_control |= 0x4U;
224
225 arm720t_write_cp15(target, 0xee010f10, cp15_control);
226 }
227
228 void arm720t_post_debug_entry(target_t *target)
229 {
230 armv4_5_common_t *armv4_5 = target->arch_info;
231 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
232 arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;
233 arm720t_common_t *arm720t = arm7tdmi->arch_info;
234
235 /* examine cp15 control reg */
236 arm720t_read_cp15(target, 0xee110f10, &arm720t->cp15_control_reg);
237 jtag_execute_queue();
238 LOG_DEBUG("cp15_control_reg: %8.8" PRIx32 "", arm720t->cp15_control_reg);
239
240 arm720t->armv4_5_mmu.mmu_enabled = (arm720t->cp15_control_reg & 0x1U) ? 1 : 0;
241 arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm720t->cp15_control_reg & 0x4U) ? 1 : 0;
242 arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
243
244 /* save i/d fault status and address register */
245 arm720t_read_cp15(target, 0xee150f10, &arm720t->fsr_reg);
246 arm720t_read_cp15(target, 0xee160f10, &arm720t->far_reg);
247 jtag_execute_queue();
248 }
249
250 void arm720t_pre_restore_context(target_t *target)
251 {
252 armv4_5_common_t *armv4_5 = target->arch_info;
253 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
254 arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;
255 arm720t_common_t *arm720t = arm7tdmi->arch_info;
256
257 /* restore i/d fault status and address register */
258 arm720t_write_cp15(target, 0xee050f10, arm720t->fsr_reg);
259 arm720t_write_cp15(target, 0xee060f10, arm720t->far_reg);
260 }
261
262 int arm720t_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p, arm7tdmi_common_t **arm7tdmi_p, arm720t_common_t **arm720t_p)
263 {
264 armv4_5_common_t *armv4_5 = target->arch_info;
265 arm7_9_common_t *arm7_9;
266 arm7tdmi_common_t *arm7tdmi;
267 arm720t_common_t *arm720t;
268
269 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
270 {
271 return -1;
272 }
273
274 arm7_9 = armv4_5->arch_info;
275 if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
276 {
277 return -1;
278 }
279
280 arm7tdmi = arm7_9->arch_info;
281 if (arm7tdmi->common_magic != ARM7TDMI_COMMON_MAGIC)
282 {
283 return -1;
284 }
285
286 arm720t = arm7tdmi->arch_info;
287 if (arm720t->common_magic != ARM720T_COMMON_MAGIC)
288 {
289 return -1;
290 }
291
292 *armv4_5_p = armv4_5;
293 *arm7_9_p = arm7_9;
294 *arm7tdmi_p = arm7tdmi;
295 *arm720t_p = arm720t;
296
297 return ERROR_OK;
298 }
299
300 int arm720t_arch_state(struct target_s *target)
301 {
302 armv4_5_common_t *armv4_5 = target->arch_info;
303 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
304 arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;
305 arm720t_common_t *arm720t = arm7tdmi->arch_info;
306
307 char *state[] =
308 {
309 "disabled", "enabled"
310 };
311
312 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
313 {
314 LOG_ERROR("BUG: called for a non-ARMv4/5 target");
315 exit(-1);
316 }
317
318 LOG_USER("target halted in %s state due to %s, current mode: %s\n"
319 "cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n"
320 "MMU: %s, Cache: %s",
321 armv4_5_state_strings[armv4_5->core_state],
322 Jim_Nvp_value2name_simple( nvp_target_debug_reason, target->debug_reason )->name ,
323 armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)],
324 buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
325 buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
326 state[arm720t->armv4_5_mmu.mmu_enabled],
327 state[arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled]);
328
329 return ERROR_OK;
330 }
331
332 int arm720t_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
333 {
334 int retval;
335 armv4_5_common_t *armv4_5 = target->arch_info;
336 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
337 arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;
338 arm720t_common_t *arm720t = arm7tdmi->arch_info;
339
340 /* disable cache, but leave MMU enabled */
341 if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
342 arm720t_disable_mmu_caches(target, 0, 1, 0);
343
344 retval = arm7_9_read_memory(target, address, size, count, buffer);
345
346 if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
347 arm720t_enable_mmu_caches(target, 0, 1, 0);
348
349 return retval;
350 }
351
352 int arm720t_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
353 {
354 int retval;
355
356 if ((retval = arm7_9_write_memory(target, address, size, count, buffer)) != ERROR_OK)
357 return retval;
358
359 return retval;
360 }
361
362 int arm720t_soft_reset_halt(struct target_s *target)
363 {
364 int retval = ERROR_OK;
365 armv4_5_common_t *armv4_5 = target->arch_info;
366 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
367 arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;
368 arm720t_common_t *arm720t = arm7tdmi->arch_info;
369 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
370
371 if ((retval = target_halt(target)) != ERROR_OK)
372 {
373 return retval;
374 }
375
376 long long then = timeval_ms();
377 int timeout;
378 while (!(timeout = ((timeval_ms()-then) > 1000)))
379 {
380 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
381 {
382 embeddedice_read_reg(dbg_stat);
383 if ((retval = jtag_execute_queue()) != ERROR_OK)
384 {
385 return retval;
386 }
387 } else
388 {
389 break;
390 }
391 if (debug_level >= 3)
392 {
393 alive_sleep(100);
394 } else
395 {
396 keep_alive();
397 }
398 }
399 if (timeout)
400 {
401 LOG_ERROR("Failed to halt CPU after 1 sec");
402 return ERROR_TARGET_TIMEOUT;
403 }
404
405 target->state = TARGET_HALTED;
406
407 /* SVC, ARM state, IRQ and FIQ disabled */
408 buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
409 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
410 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
411
412 /* start fetching from 0x0 */
413 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
414 armv4_5->core_cache->reg_list[15].dirty = 1;
415 armv4_5->core_cache->reg_list[15].valid = 1;
416
417 armv4_5->core_mode = ARMV4_5_MODE_SVC;
418 armv4_5->core_state = ARMV4_5_STATE_ARM;
419
420 arm720t_disable_mmu_caches(target, 1, 1, 1);
421 arm720t->armv4_5_mmu.mmu_enabled = 0;
422 arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
423 arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
424
425 if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
426 {
427 return retval;
428 }
429
430 return ERROR_OK;
431 }
432
433 int arm720t_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
434 {
435 arm7tdmi_init_target(cmd_ctx, target);
436
437 return ERROR_OK;
438 }
439
440 int arm720t_quit(void)
441 {
442 return ERROR_OK;
443 }
444
445 int arm720t_init_arch_info(target_t *target, arm720t_common_t *arm720t, jtag_tap_t *tap)
446 {
447 arm7tdmi_common_t *arm7tdmi = &arm720t->arm7tdmi_common;
448 arm7_9_common_t *arm7_9 = &arm7tdmi->arm7_9_common;
449
450 arm7tdmi_init_arch_info(target, arm7tdmi, tap);
451
452 arm7tdmi->arch_info = arm720t;
453 arm720t->common_magic = ARM720T_COMMON_MAGIC;
454
455 arm7_9->post_debug_entry = arm720t_post_debug_entry;
456 arm7_9->pre_restore_context = arm720t_pre_restore_context;
457
458 arm720t->armv4_5_mmu.armv4_5_cache.ctype = -1;
459 arm720t->armv4_5_mmu.get_ttb = arm720t_get_ttb;
460 arm720t->armv4_5_mmu.read_memory = arm7_9_read_memory;
461 arm720t->armv4_5_mmu.write_memory = arm7_9_write_memory;
462 arm720t->armv4_5_mmu.disable_mmu_caches = arm720t_disable_mmu_caches;
463 arm720t->armv4_5_mmu.enable_mmu_caches = arm720t_enable_mmu_caches;
464 arm720t->armv4_5_mmu.has_tiny_pages = 0;
465 arm720t->armv4_5_mmu.mmu_enabled = 0;
466
467 return ERROR_OK;
468 }
469
470 int arm720t_target_create(struct target_s *target, Jim_Interp *interp)
471 {
472 arm720t_common_t *arm720t = calloc(1,sizeof(arm720t_common_t));
473
474 arm720t_init_arch_info(target, arm720t, target->tap);
475
476 return ERROR_OK;
477 }
478
479 int arm720t_register_commands(struct command_context_s *cmd_ctx)
480 {
481 int retval;
482 command_t *arm720t_cmd;
483
484
485 retval = arm7tdmi_register_commands(cmd_ctx);
486
487 arm720t_cmd = register_command(cmd_ctx, NULL, "arm720t", NULL, COMMAND_ANY, "arm720t specific commands");
488
489 register_command(cmd_ctx, arm720t_cmd, "cp15", arm720t_handle_cp15_command, COMMAND_EXEC, "display/modify cp15 register <opcode> [value]");
490 register_command(cmd_ctx, arm720t_cmd, "virt2phys", arm720t_handle_virt2phys_command, COMMAND_EXEC, "translate va to pa <va>");
491
492 register_command(cmd_ctx, arm720t_cmd, "mdw_phys", arm720t_handle_md_phys_command, COMMAND_EXEC, "display memory words <physical addr> [count]");
493 register_command(cmd_ctx, arm720t_cmd, "mdh_phys", arm720t_handle_md_phys_command, COMMAND_EXEC, "display memory half-words <physical addr> [count]");
494 register_command(cmd_ctx, arm720t_cmd, "mdb_phys", arm720t_handle_md_phys_command, COMMAND_EXEC, "display memory bytes <physical addr> [count]");
495
496 register_command(cmd_ctx, arm720t_cmd, "mww_phys", arm720t_handle_mw_phys_command, COMMAND_EXEC, "write memory word <physical addr> <value>");
497 register_command(cmd_ctx, arm720t_cmd, "mwh_phys", arm720t_handle_mw_phys_command, COMMAND_EXEC, "write memory half-word <physical addr> <value>");
498 register_command(cmd_ctx, arm720t_cmd, "mwb_phys", arm720t_handle_mw_phys_command, COMMAND_EXEC, "write memory byte <physical addr> <value>");
499
500 return ERROR_OK;
501 }
502
503 int arm720t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
504 {
505 int retval;
506 target_t *target = get_current_target(cmd_ctx);
507 armv4_5_common_t *armv4_5;
508 arm7_9_common_t *arm7_9;
509 arm7tdmi_common_t *arm7tdmi;
510 arm720t_common_t *arm720t;
511 arm_jtag_t *jtag_info;
512
513 if (arm720t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm7tdmi, &arm720t) != ERROR_OK)
514 {
515 command_print(cmd_ctx, "current target isn't an ARM720t target");
516 return ERROR_OK;
517 }
518
519 jtag_info = &arm7_9->jtag_info;
520
521 if (target->state != TARGET_HALTED)
522 {
523 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
524 return ERROR_OK;
525 }
526
527 /* one or more argument, access a single register (write if second argument is given */
528 if (argc >= 1)
529 {
530 uint32_t opcode = strtoul(args[0], NULL, 0);
531
532 if (argc == 1)
533 {
534 uint32_t value;
535 if ((retval = arm720t_read_cp15(target, opcode, &value)) != ERROR_OK)
536 {
537 command_print(cmd_ctx, "couldn't access cp15 with opcode 0x%8.8" PRIx32 "", opcode);
538 return ERROR_OK;
539 }
540
541 if ((retval = jtag_execute_queue()) != ERROR_OK)
542 {
543 return retval;
544 }
545
546 command_print(cmd_ctx, "0x%8.8" PRIx32 ": 0x%8.8" PRIx32 "", opcode, value);
547 }
548 else if (argc == 2)
549 {
550 uint32_t value = strtoul(args[1], NULL, 0);
551 if ((retval = arm720t_write_cp15(target, opcode, value)) != ERROR_OK)
552 {
553 command_print(cmd_ctx, "couldn't access cp15 with opcode 0x%8.8" PRIx32 "", opcode);
554 return ERROR_OK;
555 }
556 command_print(cmd_ctx, "0x%8.8" PRIx32 ": 0x%8.8" PRIx32 "", opcode, value);
557 }
558 }
559
560 return ERROR_OK;
561 }
562
563 int arm720t_handle_virt2phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
564 {
565 target_t *target = get_current_target(cmd_ctx);
566 armv4_5_common_t *armv4_5;
567 arm7_9_common_t *arm7_9;
568 arm7tdmi_common_t *arm7tdmi;
569 arm720t_common_t *arm720t;
570 arm_jtag_t *jtag_info;
571
572 if (arm720t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm7tdmi, &arm720t) != ERROR_OK)
573 {
574 command_print(cmd_ctx, "current target isn't an ARM720t target");
575 return ERROR_OK;
576 }
577
578 jtag_info = &arm7_9->jtag_info;
579
580 if (target->state != TARGET_HALTED)
581 {
582 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
583 return ERROR_OK;
584 }
585
586 return armv4_5_mmu_handle_virt2phys_command(cmd_ctx, cmd, args, argc, target, &arm720t->armv4_5_mmu);
587 }
588
589 int arm720t_handle_md_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
590 {
591 target_t *target = get_current_target(cmd_ctx);
592 armv4_5_common_t *armv4_5;
593 arm7_9_common_t *arm7_9;
594 arm7tdmi_common_t *arm7tdmi;
595 arm720t_common_t *arm720t;
596 arm_jtag_t *jtag_info;
597
598 if (arm720t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm7tdmi, &arm720t) != ERROR_OK)
599 {
600 command_print(cmd_ctx, "current target isn't an ARM720t target");
601 return ERROR_OK;
602 }
603
604 jtag_info = &arm7_9->jtag_info;
605
606 if (target->state != TARGET_HALTED)
607 {
608 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
609 return ERROR_OK;
610 }
611
612 return armv4_5_mmu_handle_md_phys_command(cmd_ctx, cmd, args, argc, target, &arm720t->armv4_5_mmu);
613 }
614
615 int arm720t_handle_mw_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
616 {
617 target_t *target = get_current_target(cmd_ctx);
618 armv4_5_common_t *armv4_5;
619 arm7_9_common_t *arm7_9;
620 arm7tdmi_common_t *arm7tdmi;
621 arm720t_common_t *arm720t;
622 arm_jtag_t *jtag_info;
623
624 if (arm720t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm7tdmi, &arm720t) != ERROR_OK)
625 {
626 command_print(cmd_ctx, "current target isn't an ARM720t target");
627 return ERROR_OK;
628 }
629
630 jtag_info = &arm7_9->jtag_info;
631
632 if (target->state != TARGET_HALTED)
633 {
634 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
635 return ERROR_OK;
636 }
637
638 return armv4_5_mmu_handle_mw_phys_command(cmd_ctx, cmd, args, argc, target, &arm720t->armv4_5_mmu);
639 }