jtag newtap change & huge manual update
[openocd.git] / src / target / arm720t.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
20 #ifdef HAVE_CONFIG_H
21 #include "config.h"
22 #endif
23
24 #include "arm720t.h"
25 #include "jtag.h"
26 #include "log.h"
27 #include "time_support.h"
28
29 #include <stdlib.h>
30 #include <string.h>
31
32 #if 0
33 #define _DEBUG_INSTRUCTION_EXECUTION_
34 #endif
35
36 /* cli handling */
37 int arm720t_register_commands(struct command_context_s *cmd_ctx);
38
39 int arm720t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
40 int arm720t_handle_virt2phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
41 int arm720t_handle_md_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
42 int arm720t_handle_mw_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
43
44 /* forward declarations */
45 int arm720t_target_create(struct target_s *target,Jim_Interp *interp);
46 int arm720t_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
47 int arm720t_quit(void);
48 int arm720t_arch_state(struct target_s *target);
49 int arm720t_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
50 int arm720t_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
51 int arm720t_soft_reset_halt(struct target_s *target);
52
53 target_type_t arm720t_target =
54 {
55 .name = "arm720t",
56
57 .poll = arm7_9_poll,
58 .arch_state = arm720t_arch_state,
59
60 .halt = arm7_9_halt,
61 .resume = arm7_9_resume,
62 .step = arm7_9_step,
63
64 .assert_reset = arm7_9_assert_reset,
65 .deassert_reset = arm7_9_deassert_reset,
66 .soft_reset_halt = arm720t_soft_reset_halt,
67
68 .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
69
70 .read_memory = arm720t_read_memory,
71 .write_memory = arm720t_write_memory,
72 .bulk_write_memory = arm7_9_bulk_write_memory,
73 .checksum_memory = arm7_9_checksum_memory,
74 .blank_check_memory = arm7_9_blank_check_memory,
75
76 .run_algorithm = armv4_5_run_algorithm,
77
78 .add_breakpoint = arm7_9_add_breakpoint,
79 .remove_breakpoint = arm7_9_remove_breakpoint,
80 .add_watchpoint = arm7_9_add_watchpoint,
81 .remove_watchpoint = arm7_9_remove_watchpoint,
82
83 .register_commands = arm720t_register_commands,
84 .target_create = arm720t_target_create,
85 .init_target = arm720t_init_target,
86 .examine = arm7tdmi_examine,
87 .quit = arm720t_quit
88 };
89
90 int arm720t_scan_cp15(target_t *target, u32 out, u32 *in, int instruction, int clock)
91 {
92 int retval = ERROR_OK;
93 armv4_5_common_t *armv4_5 = target->arch_info;
94 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
95 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
96 scan_field_t fields[2];
97 u8 out_buf[4];
98 u8 instruction_buf = instruction;
99
100 buf_set_u32(out_buf, 0, 32, flip_u32(out, 32));
101
102 jtag_add_end_state(TAP_PD);
103 if((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
104 {
105 return retval;
106 }
107 if((retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL)) != ERROR_OK)
108 {
109 return retval;
110 }
111
112 fields[0].tap = jtag_info->tap;
113 fields[0].num_bits = 1;
114 fields[0].out_value = &instruction_buf;
115 fields[0].out_mask = NULL;
116 fields[0].in_value = NULL;
117 fields[0].in_check_value = NULL;
118 fields[0].in_check_mask = NULL;
119 fields[0].in_handler = NULL;
120 fields[0].in_handler_priv = NULL;
121
122 fields[1].tap = jtag_info->tap;
123 fields[1].num_bits = 32;
124 fields[1].out_value = out_buf;
125 fields[1].out_mask = NULL;
126 fields[1].in_value = NULL;
127 if (in)
128 {
129 fields[1].in_handler = arm_jtag_buf_to_u32_flip;
130 fields[1].in_handler_priv = in;
131 } else
132 {
133 fields[1].in_handler = NULL;
134 fields[1].in_handler_priv = NULL;
135 }
136 fields[1].in_check_value = NULL;
137 fields[1].in_check_mask = NULL;
138
139 jtag_add_dr_scan(2, fields, -1);
140
141 if (clock)
142 jtag_add_runtest(0, -1);
143
144 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
145 if((retval = jtag_execute_queue()) != ERROR_OK)
146 {
147 return retval;
148 }
149
150 if (in)
151 LOG_DEBUG("out: %8.8x, in: %8.8x, instruction: %i, clock: %i", out, *in, instruction, clock);
152 else
153 LOG_DEBUG("out: %8.8x, instruction: %i, clock: %i", out, instruction, clock);
154 #else
155 LOG_DEBUG("out: %8.8x, instruction: %i, clock: %i", out, instruction, clock);
156 #endif
157
158 return ERROR_OK;
159 }
160
161 int arm720t_read_cp15(target_t *target, u32 opcode, u32 *value)
162 {
163 /* fetch CP15 opcode */
164 arm720t_scan_cp15(target, opcode, NULL, 1, 1);
165 /* "DECODE" stage */
166 arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 1);
167 /* "EXECUTE" stage (1) */
168 arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 0);
169 arm720t_scan_cp15(target, 0x0, NULL, 0, 1);
170 /* "EXECUTE" stage (2) */
171 arm720t_scan_cp15(target, 0x0, NULL, 0, 1);
172 /* "EXECUTE" stage (3), CDATA is read */
173 arm720t_scan_cp15(target, ARMV4_5_NOP, value, 1, 1);
174
175 return ERROR_OK;
176 }
177
178 int arm720t_write_cp15(target_t *target, u32 opcode, u32 value)
179 {
180 /* fetch CP15 opcode */
181 arm720t_scan_cp15(target, opcode, NULL, 1, 1);
182 /* "DECODE" stage */
183 arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 1);
184 /* "EXECUTE" stage (1) */
185 arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 0);
186 arm720t_scan_cp15(target, 0x0, NULL, 0, 1);
187 /* "EXECUTE" stage (2) */
188 arm720t_scan_cp15(target, value, NULL, 0, 1);
189 arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 1);
190
191 return ERROR_OK;
192 }
193
194 u32 arm720t_get_ttb(target_t *target)
195 {
196 u32 ttb = 0x0;
197
198 arm720t_read_cp15(target, 0xee120f10, &ttb);
199 jtag_execute_queue();
200
201 ttb &= 0xffffc000;
202
203 return ttb;
204 }
205
206 void arm720t_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
207 {
208 u32 cp15_control;
209
210 /* read cp15 control register */
211 arm720t_read_cp15(target, 0xee110f10, &cp15_control);
212 jtag_execute_queue();
213
214 if (mmu)
215 cp15_control &= ~0x1U;
216
217 if (d_u_cache || i_cache)
218 cp15_control &= ~0x4U;
219
220 arm720t_write_cp15(target, 0xee010f10, cp15_control);
221 }
222
223 void arm720t_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
224 {
225 u32 cp15_control;
226
227 /* read cp15 control register */
228 arm720t_read_cp15(target, 0xee110f10, &cp15_control);
229 jtag_execute_queue();
230
231 if (mmu)
232 cp15_control |= 0x1U;
233
234 if (d_u_cache || i_cache)
235 cp15_control |= 0x4U;
236
237 arm720t_write_cp15(target, 0xee010f10, cp15_control);
238 }
239
240 void arm720t_post_debug_entry(target_t *target)
241 {
242 armv4_5_common_t *armv4_5 = target->arch_info;
243 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
244 arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;
245 arm720t_common_t *arm720t = arm7tdmi->arch_info;
246
247 /* examine cp15 control reg */
248 arm720t_read_cp15(target, 0xee110f10, &arm720t->cp15_control_reg);
249 jtag_execute_queue();
250 LOG_DEBUG("cp15_control_reg: %8.8x", arm720t->cp15_control_reg);
251
252 arm720t->armv4_5_mmu.mmu_enabled = (arm720t->cp15_control_reg & 0x1U) ? 1 : 0;
253 arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm720t->cp15_control_reg & 0x4U) ? 1 : 0;
254 arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
255
256 /* save i/d fault status and address register */
257 arm720t_read_cp15(target, 0xee150f10, &arm720t->fsr_reg);
258 arm720t_read_cp15(target, 0xee160f10, &arm720t->far_reg);
259 jtag_execute_queue();
260 }
261
262 void arm720t_pre_restore_context(target_t *target)
263 {
264 armv4_5_common_t *armv4_5 = target->arch_info;
265 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
266 arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;
267 arm720t_common_t *arm720t = arm7tdmi->arch_info;
268
269 /* restore i/d fault status and address register */
270 arm720t_write_cp15(target, 0xee050f10, arm720t->fsr_reg);
271 arm720t_write_cp15(target, 0xee060f10, arm720t->far_reg);
272 }
273
274 int arm720t_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p, arm7tdmi_common_t **arm7tdmi_p, arm720t_common_t **arm720t_p)
275 {
276 armv4_5_common_t *armv4_5 = target->arch_info;
277 arm7_9_common_t *arm7_9;
278 arm7tdmi_common_t *arm7tdmi;
279 arm720t_common_t *arm720t;
280
281 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
282 {
283 return -1;
284 }
285
286 arm7_9 = armv4_5->arch_info;
287 if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
288 {
289 return -1;
290 }
291
292 arm7tdmi = arm7_9->arch_info;
293 if (arm7tdmi->common_magic != ARM7TDMI_COMMON_MAGIC)
294 {
295 return -1;
296 }
297
298 arm720t = arm7tdmi->arch_info;
299 if (arm720t->common_magic != ARM720T_COMMON_MAGIC)
300 {
301 return -1;
302 }
303
304 *armv4_5_p = armv4_5;
305 *arm7_9_p = arm7_9;
306 *arm7tdmi_p = arm7tdmi;
307 *arm720t_p = arm720t;
308
309 return ERROR_OK;
310 }
311
312 int arm720t_arch_state(struct target_s *target)
313 {
314 armv4_5_common_t *armv4_5 = target->arch_info;
315 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
316 arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;
317 arm720t_common_t *arm720t = arm7tdmi->arch_info;
318
319 char *state[] =
320 {
321 "disabled", "enabled"
322 };
323
324 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
325 {
326 LOG_ERROR("BUG: called for a non-ARMv4/5 target");
327 exit(-1);
328 }
329
330 LOG_USER("target halted in %s state due to %s, current mode: %s\n"
331 "cpsr: 0x%8.8x pc: 0x%8.8x\n"
332 "MMU: %s, Cache: %s",
333 armv4_5_state_strings[armv4_5->core_state],
334 Jim_Nvp_value2name_simple( nvp_target_debug_reason, target->debug_reason )->name ,
335 armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)],
336 buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
337 buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
338 state[arm720t->armv4_5_mmu.mmu_enabled],
339 state[arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled]);
340
341 return ERROR_OK;
342 }
343
344 int arm720t_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
345 {
346 int retval;
347 armv4_5_common_t *armv4_5 = target->arch_info;
348 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
349 arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;
350 arm720t_common_t *arm720t = arm7tdmi->arch_info;
351
352 /* disable cache, but leave MMU enabled */
353 if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
354 arm720t_disable_mmu_caches(target, 0, 1, 0);
355
356 retval = arm7_9_read_memory(target, address, size, count, buffer);
357
358 if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
359 arm720t_enable_mmu_caches(target, 0, 1, 0);
360
361 return retval;
362 }
363
364 int arm720t_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
365 {
366 int retval;
367
368 if ((retval = arm7_9_write_memory(target, address, size, count, buffer)) != ERROR_OK)
369 return retval;
370
371 return retval;
372 }
373
374 int arm720t_soft_reset_halt(struct target_s *target)
375 {
376 int retval = ERROR_OK;
377 armv4_5_common_t *armv4_5 = target->arch_info;
378 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
379 arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;
380 arm720t_common_t *arm720t = arm7tdmi->arch_info;
381 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
382
383 if ((retval = target_halt(target)) != ERROR_OK)
384 {
385 return retval;
386 }
387
388 long long then=timeval_ms();
389 int timeout;
390 while (!(timeout=((timeval_ms()-then)>1000)))
391 {
392 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
393 {
394 embeddedice_read_reg(dbg_stat);
395 if ((retval = jtag_execute_queue()) != ERROR_OK)
396 {
397 return retval;
398 }
399 } else
400 {
401 break;
402 }
403 if (debug_level>=3)
404 {
405 alive_sleep(100);
406 } else
407 {
408 keep_alive();
409 }
410 }
411 if (timeout)
412 {
413 LOG_ERROR("Failed to halt CPU after 1 sec");
414 return ERROR_TARGET_TIMEOUT;
415 }
416
417 target->state = TARGET_HALTED;
418
419 /* SVC, ARM state, IRQ and FIQ disabled */
420 buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
421 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
422 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
423
424 /* start fetching from 0x0 */
425 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
426 armv4_5->core_cache->reg_list[15].dirty = 1;
427 armv4_5->core_cache->reg_list[15].valid = 1;
428
429 armv4_5->core_mode = ARMV4_5_MODE_SVC;
430 armv4_5->core_state = ARMV4_5_STATE_ARM;
431
432 arm720t_disable_mmu_caches(target, 1, 1, 1);
433 arm720t->armv4_5_mmu.mmu_enabled = 0;
434 arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
435 arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
436
437 if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
438 {
439 return retval;
440 }
441
442 return ERROR_OK;
443 }
444
445 int arm720t_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
446 {
447 arm7tdmi_init_target(cmd_ctx, target);
448
449 return ERROR_OK;
450
451 }
452
453 int arm720t_quit(void)
454 {
455
456 return ERROR_OK;
457 }
458
459 int arm720t_init_arch_info(target_t *target, arm720t_common_t *arm720t, jtag_tap_t *tap, const char *variant)
460 {
461 arm7tdmi_common_t *arm7tdmi = &arm720t->arm7tdmi_common;
462 arm7_9_common_t *arm7_9 = &arm7tdmi->arm7_9_common;
463
464 arm7tdmi_init_arch_info(target, arm7tdmi, tap, variant);
465
466 arm7tdmi->arch_info = arm720t;
467 arm720t->common_magic = ARM720T_COMMON_MAGIC;
468
469 arm7_9->post_debug_entry = arm720t_post_debug_entry;
470 arm7_9->pre_restore_context = arm720t_pre_restore_context;
471
472 arm720t->armv4_5_mmu.armv4_5_cache.ctype = -1;
473 arm720t->armv4_5_mmu.get_ttb = arm720t_get_ttb;
474 arm720t->armv4_5_mmu.read_memory = arm7_9_read_memory;
475 arm720t->armv4_5_mmu.write_memory = arm7_9_write_memory;
476 arm720t->armv4_5_mmu.disable_mmu_caches = arm720t_disable_mmu_caches;
477 arm720t->armv4_5_mmu.enable_mmu_caches = arm720t_enable_mmu_caches;
478 arm720t->armv4_5_mmu.has_tiny_pages = 0;
479 arm720t->armv4_5_mmu.mmu_enabled = 0;
480
481 return ERROR_OK;
482 }
483
484 int arm720t_target_create(struct target_s *target, Jim_Interp *interp)
485 {
486 arm720t_common_t *arm720t = calloc(1,sizeof(arm720t_common_t));
487
488 arm720t_init_arch_info(target, arm720t, target->tap, target->variant);
489
490 return ERROR_OK;
491 }
492
493 int arm720t_register_commands(struct command_context_s *cmd_ctx)
494 {
495 int retval;
496 command_t *arm720t_cmd;
497
498
499 retval = arm7tdmi_register_commands(cmd_ctx);
500
501 arm720t_cmd = register_command(cmd_ctx, NULL, "arm720t", NULL, COMMAND_ANY, "arm720t specific commands");
502
503 register_command(cmd_ctx, arm720t_cmd, "cp15", arm720t_handle_cp15_command, COMMAND_EXEC, "display/modify cp15 register <opcode> [value]");
504 register_command(cmd_ctx, arm720t_cmd, "virt2phys", arm720t_handle_virt2phys_command, COMMAND_EXEC, "translate va to pa <va>");
505
506 register_command(cmd_ctx, arm720t_cmd, "mdw_phys", arm720t_handle_md_phys_command, COMMAND_EXEC, "display memory words <physical addr> [count]");
507 register_command(cmd_ctx, arm720t_cmd, "mdh_phys", arm720t_handle_md_phys_command, COMMAND_EXEC, "display memory half-words <physical addr> [count]");
508 register_command(cmd_ctx, arm720t_cmd, "mdb_phys", arm720t_handle_md_phys_command, COMMAND_EXEC, "display memory bytes <physical addr> [count]");
509
510 register_command(cmd_ctx, arm720t_cmd, "mww_phys", arm720t_handle_mw_phys_command, COMMAND_EXEC, "write memory word <physical addr> <value>");
511 register_command(cmd_ctx, arm720t_cmd, "mwh_phys", arm720t_handle_mw_phys_command, COMMAND_EXEC, "write memory half-word <physical addr> <value>");
512 register_command(cmd_ctx, arm720t_cmd, "mwb_phys", arm720t_handle_mw_phys_command, COMMAND_EXEC, "write memory byte <physical addr> <value>");
513
514 return ERROR_OK;
515 }
516
517 int arm720t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
518 {
519 int retval;
520 target_t *target = get_current_target(cmd_ctx);
521 armv4_5_common_t *armv4_5;
522 arm7_9_common_t *arm7_9;
523 arm7tdmi_common_t *arm7tdmi;
524 arm720t_common_t *arm720t;
525 arm_jtag_t *jtag_info;
526
527 if (arm720t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm7tdmi, &arm720t) != ERROR_OK)
528 {
529 command_print(cmd_ctx, "current target isn't an ARM720t target");
530 return ERROR_OK;
531 }
532
533 jtag_info = &arm7_9->jtag_info;
534
535 if (target->state != TARGET_HALTED)
536 {
537 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
538 return ERROR_OK;
539 }
540
541 /* one or more argument, access a single register (write if second argument is given */
542 if (argc >= 1)
543 {
544 u32 opcode = strtoul(args[0], NULL, 0);
545
546 if (argc == 1)
547 {
548 u32 value;
549 if ((retval = arm720t_read_cp15(target, opcode, &value)) != ERROR_OK)
550 {
551 command_print(cmd_ctx, "couldn't access cp15 with opcode 0x%8.8x", opcode);
552 return ERROR_OK;
553 }
554
555 if ((retval = jtag_execute_queue()) != ERROR_OK)
556 {
557 return retval;
558 }
559
560 command_print(cmd_ctx, "0x%8.8x: 0x%8.8x", opcode, value);
561 }
562 else if (argc == 2)
563 {
564 u32 value = strtoul(args[1], NULL, 0);
565 if ((retval = arm720t_write_cp15(target, opcode, value)) != ERROR_OK)
566 {
567 command_print(cmd_ctx, "couldn't access cp15 with opcode 0x%8.8x", opcode);
568 return ERROR_OK;
569 }
570 command_print(cmd_ctx, "0x%8.8x: 0x%8.8x", opcode, value);
571 }
572 }
573
574 return ERROR_OK;
575 }
576
577 int arm720t_handle_virt2phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
578 {
579 target_t *target = get_current_target(cmd_ctx);
580 armv4_5_common_t *armv4_5;
581 arm7_9_common_t *arm7_9;
582 arm7tdmi_common_t *arm7tdmi;
583 arm720t_common_t *arm720t;
584 arm_jtag_t *jtag_info;
585
586 if (arm720t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm7tdmi, &arm720t) != ERROR_OK)
587 {
588 command_print(cmd_ctx, "current target isn't an ARM720t target");
589 return ERROR_OK;
590 }
591
592 jtag_info = &arm7_9->jtag_info;
593
594 if (target->state != TARGET_HALTED)
595 {
596 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
597 return ERROR_OK;
598 }
599
600 return armv4_5_mmu_handle_virt2phys_command(cmd_ctx, cmd, args, argc, target, &arm720t->armv4_5_mmu);
601 }
602
603 int arm720t_handle_md_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
604 {
605 target_t *target = get_current_target(cmd_ctx);
606 armv4_5_common_t *armv4_5;
607 arm7_9_common_t *arm7_9;
608 arm7tdmi_common_t *arm7tdmi;
609 arm720t_common_t *arm720t;
610 arm_jtag_t *jtag_info;
611
612 if (arm720t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm7tdmi, &arm720t) != ERROR_OK)
613 {
614 command_print(cmd_ctx, "current target isn't an ARM720t target");
615 return ERROR_OK;
616 }
617
618 jtag_info = &arm7_9->jtag_info;
619
620 if (target->state != TARGET_HALTED)
621 {
622 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
623 return ERROR_OK;
624 }
625
626 return armv4_5_mmu_handle_md_phys_command(cmd_ctx, cmd, args, argc, target, &arm720t->armv4_5_mmu);
627 }
628
629 int arm720t_handle_mw_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
630 {
631 target_t *target = get_current_target(cmd_ctx);
632 armv4_5_common_t *armv4_5;
633 arm7_9_common_t *arm7_9;
634 arm7tdmi_common_t *arm7tdmi;
635 arm720t_common_t *arm720t;
636 arm_jtag_t *jtag_info;
637
638 if (arm720t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm7tdmi, &arm720t) != ERROR_OK)
639 {
640 command_print(cmd_ctx, "current target isn't an ARM720t target");
641 return ERROR_OK;
642 }
643
644 jtag_info = &arm7_9->jtag_info;
645
646 if (target->state != TARGET_HALTED)
647 {
648 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
649 return ERROR_OK;
650 }
651
652 return armv4_5_mmu_handle_mw_phys_command(cmd_ctx, cmd, args, argc, target, &arm720t->armv4_5_mmu);
653 }