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[openocd.git] / src / target / arm11_dbgtap.c
1 /***************************************************************************
2 * Copyright (C) 2008 digenius technology GmbH. *
3 * *
4 * Copyright (C) 2008 Oyvind Harboe oyvind.harboe@zylin.com *
5 * *
6 * This program is free software; you can redistribute it and/or modify *
7 * it under the terms of the GNU General Public License as published by *
8 * the Free Software Foundation; either version 2 of the License, or *
9 * (at your option) any later version. *
10 * *
11 * This program is distributed in the hope that it will be useful, *
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
14 * GNU General Public License for more details. *
15 * *
16 * You should have received a copy of the GNU General Public License *
17 * along with this program; if not, write to the *
18 * Free Software Foundation, Inc., *
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
20 ***************************************************************************/
21
22 #ifdef HAVE_CONFIG_H
23 #include "config.h"
24 #endif
25
26 #include "arm11.h"
27 #include "jtag.h"
28 #include "log.h"
29
30 #include <stdlib.h>
31 #include <string.h>
32
33 #if 0
34 #define JTAG_DEBUG(expr ...) DEBUG(expr)
35 #else
36 #define JTAG_DEBUG(expr ...) do {} while(0)
37 #endif
38
39 enum tap_state arm11_move_pi_to_si_via_ci[] =
40 {
41 TAP_E2I, TAP_UI, TAP_SDS, TAP_SIS, TAP_CI, TAP_SI
42 };
43
44
45 int arm11_add_ir_scan_vc(int num_fields, scan_field_t *fields, enum tap_state state)
46 {
47 if (cmd_queue_cur_state == TAP_PI)
48 jtag_add_pathmove(asizeof(arm11_move_pi_to_si_via_ci), arm11_move_pi_to_si_via_ci);
49
50 jtag_add_ir_scan(num_fields, fields, state);
51 return ERROR_OK;
52 }
53
54 enum tap_state arm11_move_pd_to_sd_via_cd[] =
55 {
56 TAP_E2D, TAP_UD, TAP_SDS, TAP_CD, TAP_SD
57 };
58
59 int arm11_add_dr_scan_vc(int num_fields, scan_field_t *fields, enum tap_state state)
60 {
61 if (cmd_queue_cur_state == TAP_PD)
62 jtag_add_pathmove(asizeof(arm11_move_pd_to_sd_via_cd), arm11_move_pd_to_sd_via_cd);
63
64 jtag_add_dr_scan(num_fields, fields, state);
65 return ERROR_OK;
66 }
67
68
69 /** Code de-clutter: Construct scan_field_t to write out a value
70 *
71 * \param arm11 Target state variable.
72 * \param num_bits Length of the data field
73 * \param out_data pointer to the data that will be sent out
74 * <em>(data is read when it is added to the JTAG queue)</em>
75 * \param in_data pointer to the memory that will receive data that was clocked in
76 * <em>(data is written when the JTAG queue is executed)</em>
77 * \param field target data structure that will be initialized
78 */
79 void arm11_setup_field(arm11_common_t * arm11, int num_bits, void * out_data, void * in_data, scan_field_t * field)
80 {
81 field->device = arm11->jtag_info.chain_pos;
82 field->num_bits = num_bits;
83 field->out_mask = NULL;
84 field->in_check_mask = NULL;
85 field->in_check_value = NULL;
86 field->in_handler = NULL;
87 field->in_handler_priv = NULL;
88
89 field->out_value = out_data;
90 field->in_value = in_data;
91 }
92
93
94 /** Write JTAG instruction register
95 *
96 * \param arm11 Target state variable.
97 * \param instr An ARM11 DBGTAP instruction. Use enum #arm11_instructions.
98 * \param state Pass the final TAP state or -1 for the default value (Pause-IR).
99 *
100 * \remarks This adds to the JTAG command queue but does \em not execute it.
101 */
102 void arm11_add_IR(arm11_common_t * arm11, u8 instr, enum tap_state state)
103 {
104 jtag_device_t *device = jtag_get_device(arm11->jtag_info.chain_pos);
105
106 if (buf_get_u32(device->cur_instr, 0, 5) == instr)
107 {
108 JTAG_DEBUG("IR <= 0x%02x SKIPPED", instr);
109 return;
110 }
111
112 JTAG_DEBUG("IR <= 0x%02x", instr);
113
114 scan_field_t field;
115
116 arm11_setup_field(arm11, 5, &instr, NULL, &field);
117
118 arm11_add_ir_scan_vc(1, &field, state == -1 ? TAP_PI : state);
119 }
120
121 /** Verify shifted out data from Scan Chain Register (SCREG)
122 * Used as parameter to scan_field_t::in_handler in
123 * arm11_add_debug_SCAN_N().
124 *
125 */
126 static int arm11_in_handler_SCAN_N(u8 *in_value, void *priv, struct scan_field_s *field)
127 {
128 /** \todo TODO: clarify why this isnt properly masked in jtag.c jtag_read_buffer() */
129 u8 v = *in_value & 0x1F;
130
131 if (v != 0x10)
132 {
133 LOG_ERROR("'arm11 target' JTAG communication error SCREG SCAN OUT 0x%02x (expected 0x10)", v);
134 return ERROR_FAIL;
135 }
136
137 JTAG_DEBUG("SCREG SCAN OUT 0x%02x", v);
138 return ERROR_OK;
139 }
140
141 /** Select and write to Scan Chain Register (SCREG)
142 *
143 * This function sets the instruction register to SCAN_N and writes
144 * the data register with the selected chain number.
145 *
146 * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0301f/Cacbjhfg.html
147 *
148 * \param arm11 Target state variable.
149 * \param chain Scan chain that will be selected.
150 * \param state Pass the final TAP state or -1 for the default
151 * value (Pause-DR).
152 *
153 * The chain takes effect when Update-DR is passed (usually when subsequently
154 * the INTEXT/EXTEST instructions are written).
155 *
156 * \warning (Obsolete) Using this twice in a row will \em fail. The first call will end
157 * in Pause-DR. The second call, due to the IR caching, will not
158 * go through Capture-DR when shifting in the new scan chain number.
159 * As a result the verification in arm11_in_handler_SCAN_N() must
160 * fail.
161 *
162 * \remarks This adds to the JTAG command queue but does \em not execute it.
163 */
164
165 void arm11_add_debug_SCAN_N(arm11_common_t * arm11, u8 chain, enum tap_state state)
166 {
167 JTAG_DEBUG("SCREG <= 0x%02x", chain);
168
169 arm11_add_IR(arm11, ARM11_SCAN_N, -1);
170
171 scan_field_t field;
172
173 arm11_setup_field(arm11, 5, &chain, NULL, &field);
174
175 field.in_handler = arm11_in_handler_SCAN_N;
176
177 arm11_add_dr_scan_vc(1, &field, state == -1 ? TAP_PD : state);
178 }
179
180 /** Write an instruction into the ITR register
181 *
182 * \param arm11 Target state variable.
183 * \param inst An ARM11 processor instruction/opcode.
184 * \param flag Optional parameter to retrieve the InstCompl flag
185 * (this will be written when the JTAG chain is executed).
186 * \param state Pass the final TAP state or -1 for the default
187 * value (Run-Test/Idle).
188 *
189 * \remarks By default this ends with Run-Test/Idle state
190 * and causes the instruction to be executed. If
191 * a subsequent write to DTR is needed before
192 * executing the instruction then TAP_PD should be
193 * passed to \p state.
194 *
195 * \remarks This adds to the JTAG command queue but does \em not execute it.
196 */
197 void arm11_add_debug_INST(arm11_common_t * arm11, u32 inst, u8 * flag, enum tap_state state)
198 {
199 JTAG_DEBUG("INST <= 0x%08x", inst);
200
201 scan_field_t itr[2];
202
203 arm11_setup_field(arm11, 32, &inst, NULL, itr + 0);
204 arm11_setup_field(arm11, 1, NULL, flag, itr + 1);
205
206 arm11_add_dr_scan_vc(asizeof(itr), itr, state == -1 ? TAP_RTI : state);
207 }
208
209 /** Read the Debug Status and Control Register (DSCR)
210 *
211 * same as CP14 c1
212 *
213 * \param arm11 Target state variable.
214 * \return DSCR content
215 *
216 * \remarks This is a stand-alone function that executes the JTAG command queue.
217 */
218 u32 arm11_read_DSCR(arm11_common_t * arm11)
219 {
220 arm11_add_debug_SCAN_N(arm11, 0x01, -1);
221
222 arm11_add_IR(arm11, ARM11_INTEST, -1);
223
224 u32 dscr;
225 scan_field_t chain1_field;
226
227 arm11_setup_field(arm11, 32, NULL, &dscr, &chain1_field);
228
229 arm11_add_dr_scan_vc(1, &chain1_field, TAP_PD);
230
231 jtag_execute_queue();
232
233 if (arm11->last_dscr != dscr)
234 JTAG_DEBUG("DSCR = %08x (OLD %08x)", dscr, arm11->last_dscr);
235
236 arm11->last_dscr = dscr;
237
238 return dscr;
239 }
240
241 /** Write the Debug Status and Control Register (DSCR)
242 *
243 * same as CP14 c1
244 *
245 * \param arm11 Target state variable.
246 * \param dscr DSCR content
247 *
248 * \remarks This is a stand-alone function that executes the JTAG command queue.
249 */
250 void arm11_write_DSCR(arm11_common_t * arm11, u32 dscr)
251 {
252 arm11_add_debug_SCAN_N(arm11, 0x01, -1);
253
254 arm11_add_IR(arm11, ARM11_EXTEST, -1);
255
256 scan_field_t chain1_field;
257
258 arm11_setup_field(arm11, 32, &dscr, NULL, &chain1_field);
259
260 arm11_add_dr_scan_vc(1, &chain1_field, TAP_PD);
261
262 jtag_execute_queue();
263
264 JTAG_DEBUG("DSCR <= %08x (OLD %08x)", dscr, arm11->last_dscr);
265
266 arm11->last_dscr = dscr;
267 }
268
269
270
271 /** Get the debug reason from Debug Status and Control Register (DSCR)
272 *
273 * \param dscr DSCR value to analyze
274 * \return Debug reason
275 *
276 */
277 enum target_debug_reason arm11_get_DSCR_debug_reason(u32 dscr)
278 {
279 switch (dscr & ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_MASK)
280 {
281 case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_HALT:
282 LOG_INFO("Debug entry: JTAG HALT");
283 return DBG_REASON_DBGRQ;
284
285 case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BREAKPOINT:
286 LOG_INFO("Debug entry: breakpoint");
287 return DBG_REASON_BREAKPOINT;
288
289 case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_WATCHPOINT:
290 LOG_INFO("Debug entry: watchpoint");
291 return DBG_REASON_WATCHPOINT;
292
293 case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BKPT_INSTRUCTION:
294 LOG_INFO("Debug entry: BKPT instruction");
295 return DBG_REASON_BREAKPOINT;
296
297 case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_EDBGRQ:
298 LOG_INFO("Debug entry: EDBGRQ signal");
299 return DBG_REASON_DBGRQ;
300
301 case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_VECTOR_CATCH:
302 LOG_INFO("Debug entry: VCR vector catch");
303 return DBG_REASON_BREAKPOINT;
304
305 default:
306 LOG_INFO("Debug entry: unknown");
307 return DBG_REASON_DBGRQ;
308 }
309 };
310
311
312
313 /** Prepare the stage for ITR/DTR operations
314 * from the arm11_run_instr... group of functions.
315 *
316 * Put arm11_run_instr_data_prepare() and arm11_run_instr_data_finish()
317 * around a block of arm11_run_instr_... calls.
318 *
319 * Select scan chain 5 to allow quick access to DTR. When scan
320 * chain 4 is needed to put in a register the ITRSel instruction
321 * shortcut is used instead of actually changing the Scan_N
322 * register.
323 *
324 * \param arm11 Target state variable.
325 *
326 */
327 void arm11_run_instr_data_prepare(arm11_common_t * arm11)
328 {
329 arm11_add_debug_SCAN_N(arm11, 0x05, -1);
330 }
331
332 /** Cleanup after ITR/DTR operations
333 * from the arm11_run_instr... group of functions
334 *
335 * Put arm11_run_instr_data_prepare() and arm11_run_instr_data_finish()
336 * around a block of arm11_run_instr_... calls.
337 *
338 * Any RTI can lead to an instruction execution when
339 * scan chains 4 or 5 are selected and the IR holds
340 * INTEST or EXTEST. So we must disable that before
341 * any following activities lead to an RTI.
342 *
343 * \param arm11 Target state variable.
344 *
345 */
346 void arm11_run_instr_data_finish(arm11_common_t * arm11)
347 {
348 arm11_add_debug_SCAN_N(arm11, 0x00, -1);
349 }
350
351
352 /** Execute one or multiple instructions via ITR
353 *
354 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
355 *
356 * \param arm11 Target state variable.
357 * \param opcode Pointer to sequence of ARM opcodes
358 * \param count Number of opcodes to execute
359 *
360 */
361 void arm11_run_instr_no_data(arm11_common_t * arm11, u32 * opcode, size_t count)
362 {
363 arm11_add_IR(arm11, ARM11_ITRSEL, -1);
364
365 while (count--)
366 {
367 arm11_add_debug_INST(arm11, *opcode++, NULL, TAP_RTI);
368
369 while (1)
370 {
371 u8 flag;
372
373 arm11_add_debug_INST(arm11, 0, &flag, count ? TAP_RTI : TAP_PD);
374
375 jtag_execute_queue();
376
377 if (flag)
378 break;
379 }
380 }
381 }
382
383 /** Execute one instruction via ITR
384 *
385 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
386 *
387 * \param arm11 Target state variable.
388 * \param opcode ARM opcode
389 *
390 */
391 void arm11_run_instr_no_data1(arm11_common_t * arm11, u32 opcode)
392 {
393 arm11_run_instr_no_data(arm11, &opcode, 1);
394 }
395
396
397 /** Execute one instruction via ITR repeatedly while
398 * passing data to the core via DTR on each execution.
399 *
400 * The executed instruction \em must read data from DTR.
401 *
402 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
403 *
404 * \param arm11 Target state variable.
405 * \param opcode ARM opcode
406 * \param data Pointer to the data words to be passed to the core
407 * \param count Number of data words and instruction repetitions
408 *
409 */
410 void arm11_run_instr_data_to_core(arm11_common_t * arm11, u32 opcode, u32 * data, size_t count)
411 {
412 arm11_add_IR(arm11, ARM11_ITRSEL, -1);
413
414 arm11_add_debug_INST(arm11, opcode, NULL, TAP_PD);
415
416 arm11_add_IR(arm11, ARM11_EXTEST, -1);
417
418 scan_field_t chain5_fields[3];
419
420 u32 Data;
421 u8 Ready;
422 u8 nRetry;
423
424 arm11_setup_field(arm11, 32, &Data, NULL, chain5_fields + 0);
425 arm11_setup_field(arm11, 1, NULL, &Ready, chain5_fields + 1);
426 arm11_setup_field(arm11, 1, NULL, &nRetry, chain5_fields + 2);
427
428 while (count--)
429 {
430 do
431 {
432 Data = *data;
433
434 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_RTI);
435 jtag_execute_queue();
436
437 JTAG_DEBUG("DTR Ready %d nRetry %d", Ready, nRetry);
438 }
439 while (!Ready);
440
441 data++;
442 }
443
444 arm11_add_IR(arm11, ARM11_INTEST, -1);
445
446 do
447 {
448 Data = 0;
449
450 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_PD);
451 jtag_execute_queue();
452
453 JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d", Data, Ready, nRetry);
454 }
455 while (!Ready);
456 }
457
458 /** JTAG path for arm11_run_instr_data_to_core_noack
459 *
460 * The repeated TAP_RTI's do not cause a repeated execution
461 * if passed without leaving the state.
462 *
463 * Since this is more than 7 bits (adjustable via adding more
464 * TAP_RTI's) it produces an artificial delay in the lower
465 * layer (FT2232) that is long enough to finish execution on
466 * the core but still shorter than any manually inducible delays.
467 *
468 */
469 enum tap_state arm11_MOVE_PD_RTI_PD_with_delay[] =
470 {
471 TAP_E2D, TAP_UD, TAP_RTI, TAP_RTI, TAP_RTI, TAP_SDS, TAP_CD, TAP_SD
472 };
473
474
475
476 /** Execute one instruction via ITR repeatedly while
477 * passing data to the core via DTR on each execution.
478 *
479 * No Ready check during transmission.
480 *
481 * The executed instruction \em must read data from DTR.
482 *
483 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
484 *
485 * \param arm11 Target state variable.
486 * \param opcode ARM opcode
487 * \param data Pointer to the data words to be passed to the core
488 * \param count Number of data words and instruction repetitions
489 *
490 */
491 void arm11_run_instr_data_to_core_noack(arm11_common_t * arm11, u32 opcode, u32 * data, size_t count)
492 {
493 arm11_add_IR(arm11, ARM11_ITRSEL, -1);
494
495 arm11_add_debug_INST(arm11, opcode, NULL, TAP_PD);
496
497 arm11_add_IR(arm11, ARM11_EXTEST, -1);
498
499 scan_field_t chain5_fields[3];
500
501 arm11_setup_field(arm11, 32, NULL/*&Data*/, NULL, chain5_fields + 0);
502 arm11_setup_field(arm11, 1, NULL, NULL /*&Ready*/, chain5_fields + 1);
503 arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 2);
504
505 u8 Readies[count + 1];
506 u8 * ReadyPos = Readies;
507
508 while (count--)
509 {
510 chain5_fields[0].out_value = (void *)(data++);
511 chain5_fields[1].in_value = ReadyPos++;
512
513 if (count)
514 {
515 jtag_add_dr_scan(asizeof(chain5_fields), chain5_fields, TAP_PD);
516 jtag_add_pathmove(asizeof(arm11_MOVE_PD_RTI_PD_with_delay),
517 arm11_MOVE_PD_RTI_PD_with_delay);
518 }
519 else
520 {
521 jtag_add_dr_scan(asizeof(chain5_fields), chain5_fields, TAP_RTI);
522 }
523 }
524
525 arm11_add_IR(arm11, ARM11_INTEST, -1);
526
527 chain5_fields[0].out_value = 0;
528 chain5_fields[1].in_value = ReadyPos++;
529
530 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_PD);
531
532 jtag_execute_queue();
533
534 size_t error_count = 0;
535
536 {size_t i;
537 for (i = 0; i < asizeof(Readies); i++)
538 {
539 if (Readies[i] != 1)
540 {
541 error_count++;
542 }
543 }}
544
545 if (error_count)
546 LOG_ERROR("Transfer errors " ZU, error_count);
547 }
548
549
550 /** Execute an instruction via ITR while handing data into the core via DTR.
551 *
552 * The executed instruction \em must read data from DTR.
553 *
554 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
555 *
556 * \param arm11 Target state variable.
557 * \param opcode ARM opcode
558 * \param data Data word to be passed to the core via DTR
559 *
560 */
561 void arm11_run_instr_data_to_core1(arm11_common_t * arm11, u32 opcode, u32 data)
562 {
563 arm11_run_instr_data_to_core(arm11, opcode, &data, 1);
564 }
565
566
567 /** Execute one instruction via ITR repeatedly while
568 * reading data from the core via DTR on each execution.
569 *
570 * The executed instruction \em must write data to DTR.
571 *
572 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
573 *
574 * \param arm11 Target state variable.
575 * \param opcode ARM opcode
576 * \param data Pointer to an array that receives the data words from the core
577 * \param count Number of data words and instruction repetitions
578 *
579 */
580 void arm11_run_instr_data_from_core(arm11_common_t * arm11, u32 opcode, u32 * data, size_t count)
581 {
582 arm11_add_IR(arm11, ARM11_ITRSEL, -1);
583
584 arm11_add_debug_INST(arm11, opcode, NULL, TAP_RTI);
585
586 arm11_add_IR(arm11, ARM11_INTEST, -1);
587
588 scan_field_t chain5_fields[3];
589
590 u32 Data;
591 u8 Ready;
592 u8 nRetry;
593
594 arm11_setup_field(arm11, 32, NULL, &Data, chain5_fields + 0);
595 arm11_setup_field(arm11, 1, NULL, &Ready, chain5_fields + 1);
596 arm11_setup_field(arm11, 1, NULL, &nRetry, chain5_fields + 2);
597
598 while (count--)
599 {
600 do
601 {
602 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, count ? TAP_RTI : TAP_PD);
603 jtag_execute_queue();
604
605 JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d", Data, Ready, nRetry);
606 }
607 while (!Ready);
608
609 *data++ = Data;
610 }
611 }
612
613 /** Execute one instruction via ITR
614 * then load r0 into DTR and read DTR from core.
615 *
616 * The first executed instruction (\p opcode) should write data to r0.
617 *
618 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
619 *
620 * \param arm11 Target state variable.
621 * \param opcode ARM opcode to write r0 with the value of interest
622 * \param data Pointer to a data word that receives the value from r0 after \p opcode was executed.
623 *
624 */
625 void arm11_run_instr_data_from_core_via_r0(arm11_common_t * arm11, u32 opcode, u32 * data)
626 {
627 arm11_run_instr_no_data1(arm11, opcode);
628
629 /* MCR p14,0,R0,c0,c5,0 (move r0 -> wDTR -> local var) */
630 arm11_run_instr_data_from_core(arm11, 0xEE000E15, data, 1);
631 }
632
633 /** Load data into core via DTR then move it to r0 then
634 * execute one instruction via ITR
635 *
636 * The final executed instruction (\p opcode) should read data from r0.
637 *
638 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
639 *
640 * \param arm11 Target state variable.
641 * \param opcode ARM opcode to read r0 act upon it
642 * \param data Data word that will be written to r0 before \p opcode is executed
643 *
644 */
645 void arm11_run_instr_data_to_core_via_r0(arm11_common_t * arm11, u32 opcode, u32 data)
646 {
647 /* MRC p14,0,r0,c0,c5,0 */
648 arm11_run_instr_data_to_core1(arm11, 0xEE100E15, data);
649
650 arm11_run_instr_no_data1(arm11, opcode);
651 }
652
653 /** Apply reads and writes to scan chain 7
654 *
655 * \see arm11_sc7_action_t
656 *
657 * \param arm11 Target state variable.
658 * \param actions A list of read and/or write instructions
659 * \param count Number of instructions in the list.
660 *
661 */
662 void arm11_sc7_run(arm11_common_t * arm11, arm11_sc7_action_t * actions, size_t count)
663 {
664 arm11_add_debug_SCAN_N(arm11, 0x07, -1);
665
666 arm11_add_IR(arm11, ARM11_EXTEST, -1);
667
668 scan_field_t chain7_fields[3];
669
670 u8 nRW;
671 u32 DataOut;
672 u8 AddressOut;
673 u8 Ready;
674 u32 DataIn;
675 u8 AddressIn;
676
677 arm11_setup_field(arm11, 1, &nRW, &Ready, chain7_fields + 0);
678 arm11_setup_field(arm11, 32, &DataOut, &DataIn, chain7_fields + 1);
679 arm11_setup_field(arm11, 7, &AddressOut, &AddressIn, chain7_fields + 2);
680
681 {size_t i;
682 for (i = 0; i < count + 1; i++)
683 {
684 if (i < count)
685 {
686 nRW = actions[i].write ? 1 : 0;
687 DataOut = actions[i].value;
688 AddressOut = actions[i].address;
689 }
690 else
691 {
692 nRW = 0;
693 DataOut = 0;
694 AddressOut = 0;
695 }
696
697 do
698 {
699 JTAG_DEBUG("SC7 <= Address %02x Data %08x nRW %d", AddressOut, DataOut, nRW);
700
701 arm11_add_dr_scan_vc(asizeof(chain7_fields), chain7_fields, TAP_PD);
702 jtag_execute_queue();
703
704 JTAG_DEBUG("SC7 => Address %02x Data %08x Ready %d", AddressIn, DataIn, Ready);
705 }
706 while (!Ready); /* 'nRW' is 'Ready' on read out */
707
708 if (i > 0)
709 {
710 if (actions[i - 1].address != AddressIn)
711 {
712 LOG_WARNING("Scan chain 7 shifted out unexpected address");
713 }
714
715 if (!actions[i - 1].write)
716 {
717 actions[i - 1].value = DataIn;
718 }
719 else
720 {
721 if (actions[i - 1].value != DataIn)
722 {
723 LOG_WARNING("Scan chain 7 shifted out unexpected data");
724 }
725 }
726 }
727 }}
728
729 {size_t i;
730 for (i = 0; i < count; i++)
731 {
732 JTAG_DEBUG("SC7 %02d: %02x %s %08x", i, actions[i].address, actions[i].write ? "<=" : "=>", actions[i].value);
733 }}
734 }
735
736 /** Clear VCR and all breakpoints and watchpoints via scan chain 7
737 *
738 * \param arm11 Target state variable.
739 *
740 */
741 void arm11_sc7_clear_vbw(arm11_common_t * arm11)
742 {
743 arm11_sc7_action_t clear_bw[arm11->brp + arm11->wrp + 1];
744 arm11_sc7_action_t * pos = clear_bw;
745
746 {size_t i;
747 for (i = 0; i < asizeof(clear_bw); i++)
748 {
749 clear_bw[i].write = true;
750 clear_bw[i].value = 0;
751 }}
752
753 {size_t i;
754 for (i = 0; i < arm11->brp; i++)
755 (pos++)->address = ARM11_SC7_BCR0 + i;
756 }
757
758 {size_t i;
759 for (i = 0; i < arm11->wrp; i++)
760 (pos++)->address = ARM11_SC7_WCR0 + i;
761 }
762
763 (pos++)->address = ARM11_SC7_VCR;
764
765 arm11_sc7_run(arm11, clear_bw, asizeof(clear_bw));
766 }
767
768 /** Write VCR register
769 *
770 * \param arm11 Target state variable.
771 * \param value Value to be written
772 */
773 void arm11_sc7_set_vcr(arm11_common_t * arm11, u32 value)
774 {
775 arm11_sc7_action_t set_vcr;
776
777 set_vcr.write = true;
778 set_vcr.address = ARM11_SC7_VCR;
779 set_vcr.value = value;
780
781
782 arm11_sc7_run(arm11, &set_vcr, 1);
783 }
784
785
786
787 /** Read word from address
788 *
789 * \param arm11 Target state variable.
790 * \param address Memory address to be read
791 * \param result Pointer where to store result
792 *
793 */
794 void arm11_read_memory_word(arm11_common_t * arm11, u32 address, u32 * result)
795 {
796 arm11_run_instr_data_prepare(arm11);
797
798 /* MRC p14,0,r0,c0,c5,0 (r0 = address) */
799 arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
800
801 /* LDC p14,c5,[R0],#4 (DTR = [r0]) */
802 arm11_run_instr_data_from_core(arm11, 0xecb05e01, result, 1);
803
804 arm11_run_instr_data_finish(arm11);
805 }
806
807