1 /***************************************************************************
2 * Copyright (C) 2008 digenius technology GmbH. *
4 * Copyright (C) 2008 Oyvind Harboe oyvind.harboe@zylin.com *
6 * This program is free software; you can redistribute it and/or modify *
7 * it under the terms of the GNU General Public License as published by *
8 * the Free Software Foundation; either version 2 of the License, or *
9 * (at your option) any later version. *
11 * This program is distributed in the hope that it will be useful, *
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
14 * GNU General Public License for more details. *
16 * You should have received a copy of the GNU General Public License *
17 * along with this program; if not, write to the *
18 * Free Software Foundation, Inc., *
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
20 ***************************************************************************/
34 #define JTAG_DEBUG(expr ...) DEBUG(expr)
36 #define JTAG_DEBUG(expr ...) do {} while(0)
39 tap_state_t arm11_move_pi_to_si_via_ci
[] =
41 TAP_IREXIT2
, TAP_IRUPDATE
, TAP_DRSELECT
, TAP_IRSELECT
, TAP_IRCAPTURE
, TAP_IRSHIFT
45 int arm11_add_ir_scan_vc(int num_fields
, scan_field_t
*fields
, tap_state_t state
)
47 if (cmd_queue_cur_state
== TAP_IRPAUSE
)
48 jtag_add_pathmove(asizeof(arm11_move_pi_to_si_via_ci
), arm11_move_pi_to_si_via_ci
);
50 jtag_add_ir_scan(num_fields
, fields
, state
);
54 tap_state_t arm11_move_pd_to_sd_via_cd
[] =
56 TAP_DREXIT2
, TAP_DRUPDATE
, TAP_DRSELECT
, TAP_DRCAPTURE
, TAP_DRSHIFT
59 int arm11_add_dr_scan_vc(int num_fields
, scan_field_t
*fields
, tap_state_t state
)
61 if (cmd_queue_cur_state
== TAP_DRPAUSE
)
62 jtag_add_pathmove(asizeof(arm11_move_pd_to_sd_via_cd
), arm11_move_pd_to_sd_via_cd
);
64 jtag_add_dr_scan(num_fields
, fields
, state
);
69 /** Code de-clutter: Construct scan_field_t to write out a value
71 * \param arm11 Target state variable.
72 * \param num_bits Length of the data field
73 * \param out_data pointer to the data that will be sent out
74 * <em>(data is read when it is added to the JTAG queue)</em>
75 * \param in_data pointer to the memory that will receive data that was clocked in
76 * <em>(data is written when the JTAG queue is executed)</em>
77 * \param field target data structure that will be initialized
79 void arm11_setup_field(arm11_common_t
* arm11
, int num_bits
, void * out_data
, void * in_data
, scan_field_t
* field
)
81 field
->tap
= arm11
->jtag_info
.tap
;
82 field
->num_bits
= num_bits
;
83 field
->out_mask
= NULL
;
84 field
->in_check_mask
= NULL
;
85 field
->in_check_value
= NULL
;
86 field
->in_handler
= NULL
;
87 field
->in_handler_priv
= NULL
;
89 field
->out_value
= out_data
;
90 field
->in_value
= in_data
;
94 /** Write JTAG instruction register
96 * \param arm11 Target state variable.
97 * \param instr An ARM11 DBGTAP instruction. Use enum #arm11_instructions.
98 * \param state Pass the final TAP state or ARM11_TAP_DEFAULT for the default value (Pause-IR).
100 * \remarks This adds to the JTAG command queue but does \em not execute it.
102 void arm11_add_IR(arm11_common_t
* arm11
, u8 instr
, tap_state_t state
)
105 tap
= arm11
->jtag_info
.tap
;
107 if (buf_get_u32(tap
->cur_instr
, 0, 5) == instr
)
109 JTAG_DEBUG("IR <= 0x%02x SKIPPED", instr
);
113 JTAG_DEBUG("IR <= 0x%02x", instr
);
117 arm11_setup_field(arm11
, 5, &instr
, NULL
, &field
);
119 arm11_add_ir_scan_vc(1, &field
, state
== ARM11_TAP_DEFAULT
? TAP_IRPAUSE
: state
);
122 /** Verify shifted out data from Scan Chain Register (SCREG)
123 * Used as parameter to scan_field_t::in_handler in
124 * arm11_add_debug_SCAN_N().
127 static int arm11_in_handler_SCAN_N(u8
*in_value
, void *priv
, struct scan_field_s
*field
)
129 /** \todo TODO: clarify why this isnt properly masked in jtag.c jtag_read_buffer() */
130 u8 v
= *in_value
& 0x1F;
134 LOG_ERROR("'arm11 target' JTAG communication error SCREG SCAN OUT 0x%02x (expected 0x10)", v
);
138 JTAG_DEBUG("SCREG SCAN OUT 0x%02x", v
);
142 /** Select and write to Scan Chain Register (SCREG)
144 * This function sets the instruction register to SCAN_N and writes
145 * the data register with the selected chain number.
147 * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0301f/Cacbjhfg.html
149 * \param arm11 Target state variable.
150 * \param chain Scan chain that will be selected.
151 * \param state Pass the final TAP state or ARM11_TAP_DEFAULT for the default
154 * The chain takes effect when Update-DR is passed (usually when subsequently
155 * the INTEXT/EXTEST instructions are written).
157 * \warning (Obsolete) Using this twice in a row will \em fail. The first
158 * call will end in Pause-DR. The second call, due to the IR
159 * caching, will not go through Capture-DR when shifting in the
160 * new scan chain number. As a result the verification in
161 * arm11_in_handler_SCAN_N() must fail.
163 * \remarks This adds to the JTAG command queue but does \em not execute it.
166 void arm11_add_debug_SCAN_N(arm11_common_t
* arm11
, u8 chain
, tap_state_t state
)
168 JTAG_DEBUG("SCREG <= 0x%02x", chain
);
170 arm11_add_IR(arm11
, ARM11_SCAN_N
, ARM11_TAP_DEFAULT
);
174 arm11_setup_field(arm11
, 5, &chain
, NULL
, &field
);
176 field
.in_handler
= arm11_in_handler_SCAN_N
;
178 arm11_add_dr_scan_vc(1, &field
, state
== ARM11_TAP_DEFAULT
? TAP_DRPAUSE
: state
);
181 /** Write an instruction into the ITR register
183 * \param arm11 Target state variable.
184 * \param inst An ARM11 processor instruction/opcode.
185 * \param flag Optional parameter to retrieve the InstCompl flag
186 * (this will be written when the JTAG chain is executed).
187 * \param state Pass the final TAP state or ARM11_TAP_DEFAULT for the default
188 * value (Run-Test/Idle).
190 * \remarks By default this ends with Run-Test/Idle state
191 * and causes the instruction to be executed. If
192 * a subsequent write to DTR is needed before
193 * executing the instruction then TAP_DRPAUSE should be
194 * passed to \p state.
196 * \remarks This adds to the JTAG command queue but does \em not execute it.
198 void arm11_add_debug_INST(arm11_common_t
* arm11
, u32 inst
, u8
* flag
, tap_state_t state
)
200 JTAG_DEBUG("INST <= 0x%08x", inst
);
204 arm11_setup_field(arm11
, 32, &inst
, NULL
, itr
+ 0);
205 arm11_setup_field(arm11
, 1, NULL
, flag
, itr
+ 1);
207 arm11_add_dr_scan_vc(asizeof(itr
), itr
, state
== ARM11_TAP_DEFAULT
? TAP_IDLE
: state
);
210 /** Read the Debug Status and Control Register (DSCR)
214 * \param arm11 Target state variable.
215 * \return DSCR content
217 * \remarks This is a stand-alone function that executes the JTAG command queue.
219 int arm11_read_DSCR(arm11_common_t
* arm11
, u32
*value
)
221 arm11_add_debug_SCAN_N(arm11
, 0x01, ARM11_TAP_DEFAULT
);
223 arm11_add_IR(arm11
, ARM11_INTEST
, ARM11_TAP_DEFAULT
);
226 scan_field_t chain1_field
;
228 arm11_setup_field(arm11
, 32, NULL
, &dscr
, &chain1_field
);
230 arm11_add_dr_scan_vc(1, &chain1_field
, TAP_DRPAUSE
);
233 if ((retval
=jtag_execute_queue())!=ERROR_OK
)
238 if (arm11
->last_dscr
!= dscr
)
239 JTAG_DEBUG("DSCR = %08x (OLD %08x)", dscr
, arm11
->last_dscr
);
241 arm11
->last_dscr
= dscr
;
248 /** Write the Debug Status and Control Register (DSCR)
252 * \param arm11 Target state variable.
253 * \param dscr DSCR content
255 * \remarks This is a stand-alone function that executes the JTAG command queue.
257 void arm11_write_DSCR(arm11_common_t
* arm11
, u32 dscr
)
259 arm11_add_debug_SCAN_N(arm11
, 0x01, ARM11_TAP_DEFAULT
);
261 arm11_add_IR(arm11
, ARM11_EXTEST
, ARM11_TAP_DEFAULT
);
263 scan_field_t chain1_field
;
265 arm11_setup_field(arm11
, 32, &dscr
, NULL
, &chain1_field
);
267 arm11_add_dr_scan_vc(1, &chain1_field
, TAP_DRPAUSE
);
269 jtag_execute_queue();
271 JTAG_DEBUG("DSCR <= %08x (OLD %08x)", dscr
, arm11
->last_dscr
);
273 arm11
->last_dscr
= dscr
;
278 /** Get the debug reason from Debug Status and Control Register (DSCR)
280 * \param dscr DSCR value to analyze
281 * \return Debug reason
284 enum target_debug_reason
arm11_get_DSCR_debug_reason(u32 dscr
)
286 switch (dscr
& ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_MASK
)
288 case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_HALT
:
289 LOG_INFO("Debug entry: JTAG HALT");
290 return DBG_REASON_DBGRQ
;
292 case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BREAKPOINT
:
293 LOG_INFO("Debug entry: breakpoint");
294 return DBG_REASON_BREAKPOINT
;
296 case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_WATCHPOINT
:
297 LOG_INFO("Debug entry: watchpoint");
298 return DBG_REASON_WATCHPOINT
;
300 case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BKPT_INSTRUCTION
:
301 LOG_INFO("Debug entry: BKPT instruction");
302 return DBG_REASON_BREAKPOINT
;
304 case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_EDBGRQ
:
305 LOG_INFO("Debug entry: EDBGRQ signal");
306 return DBG_REASON_DBGRQ
;
308 case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_VECTOR_CATCH
:
309 LOG_INFO("Debug entry: VCR vector catch");
310 return DBG_REASON_BREAKPOINT
;
313 LOG_INFO("Debug entry: unknown");
314 return DBG_REASON_DBGRQ
;
320 /** Prepare the stage for ITR/DTR operations
321 * from the arm11_run_instr... group of functions.
323 * Put arm11_run_instr_data_prepare() and arm11_run_instr_data_finish()
324 * around a block of arm11_run_instr_... calls.
326 * Select scan chain 5 to allow quick access to DTR. When scan
327 * chain 4 is needed to put in a register the ITRSel instruction
328 * shortcut is used instead of actually changing the Scan_N
331 * \param arm11 Target state variable.
334 void arm11_run_instr_data_prepare(arm11_common_t
* arm11
)
336 arm11_add_debug_SCAN_N(arm11
, 0x05, ARM11_TAP_DEFAULT
);
339 /** Cleanup after ITR/DTR operations
340 * from the arm11_run_instr... group of functions
342 * Put arm11_run_instr_data_prepare() and arm11_run_instr_data_finish()
343 * around a block of arm11_run_instr_... calls.
345 * Any IDLE can lead to an instruction execution when
346 * scan chains 4 or 5 are selected and the IR holds
347 * INTEST or EXTEST. So we must disable that before
348 * any following activities lead to an IDLE.
350 * \param arm11 Target state variable.
353 void arm11_run_instr_data_finish(arm11_common_t
* arm11
)
355 arm11_add_debug_SCAN_N(arm11
, 0x00, ARM11_TAP_DEFAULT
);
359 /** Execute one or multiple instructions via ITR
361 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
363 * \param arm11 Target state variable.
364 * \param opcode Pointer to sequence of ARM opcodes
365 * \param count Number of opcodes to execute
368 void arm11_run_instr_no_data(arm11_common_t
* arm11
, u32
* opcode
, size_t count
)
370 arm11_add_IR(arm11
, ARM11_ITRSEL
, ARM11_TAP_DEFAULT
);
374 arm11_add_debug_INST(arm11
, *opcode
++, NULL
, TAP_IDLE
);
380 arm11_add_debug_INST(arm11
, 0, &flag
, count
? TAP_IDLE
: TAP_DRPAUSE
);
382 jtag_execute_queue();
390 /** Execute one instruction via ITR
392 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
394 * \param arm11 Target state variable.
395 * \param opcode ARM opcode
398 void arm11_run_instr_no_data1(arm11_common_t
* arm11
, u32 opcode
)
400 arm11_run_instr_no_data(arm11
, &opcode
, 1);
404 /** Execute one instruction via ITR repeatedly while
405 * passing data to the core via DTR on each execution.
407 * The executed instruction \em must read data from DTR.
409 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
411 * \param arm11 Target state variable.
412 * \param opcode ARM opcode
413 * \param data Pointer to the data words to be passed to the core
414 * \param count Number of data words and instruction repetitions
417 void arm11_run_instr_data_to_core(arm11_common_t
* arm11
, u32 opcode
, u32
* data
, size_t count
)
419 arm11_add_IR(arm11
, ARM11_ITRSEL
, ARM11_TAP_DEFAULT
);
421 arm11_add_debug_INST(arm11
, opcode
, NULL
, TAP_DRPAUSE
);
423 arm11_add_IR(arm11
, ARM11_EXTEST
, ARM11_TAP_DEFAULT
);
425 scan_field_t chain5_fields
[3];
431 arm11_setup_field(arm11
, 32, &Data
, NULL
, chain5_fields
+ 0);
432 arm11_setup_field(arm11
, 1, NULL
, &Ready
, chain5_fields
+ 1);
433 arm11_setup_field(arm11
, 1, NULL
, &nRetry
, chain5_fields
+ 2);
441 arm11_add_dr_scan_vc(asizeof(chain5_fields
), chain5_fields
, TAP_IDLE
);
442 jtag_execute_queue();
444 JTAG_DEBUG("DTR Ready %d nRetry %d", Ready
, nRetry
);
451 arm11_add_IR(arm11
, ARM11_INTEST
, ARM11_TAP_DEFAULT
);
457 arm11_add_dr_scan_vc(asizeof(chain5_fields
), chain5_fields
, TAP_DRPAUSE
);
458 jtag_execute_queue();
460 JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d", Data
, Ready
, nRetry
);
465 /** JTAG path for arm11_run_instr_data_to_core_noack
467 * The repeated TAP_IDLE's do not cause a repeated execution
468 * if passed without leaving the state.
470 * Since this is more than 7 bits (adjustable via adding more
471 * TAP_IDLE's) it produces an artificial delay in the lower
472 * layer (FT2232) that is long enough to finish execution on
473 * the core but still shorter than any manually inducible delays.
476 tap_state_t arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay
[] =
478 TAP_DREXIT2
, TAP_DRUPDATE
, TAP_IDLE
, TAP_IDLE
, TAP_IDLE
, TAP_DRSELECT
, TAP_DRCAPTURE
, TAP_DRSHIFT
483 /** Execute one instruction via ITR repeatedly while
484 * passing data to the core via DTR on each execution.
486 * No Ready check during transmission.
488 * The executed instruction \em must read data from DTR.
490 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
492 * \param arm11 Target state variable.
493 * \param opcode ARM opcode
494 * \param data Pointer to the data words to be passed to the core
495 * \param count Number of data words and instruction repetitions
498 void arm11_run_instr_data_to_core_noack(arm11_common_t
* arm11
, u32 opcode
, u32
* data
, size_t count
)
500 arm11_add_IR(arm11
, ARM11_ITRSEL
, ARM11_TAP_DEFAULT
);
502 arm11_add_debug_INST(arm11
, opcode
, NULL
, TAP_DRPAUSE
);
504 arm11_add_IR(arm11
, ARM11_EXTEST
, ARM11_TAP_DEFAULT
);
506 scan_field_t chain5_fields
[3];
508 arm11_setup_field(arm11
, 32, NULL
/*&Data*/, NULL
, chain5_fields
+ 0);
509 arm11_setup_field(arm11
, 1, NULL
, NULL
/*&Ready*/, chain5_fields
+ 1);
510 arm11_setup_field(arm11
, 1, NULL
, NULL
, chain5_fields
+ 2);
512 u8 Readies
[count
+ 1];
513 u8
* ReadyPos
= Readies
;
517 chain5_fields
[0].out_value
= (void *)(data
++);
518 chain5_fields
[1].in_value
= ReadyPos
++;
522 jtag_add_dr_scan(asizeof(chain5_fields
), chain5_fields
, TAP_DRPAUSE
);
523 jtag_add_pathmove(asizeof(arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay
),
524 arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay
);
528 jtag_add_dr_scan(asizeof(chain5_fields
), chain5_fields
, TAP_IDLE
);
532 arm11_add_IR(arm11
, ARM11_INTEST
, ARM11_TAP_DEFAULT
);
534 chain5_fields
[0].out_value
= 0;
535 chain5_fields
[1].in_value
= ReadyPos
++;
537 arm11_add_dr_scan_vc(asizeof(chain5_fields
), chain5_fields
, TAP_DRPAUSE
);
539 jtag_execute_queue();
541 size_t error_count
= 0;
544 for (i
= 0; i
< asizeof(Readies
); i
++)
553 LOG_ERROR("Transfer errors " ZU
, error_count
);
557 /** Execute an instruction via ITR while handing data into the core via DTR.
559 * The executed instruction \em must read data from DTR.
561 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
563 * \param arm11 Target state variable.
564 * \param opcode ARM opcode
565 * \param data Data word to be passed to the core via DTR
568 void arm11_run_instr_data_to_core1(arm11_common_t
* arm11
, u32 opcode
, u32 data
)
570 arm11_run_instr_data_to_core(arm11
, opcode
, &data
, 1);
574 /** Execute one instruction via ITR repeatedly while
575 * reading data from the core via DTR on each execution.
577 * The executed instruction \em must write data to DTR.
579 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
581 * \param arm11 Target state variable.
582 * \param opcode ARM opcode
583 * \param data Pointer to an array that receives the data words from the core
584 * \param count Number of data words and instruction repetitions
587 void arm11_run_instr_data_from_core(arm11_common_t
* arm11
, u32 opcode
, u32
* data
, size_t count
)
589 arm11_add_IR(arm11
, ARM11_ITRSEL
, ARM11_TAP_DEFAULT
);
591 arm11_add_debug_INST(arm11
, opcode
, NULL
, TAP_IDLE
);
593 arm11_add_IR(arm11
, ARM11_INTEST
, ARM11_TAP_DEFAULT
);
595 scan_field_t chain5_fields
[3];
601 arm11_setup_field(arm11
, 32, NULL
, &Data
, chain5_fields
+ 0);
602 arm11_setup_field(arm11
, 1, NULL
, &Ready
, chain5_fields
+ 1);
603 arm11_setup_field(arm11
, 1, NULL
, &nRetry
, chain5_fields
+ 2);
609 arm11_add_dr_scan_vc(asizeof(chain5_fields
), chain5_fields
, count
? TAP_IDLE
: TAP_DRPAUSE
);
610 jtag_execute_queue();
612 JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d", Data
, Ready
, nRetry
);
620 /** Execute one instruction via ITR
621 * then load r0 into DTR and read DTR from core.
623 * The first executed instruction (\p opcode) should write data to r0.
625 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
627 * \param arm11 Target state variable.
628 * \param opcode ARM opcode to write r0 with the value of interest
629 * \param data Pointer to a data word that receives the value from r0 after \p opcode was executed.
632 void arm11_run_instr_data_from_core_via_r0(arm11_common_t
* arm11
, u32 opcode
, u32
* data
)
634 arm11_run_instr_no_data1(arm11
, opcode
);
636 /* MCR p14,0,R0,c0,c5,0 (move r0 -> wDTR -> local var) */
637 arm11_run_instr_data_from_core(arm11
, 0xEE000E15, data
, 1);
640 /** Load data into core via DTR then move it to r0 then
641 * execute one instruction via ITR
643 * The final executed instruction (\p opcode) should read data from r0.
645 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
647 * \param arm11 Target state variable.
648 * \param opcode ARM opcode to read r0 act upon it
649 * \param data Data word that will be written to r0 before \p opcode is executed
652 void arm11_run_instr_data_to_core_via_r0(arm11_common_t
* arm11
, u32 opcode
, u32 data
)
654 /* MRC p14,0,r0,c0,c5,0 */
655 arm11_run_instr_data_to_core1(arm11
, 0xEE100E15, data
);
657 arm11_run_instr_no_data1(arm11
, opcode
);
660 /** Apply reads and writes to scan chain 7
662 * \see arm11_sc7_action_t
664 * \param arm11 Target state variable.
665 * \param actions A list of read and/or write instructions
666 * \param count Number of instructions in the list.
669 void arm11_sc7_run(arm11_common_t
* arm11
, arm11_sc7_action_t
* actions
, size_t count
)
671 arm11_add_debug_SCAN_N(arm11
, 0x07, ARM11_TAP_DEFAULT
);
673 arm11_add_IR(arm11
, ARM11_EXTEST
, ARM11_TAP_DEFAULT
);
675 scan_field_t chain7_fields
[3];
684 arm11_setup_field(arm11
, 1, &nRW
, &Ready
, chain7_fields
+ 0);
685 arm11_setup_field(arm11
, 32, &DataOut
, &DataIn
, chain7_fields
+ 1);
686 arm11_setup_field(arm11
, 7, &AddressOut
, &AddressIn
, chain7_fields
+ 2);
689 for (i
= 0; i
< count
+ 1; i
++)
693 nRW
= actions
[i
].write
? 1 : 0;
694 DataOut
= actions
[i
].value
;
695 AddressOut
= actions
[i
].address
;
706 JTAG_DEBUG("SC7 <= Address %02x Data %08x nRW %d", AddressOut
, DataOut
, nRW
);
708 arm11_add_dr_scan_vc(asizeof(chain7_fields
), chain7_fields
, TAP_DRPAUSE
);
709 jtag_execute_queue();
711 JTAG_DEBUG("SC7 => Address %02x Data %08x Ready %d", AddressIn
, DataIn
, Ready
);
713 while (!Ready
); /* 'nRW' is 'Ready' on read out */
717 if (actions
[i
- 1].address
!= AddressIn
)
719 LOG_WARNING("Scan chain 7 shifted out unexpected address");
722 if (!actions
[i
- 1].write
)
724 actions
[i
- 1].value
= DataIn
;
728 if (actions
[i
- 1].value
!= DataIn
)
730 LOG_WARNING("Scan chain 7 shifted out unexpected data");
737 for (i
= 0; i
< count
; i
++)
739 JTAG_DEBUG("SC7 %02d: %02x %s %08x", i
, actions
[i
].address
, actions
[i
].write
? "<=" : "=>", actions
[i
].value
);
743 /** Clear VCR and all breakpoints and watchpoints via scan chain 7
745 * \param arm11 Target state variable.
748 void arm11_sc7_clear_vbw(arm11_common_t
* arm11
)
750 arm11_sc7_action_t clear_bw
[arm11
->brp
+ arm11
->wrp
+ 1];
751 arm11_sc7_action_t
* pos
= clear_bw
;
754 for (i
= 0; i
< asizeof(clear_bw
); i
++)
756 clear_bw
[i
].write
= true;
757 clear_bw
[i
].value
= 0;
761 for (i
= 0; i
< arm11
->brp
; i
++)
762 (pos
++)->address
= ARM11_SC7_BCR0
+ i
;
766 for (i
= 0; i
< arm11
->wrp
; i
++)
767 (pos
++)->address
= ARM11_SC7_WCR0
+ i
;
770 (pos
++)->address
= ARM11_SC7_VCR
;
772 arm11_sc7_run(arm11
, clear_bw
, asizeof(clear_bw
));
775 /** Write VCR register
777 * \param arm11 Target state variable.
778 * \param value Value to be written
780 void arm11_sc7_set_vcr(arm11_common_t
* arm11
, u32 value
)
782 arm11_sc7_action_t set_vcr
;
784 set_vcr
.write
= true;
785 set_vcr
.address
= ARM11_SC7_VCR
;
786 set_vcr
.value
= value
;
789 arm11_sc7_run(arm11
, &set_vcr
, 1);
794 /** Read word from address
796 * \param arm11 Target state variable.
797 * \param address Memory address to be read
798 * \param result Pointer where to store result
801 void arm11_read_memory_word(arm11_common_t
* arm11
, u32 address
, u32
* result
)
803 arm11_run_instr_data_prepare(arm11
);
805 /* MRC p14,0,r0,c0,c5,0 (r0 = address) */
806 arm11_run_instr_data_to_core1(arm11
, 0xee100e15, address
);
808 /* LDC p14,c5,[R0],#4 (DTR = [r0]) */
809 arm11_run_instr_data_from_core(arm11
, 0xecb05e01, result
, 1);
811 arm11_run_instr_data_finish(arm11
);
Linking to existing account procedure
If you already have an account and want to add another login method
you
MUST first sign in with your existing account and
then change URL to read
https://review.openocd.org/login/?link
to get to this page again but this time it'll work for linking. Thank you.
SSH host keys fingerprints
1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=.. |
|+o.. . |
|*.o . . |
|+B . . . |
|Bo. = o S |
|Oo.+ + = |
|oB=.* = . o |
| =+=.+ + E |
|. .=o . o |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)