src/target/arm11.h

   1 /***************************************************************************
   2  *   Copyright (C) 2008 digenius technology GmbH.                          *
   3  *                                                                         *
   4  *   This program is free software; you can redistribute it and/or modify  *
   5  *   it under the terms of the GNU General Public License as published by  *
   6  *   the Free Software Foundation; either version 2 of the License, or     *
   7  *   (at your option) any later version.                                   *
   8  *                                                                         *
   9  *   This program is distributed in the hope that it will be useful,       *
  10  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  11  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  12  *   GNU General Public License for more details.                          *
  13  *                                                                         *
  14  *   You should have received a copy of the GNU General Public License     *
  15  *   along with this program; if not, write to the                         *
  16  *   Free Software Foundation, Inc.,                                       *
  17  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  18  ***************************************************************************/
  19
  20 #ifndef ARM11_H
  21 #define ARM11_H
  22
  23 #include "target.h"
  24 #include "register.h"
  25 #include "embeddedice.h"
  26 #include "arm_jtag.h"
  27 #include <stdbool.h>
  28
  29
  30 #define asizeof(x)      (sizeof(x) / sizeof((x)[0]))
  31
  32 #define NEW(type, variable, items)                      \
  33     type * variable = calloc(1, sizeof(type) * items)
  34
  35
  36 /* Don't know exactly when %zu was added to glibc (CVS says in 1998).
  37    Assume for now that its between GCC versions 3.x.x and 4.x.x .
  38    MinGW's GCC 3.4.5 comes with a glibc that doesn't support it.
  39 */
  40
  41 #if __GNUC__ > 3
  42 #define ZU              "%zu"
  43 #else
  44 #define ZU              "%u"
  45 #endif
  46
  47
  48 #define ARM11_REGCACHE_MODEREGS         0
  49 #define ARM11_REGCACHE_FREGS            0
  50
  51 #define ARM11_REGCACHE_COUNT            (20 +                                   \
  52                                          23 * ARM11_REGCACHE_MODEREGS +         \
  53                                           9 * ARM11_REGCACHE_FREGS)
  54
  55
  56 typedef struct arm11_register_history_s
  57 {
  58     u32     value;
  59     u8      valid;
  60 }arm11_register_history_t;
  61
  62 enum arm11_debug_version
  63 {
  64     ARM11_DEBUG_V6      = 0x01,
  65     ARM11_DEBUG_V61     = 0x02,
  66     ARM11_DEBUG_V7      = 0x03,
  67     ARM11_DEBUG_V7_CP14 = 0x04,
  68 };
  69
  70 typedef struct arm11_common_s
  71 {
  72     target_t *  target;
  73
  74     arm_jtag_t  jtag_info;
  75
  76     /** \name Processor type detection */
  77     /*@{*/
  78
  79     u32         device_id;          /**< IDCODE readout                         */
  80     u32         didr;               /**< DIDR readout (debug capabilities)      */
  81     u8          implementor;        /**< DIDR Implementor readout               */
  82
  83     size_t      brp;                /**< Number of Breakpoint Register Pairs from DIDR  */
  84     size_t      wrp;                /**< Number of Watchpoint Register Pairs from DIDR  */
  85
  86     enum arm11_debug_version
  87                 debug_version;      /**< ARM debug architecture from DIDR       */
  88     /*@}*/
  89
  90
  91     u32         last_dscr;          /**< Last retrieved DSCR value;
  92                                      *   Can be used to detect changes          */
  93
  94     bool        trst_active;
  95     bool        halt_requested;
  96     bool        simulate_reset_on_next_halt;
  97
  98     /** \name Shadow registers to save processor state */
  99     /*@{*/
 100
 101     reg_t *     reg_list;                               /**< target register list */
 102     u32         reg_values[ARM11_REGCACHE_COUNT];       /**< data for registers */
 103
 104     /*@}*/
 105
 106     arm11_register_history_t
 107                 reg_history[ARM11_REGCACHE_COUNT];      /**< register state before last resume */
 108
 109
 110     size_t      free_brps;                              /**< keep track of breakpoints allocated by arm11_add_breakpoint() */
 111     size_t      free_wrps;                              /**< keep track of breakpoints allocated by arm11_add_watchpoint() */
 112
 113 } arm11_common_t;
 114
 115
 116 /**
 117  * ARM11 DBGTAP instructions
 118  *
 119  * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0301f/I1006229.html
 120  */
 121 enum arm11_instructions
 122 {
 123     ARM11_EXTEST    = 0x00,
 124     ARM11_SCAN_N    = 0x02,
 125     ARM11_RESTART   = 0x04,
 126     ARM11_HALT      = 0x08,
 127     ARM11_INTEST    = 0x0C,
 128     ARM11_ITRSEL    = 0x1D,
 129     ARM11_IDCODE    = 0x1E,
 130     ARM11_BYPASS    = 0x1F,
 131 };
 132
 133 enum arm11_dscr
 134 {
 135     ARM11_DSCR_CORE_HALTED                              = 1 << 0,
 136     ARM11_DSCR_CORE_RESTARTED                           = 1 << 1,
 137
 138     ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_MASK               = 0x0F << 2,
 139     ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_HALT               = 0x00 << 2,
 140     ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BREAKPOINT         = 0x01 << 2,
 141     ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_WATCHPOINT         = 0x02 << 2,
 142     ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BKPT_INSTRUCTION   = 0x03 << 2,
 143     ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_EDBGRQ             = 0x04 << 2,
 144     ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_VECTOR_CATCH       = 0x05 << 2,
 145
 146     ARM11_DSCR_STICKY_PRECISE_DATA_ABORT                = 1 << 6,
 147     ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT              = 1 << 7,
 148     ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE           = 1 << 13,
 149     ARM11_DSCR_MODE_SELECT                              = 1 << 14,
 150     ARM11_DSCR_WDTR_FULL                                = 1 << 29,
 151     ARM11_DSCR_RDTR_FULL                                = 1 << 30,
 152 };
 153
 154 enum arm11_cpsr
 155 {
 156     ARM11_CPSR_T                                = 1 << 5,
 157     ARM11_CPSR_J                                = 1 << 24,
 158 };
 159
 160 enum arm11_sc7
 161 {
 162     ARM11_SC7_NULL                              = 0,
 163     ARM11_SC7_VCR                               = 7,
 164     ARM11_SC7_PC                                = 8,
 165     ARM11_SC7_BVR0                              = 64,
 166     ARM11_SC7_BCR0                              = 80,
 167     ARM11_SC7_WVR0                              = 96,
 168     ARM11_SC7_WCR0                              = 112,
 169 };
 170
 171
 172
 173 typedef struct arm11_reg_state_s
 174 {
 175     u32                         def_index;
 176     target_t *                  target;
 177 } arm11_reg_state_t;
 178
 179
 180
 181
 182 /* poll current target status */
 183 int arm11_poll(struct target_s *target);
 184 /* architecture specific status reply */
 185 int arm11_arch_state(struct target_s *target);
 186
 187 /* target request support */
 188 int arm11_target_request_data(struct target_s *target, u32 size, u8 *buffer);
 189
 190 /* target execution control */
 191 int arm11_halt(struct target_s *target);
 192 int arm11_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution);
 193 int arm11_step(struct target_s *target, int current, u32 address, int handle_breakpoints);
 194
 195 /* target reset control */
 196 int arm11_assert_reset(struct target_s *target);
 197 int arm11_deassert_reset(struct target_s *target);
 198 int arm11_soft_reset_halt(struct target_s *target);
 199 int arm11_prepare_reset_halt(struct target_s *target);
 200
 201 /* target register access for gdb */
 202 int arm11_get_gdb_reg_list(struct target_s *target, struct reg_s **reg_list[], int *reg_list_size);
 203
 204 /* target memory access
 205 * size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
 206 * count: number of items of <size>
 207 */
 208 int arm11_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
 209 int arm11_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
 210
 211 /* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
 212 int arm11_bulk_write_memory(struct target_s *target, u32 address, u32 count, u8 *buffer);
 213
 214 int arm11_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum);
 215
 216 /* target break-/watchpoint control
 217 * rw: 0 = write, 1 = read, 2 = access
 218 */
 219 int arm11_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
 220 int arm11_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
 221 int arm11_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint);
 222 int arm11_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint);
 223
 224 /* target algorithm support */
 225 int arm11_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_param, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info);
 226
 227 int arm11_register_commands(struct command_context_s *cmd_ctx);
 228 int arm11_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target);
 229 int arm11_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
 230 int arm11_quit(void);
 231
 232
 233 /* helpers */
 234 void arm11_build_reg_cache(target_t *target);
 235
 236 void arm11_record_register_history(arm11_common_t * arm11);
 237 void arm11_dump_reg_changes(arm11_common_t * arm11);
 238
 239
 240 /* internals */
 241
 242 void arm11_setup_field          (arm11_common_t * arm11, int num_bits, void * in_data, void * out_data, scan_field_t * field);
 243 void arm11_add_IR               (arm11_common_t * arm11, u8 instr, enum tap_state state);
 244 void arm11_add_debug_SCAN_N     (arm11_common_t * arm11, u8 chain, enum tap_state state);
 245 void arm11_add_debug_INST       (arm11_common_t * arm11, u32 inst, u8 * flag, enum tap_state state);
 246 u32  arm11_read_DSCR            (arm11_common_t * arm11);
 247 void arm11_write_DSCR           (arm11_common_t * arm11, u32 dscr);
 248
 249 enum target_debug_reason arm11_get_DSCR_debug_reason(u32 dscr);
 250
 251 void arm11_run_instr_data_prepare               (arm11_common_t * arm11);
 252 void arm11_run_instr_data_finish                (arm11_common_t * arm11);
 253 void arm11_run_instr_no_data                    (arm11_common_t * arm11, u32 * opcode, size_t count);
 254 void arm11_run_instr_no_data1                   (arm11_common_t * arm11, u32 opcode);
 255 void arm11_run_instr_data_to_core               (arm11_common_t * arm11, u32 opcode, u32 * data, size_t count);
 256 void arm11_run_instr_data_to_core_noack         (arm11_common_t * arm11, u32 opcode, u32 * data, size_t count);
 257 void arm11_run_instr_data_to_core1              (arm11_common_t * arm11, u32 opcode, u32 data);
 258 void arm11_run_instr_data_from_core             (arm11_common_t * arm11, u32 opcode, u32 * data, size_t count);
 259 void arm11_run_instr_data_from_core_via_r0      (arm11_common_t * arm11, u32 opcode, u32 * data);
 260 void arm11_run_instr_data_to_core_via_r0        (arm11_common_t * arm11, u32 opcode, u32 data);
 261
 262 int arm11_add_dr_scan_vc(int num_fields, scan_field_t *fields, enum tap_state state);
 263 int arm11_add_ir_scan_vc(int num_fields, scan_field_t *fields, enum tap_state state);
 264
 265
 266 /** Used to make a list of read/write commands for scan chain 7
 267  *
 268  *  Use with arm11_sc7_run()
 269  */
 270 typedef struct arm11_sc7_action_s
 271 {
 272     bool    write;                              /**< Access mode: true for write, false for read.       */
 273     u8      address;                            /**< Register address mode. Use enum #arm11_sc7         */
 274     u32     value;                              /**< If write then set this to value to be written.
 275                                                      In read mode this receives the read value when the
 276                                                      function returns.                                  */
 277 } arm11_sc7_action_t;
 278
 279 void arm11_sc7_run(arm11_common_t * arm11, arm11_sc7_action_t * actions, size_t count);
 280
 281 /* Mid-level helper functions */
 282 void arm11_sc7_clear_vbw(arm11_common_t * arm11);
 283 void arm11_sc7_set_vcr(arm11_common_t * arm11, u32 value);
 284
 285 void arm11_read_memory_word(arm11_common_t * arm11, u32 address, u32 * result);
 286
 287
 288
 289 #endif /* ARM11_H */