9edadee1d911681f4f7b80c5305e0223b32c321f
[openocd.git] / src / target / arm11.h
1 /***************************************************************************
2 * Copyright (C) 2008 digenius technology GmbH. *
3 * Michael Bruck *
4 * *
5 * Copyright (C) 2008 Georg Acher <acher@in.tum.de> *
6 * *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General Public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
11 * *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
15 * GNU General Public License for more details. *
16 * *
17 * You should have received a copy of the GNU General Public License *
18 * along with this program; if not, write to the *
19 * Free Software Foundation, Inc., *
20 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
21 ***************************************************************************/
22
23 #ifndef ARM11_H
24 #define ARM11_H
25
26 #include "arm.h"
27 #include "arm_dpm.h"
28
29 #define ARM11_TAP_DEFAULT TAP_INVALID
30
31 #define CHECK_RETVAL(action) \
32 do { \
33 int __retval = (action); \
34 if (__retval != ERROR_OK) { \
35 LOG_DEBUG("error while calling \"%s\"", \
36 # action ); \
37 return __retval; \
38 } \
39 } while (0)
40
41 /* bits from ARMv7 DIDR */
42 enum arm11_debug_version
43 {
44 ARM11_DEBUG_V6 = 0x01,
45 ARM11_DEBUG_V61 = 0x02,
46 ARM11_DEBUG_V7 = 0x03,
47 ARM11_DEBUG_V7_CP14 = 0x04,
48 };
49
50 struct arm11_common
51 {
52 struct arm arm;
53
54 /** Debug module state. */
55 struct arm_dpm dpm;
56 struct arm11_sc7_action *bpwp_actions;
57 unsigned bpwp_n;
58
59 size_t brp; /**< Number of Breakpoint Register Pairs from DIDR */
60 size_t free_brps; /**< Number of breakpoints allocated */
61
62 uint32_t dscr; /**< Last retrieved DSCR value. */
63
64 uint32_t saved_rdtr;
65 uint32_t saved_wdtr;
66
67 bool is_rdtr_saved;
68 bool is_wdtr_saved;
69
70 bool simulate_reset_on_next_halt; /**< Perform cleanups of the ARM state on next halt */
71
72 /* Per-core configurable options.
73 * NOTE that several of these boolean options should not exist
74 * once the relevant code is known to work correctly.
75 */
76 bool memwrite_burst;
77 bool memwrite_error_fatal;
78 bool step_irq_enable;
79 bool hardware_step;
80
81 /** Configured Vector Catch Register settings. */
82 uint32_t vcr;
83
84 struct arm_jtag jtag_info;
85 };
86
87 static inline struct arm11_common *target_to_arm11(struct target *target)
88 {
89 return container_of(target->arch_info, struct arm11_common,
90 arm);
91 }
92
93 /**
94 * ARM11 DBGTAP instructions
95 *
96 * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0301f/I1006229.html
97 */
98 enum arm11_instructions
99 {
100 ARM11_EXTEST = 0x00,
101 ARM11_SCAN_N = 0x02,
102 ARM11_RESTART = 0x04,
103 ARM11_HALT = 0x08,
104 ARM11_INTEST = 0x0C,
105 ARM11_ITRSEL = 0x1D,
106 ARM11_IDCODE = 0x1E,
107 ARM11_BYPASS = 0x1F,
108 };
109
110 enum arm11_sc7
111 {
112 ARM11_SC7_NULL = 0,
113 ARM11_SC7_VCR = 7,
114 ARM11_SC7_PC = 8,
115 ARM11_SC7_BVR0 = 64,
116 ARM11_SC7_BCR0 = 80,
117 ARM11_SC7_WVR0 = 96,
118 ARM11_SC7_WCR0 = 112,
119 };
120
121 #endif /* ARM11_H */