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More MinGW C99 printf compliance
[openocd.git] / src / target / arm11.h
1 /***************************************************************************
2 * Copyright (C) 2008 digenius technology GmbH. *
3 * Michael Bruck *
4 * *
5 * Copyright (C) 2008 Georg Acher <acher@in.tum.de> *
6 * *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General Public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
11 * *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
15 * GNU General Public License for more details. *
16 * *
17 * You should have received a copy of the GNU General Public License *
18 * along with this program; if not, write to the *
19 * Free Software Foundation, Inc., *
20 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
21 ***************************************************************************/
22
23 #ifndef ARM11_H
24 #define ARM11_H
25
26 #include "target.h"
27 #include "register.h"
28 #include "jtag.h"
29
30 #define asizeof(x) (sizeof(x) / sizeof((x)[0]))
31
32 #define NEW(type, variable, items) \
33 type * variable = calloc(1, sizeof(type) * items)
34
35 /* For MinGW use 'I' prefix to print size_t (instead of 'z') */
36 /* Except if __USE_MINGW_ANSI_STDIO is defined with MinGW */
37
38 #if (!defined(__MSVCRT__) || defined(__USE_MINGW_ANSI_STDIO))
39 #define ZU "%zu"
40 #else
41 #define ZU "%Iu"
42 #endif
43
44 #define ARM11_REGCACHE_MODEREGS 0
45 #define ARM11_REGCACHE_FREGS 0
46
47 #define ARM11_REGCACHE_COUNT (20 + \
48 23 * ARM11_REGCACHE_MODEREGS + \
49 9 * ARM11_REGCACHE_FREGS)
50
51 #define ARM11_TAP_DEFAULT TAP_INVALID
52
53
54 #define CHECK_RETVAL(action) \
55 do { \
56 int __retval = (action); \
57 \
58 if (__retval != ERROR_OK) \
59 { \
60 LOG_DEBUG("error while calling \"" # action "\""); \
61 return __retval; \
62 } \
63 \
64 } while (0)
65
66
67 typedef struct arm11_register_history_s
68 {
69 uint32_t value;
70 uint8_t valid;
71 }arm11_register_history_t;
72
73 enum arm11_debug_version
74 {
75 ARM11_DEBUG_V6 = 0x01,
76 ARM11_DEBUG_V61 = 0x02,
77 ARM11_DEBUG_V7 = 0x03,
78 ARM11_DEBUG_V7_CP14 = 0x04,
79 };
80
81 typedef struct arm11_common_s
82 {
83 target_t * target; /**< Reference back to the owner */
84
85 /** \name Processor type detection */
86 /*@{*/
87
88 uint32_t device_id; /**< IDCODE readout */
89 uint32_t didr; /**< DIDR readout (debug capabilities) */
90 uint8_t implementor; /**< DIDR Implementor readout */
91
92 size_t brp; /**< Number of Breakpoint Register Pairs from DIDR */
93 size_t wrp; /**< Number of Watchpoint Register Pairs from DIDR */
94
95 enum arm11_debug_version
96 debug_version; /**< ARM debug architecture from DIDR */
97 /*@}*/
98
99 uint32_t last_dscr; /**< Last retrieved DSCR value;
100 Use only for debug message generation */
101
102 bool simulate_reset_on_next_halt; /**< Perform cleanups of the ARM state on next halt */
103
104 /** \name Shadow registers to save processor state */
105 /*@{*/
106
107 reg_t * reg_list; /**< target register list */
108 uint32_t reg_values[ARM11_REGCACHE_COUNT]; /**< data for registers */
109
110 /*@}*/
111
112 arm11_register_history_t
113 reg_history[ARM11_REGCACHE_COUNT]; /**< register state before last resume */
114
115 size_t free_brps; /**< keep track of breakpoints allocated by arm11_add_breakpoint() */
116 size_t free_wrps; /**< keep track of breakpoints allocated by arm11_add_watchpoint() */
117
118 // GA
119 reg_cache_t *core_cache;
120 } arm11_common_t;
121
122
123 /**
124 * ARM11 DBGTAP instructions
125 *
126 * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0301f/I1006229.html
127 */
128 enum arm11_instructions
129 {
130 ARM11_EXTEST = 0x00,
131 ARM11_SCAN_N = 0x02,
132 ARM11_RESTART = 0x04,
133 ARM11_HALT = 0x08,
134 ARM11_INTEST = 0x0C,
135 ARM11_ITRSEL = 0x1D,
136 ARM11_IDCODE = 0x1E,
137 ARM11_BYPASS = 0x1F,
138 };
139
140 enum arm11_dscr
141 {
142 ARM11_DSCR_CORE_HALTED = 1 << 0,
143 ARM11_DSCR_CORE_RESTARTED = 1 << 1,
144
145 ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_MASK = 0x0F << 2,
146 ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_HALT = 0x00 << 2,
147 ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BREAKPOINT = 0x01 << 2,
148 ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_WATCHPOINT = 0x02 << 2,
149 ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BKPT_INSTRUCTION = 0x03 << 2,
150 ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_EDBGRQ = 0x04 << 2,
151 ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_VECTOR_CATCH = 0x05 << 2,
152
153 ARM11_DSCR_STICKY_PRECISE_DATA_ABORT = 1 << 6,
154 ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT = 1 << 7,
155 ARM11_DSCR_INTERRUPTS_DISABLE = 1 << 11,
156 ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE = 1 << 13,
157 ARM11_DSCR_MODE_SELECT = 1 << 14,
158 ARM11_DSCR_WDTR_FULL = 1 << 29,
159 ARM11_DSCR_RDTR_FULL = 1 << 30,
160 };
161
162 enum arm11_cpsr
163 {
164 ARM11_CPSR_T = 1 << 5,
165 ARM11_CPSR_J = 1 << 24,
166 };
167
168 enum arm11_sc7
169 {
170 ARM11_SC7_NULL = 0,
171 ARM11_SC7_VCR = 7,
172 ARM11_SC7_PC = 8,
173 ARM11_SC7_BVR0 = 64,
174 ARM11_SC7_BCR0 = 80,
175 ARM11_SC7_WVR0 = 96,
176 ARM11_SC7_WCR0 = 112,
177 };
178
179 typedef struct arm11_reg_state_s
180 {
181 uint32_t def_index;
182 target_t * target;
183 } arm11_reg_state_t;
184
185 /* poll current target status */
186 int arm11_poll(struct target_s *target);
187 /* architecture specific status reply */
188 int arm11_arch_state(struct target_s *target);
189
190 /* target request support */
191 int arm11_target_request_data(struct target_s *target, uint32_t size, uint8_t *buffer);
192
193 /* target execution control */
194 int arm11_halt(struct target_s *target);
195 int arm11_resume(struct target_s *target, int current, uint32_t address, int handle_breakpoints, int debug_execution);
196 int arm11_step(struct target_s *target, int current, uint32_t address, int handle_breakpoints);
197 int arm11_examine(struct target_s *target);
198
199 /* target reset control */
200 int arm11_assert_reset(struct target_s *target);
201 int arm11_deassert_reset(struct target_s *target);
202 int arm11_soft_reset_halt(struct target_s *target);
203
204 /* target register access for gdb */
205 int arm11_get_gdb_reg_list(struct target_s *target, struct reg_s **reg_list[], int *reg_list_size);
206
207 /* target memory access
208 * size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
209 * count: number of items of <size>
210 */
211 int arm11_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
212 int arm11_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
213
214 /* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
215 int arm11_bulk_write_memory(struct target_s *target, uint32_t address, uint32_t count, uint8_t *buffer);
216
217 int arm11_checksum_memory(struct target_s *target, uint32_t address, uint32_t count, uint32_t* checksum);
218
219 /* target break-/watchpoint control
220 * rw: 0 = write, 1 = read, 2 = access
221 */
222 int arm11_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
223 int arm11_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
224 int arm11_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint);
225 int arm11_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint);
226
227 /* target algorithm support */
228 int arm11_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_param, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info);
229
230 int arm11_register_commands(struct command_context_s *cmd_ctx);
231 int arm11_target_create(struct target_s *target, Jim_Interp *interp);
232 int arm11_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
233 int arm11_quit(void);
234
235 /* helpers */
236 int arm11_build_reg_cache(target_t *target);
237 int arm11_set_reg(reg_t *reg, uint8_t *buf);
238 int arm11_get_reg(reg_t *reg);
239
240 void arm11_record_register_history(arm11_common_t * arm11);
241 void arm11_dump_reg_changes(arm11_common_t * arm11);
242
243 /* internals */
244
245 void arm11_setup_field (arm11_common_t * arm11, int num_bits, void * in_data, void * out_data, scan_field_t * field);
246 void arm11_add_IR (arm11_common_t * arm11, uint8_t instr, tap_state_t state);
247 int arm11_add_debug_SCAN_N (arm11_common_t * arm11, uint8_t chain, tap_state_t state);
248 void arm11_add_debug_INST (arm11_common_t * arm11, uint32_t inst, uint8_t * flag, tap_state_t state);
249 int arm11_read_DSCR (arm11_common_t * arm11, uint32_t *dscr);
250 int arm11_write_DSCR (arm11_common_t * arm11, uint32_t dscr);
251
252 enum target_debug_reason arm11_get_DSCR_debug_reason(uint32_t dscr);
253
254 int arm11_run_instr_data_prepare (arm11_common_t * arm11);
255 int arm11_run_instr_data_finish (arm11_common_t * arm11);
256 int arm11_run_instr_no_data (arm11_common_t * arm11, uint32_t * opcode, size_t count);
257 int arm11_run_instr_no_data1 (arm11_common_t * arm11, uint32_t opcode);
258 int arm11_run_instr_data_to_core (arm11_common_t * arm11, uint32_t opcode, uint32_t * data, size_t count);
259 int arm11_run_instr_data_to_core_noack (arm11_common_t * arm11, uint32_t opcode, uint32_t * data, size_t count);
260 int arm11_run_instr_data_to_core1 (arm11_common_t * arm11, uint32_t opcode, uint32_t data);
261 int arm11_run_instr_data_from_core (arm11_common_t * arm11, uint32_t opcode, uint32_t * data, size_t count);
262 int arm11_run_instr_data_from_core_via_r0 (arm11_common_t * arm11, uint32_t opcode, uint32_t * data);
263 int arm11_run_instr_data_to_core_via_r0 (arm11_common_t * arm11, uint32_t opcode, uint32_t data);
264
265 int arm11_add_dr_scan_vc(int num_fields, scan_field_t *fields, tap_state_t state);
266 int arm11_add_ir_scan_vc(int num_fields, scan_field_t *fields, tap_state_t state);
267
268 /** Used to make a list of read/write commands for scan chain 7
269 *
270 * Use with arm11_sc7_run()
271 */
272 typedef struct arm11_sc7_action_s
273 {
274 bool write; /**< Access mode: true for write, false for read. */
275 uint8_t address; /**< Register address mode. Use enum #arm11_sc7 */
276 uint32_t value; /**< If write then set this to value to be written.
277 In read mode this receives the read value when the
278 function returns. */
279 } arm11_sc7_action_t;
280
281 int arm11_sc7_run(arm11_common_t * arm11, arm11_sc7_action_t * actions, size_t count);
282
283 /* Mid-level helper functions */
284 void arm11_sc7_clear_vbw(arm11_common_t * arm11);
285 void arm11_sc7_set_vcr(arm11_common_t * arm11, uint32_t value);
286
287 int arm11_read_memory_word(arm11_common_t * arm11, uint32_t address, uint32_t * result);
288
289 #endif /* ARM11_H */
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