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Audit and eliminate redundant #include directives in arm target files.
[openocd.git] / src / target / arm11.h
1 /***************************************************************************
2 * Copyright (C) 2008 digenius technology GmbH. *
3 * *
4 * Copyright (C) 2008 Georg Acher <acher@in.tum.de> *
5 * *
6 * This program is free software; you can redistribute it and/or modify *
7 * it under the terms of the GNU General Public License as published by *
8 * the Free Software Foundation; either version 2 of the License, or *
9 * (at your option) any later version. *
10 * *
11 * This program is distributed in the hope that it will be useful, *
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
14 * GNU General Public License for more details. *
15 * *
16 * You should have received a copy of the GNU General Public License *
17 * along with this program; if not, write to the *
18 * Free Software Foundation, Inc., *
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
20 ***************************************************************************/
21
22 #ifndef ARM11_H
23 #define ARM11_H
24
25 #include "embeddedice.h"
26
27 #define asizeof(x) (sizeof(x) / sizeof((x)[0]))
28
29 #define NEW(type, variable, items) \
30 type * variable = calloc(1, sizeof(type) * items)
31
32 /* For MinGW use 'I' prefix to print size_t (instead of 'z') */
33
34 #ifndef __MSVCRT__
35 #define ZU "%zu"
36 #else
37 #define ZU "%Iu"
38 #endif
39
40 #define ARM11_REGCACHE_MODEREGS 0
41 #define ARM11_REGCACHE_FREGS 0
42
43 #define ARM11_REGCACHE_COUNT (20 + \
44 23 * ARM11_REGCACHE_MODEREGS + \
45 9 * ARM11_REGCACHE_FREGS)
46
47 #define ARM11_TAP_DEFAULT TAP_INVALID
48
49
50 #define CHECK_RETVAL(action) \
51 do { \
52 int __retval = (action); \
53 \
54 if (__retval != ERROR_OK) \
55 { \
56 LOG_DEBUG("error while calling \"" # action "\""); \
57 return __retval; \
58 } \
59 \
60 } while (0)
61
62
63 typedef struct arm11_register_history_s
64 {
65 u32 value;
66 u8 valid;
67 }arm11_register_history_t;
68
69 enum arm11_debug_version
70 {
71 ARM11_DEBUG_V6 = 0x01,
72 ARM11_DEBUG_V61 = 0x02,
73 ARM11_DEBUG_V7 = 0x03,
74 ARM11_DEBUG_V7_CP14 = 0x04,
75 };
76
77 typedef struct arm11_common_s
78 {
79 target_t * target; /**< Reference back to the owner */
80
81 arm_jtag_t jtag_info; /**< Handler to access assigned JTAG device */
82
83 /** \name Processor type detection */
84 /*@{*/
85
86 u32 device_id; /**< IDCODE readout */
87 u32 didr; /**< DIDR readout (debug capabilities) */
88 u8 implementor; /**< DIDR Implementor readout */
89
90 size_t brp; /**< Number of Breakpoint Register Pairs from DIDR */
91 size_t wrp; /**< Number of Watchpoint Register Pairs from DIDR */
92
93 enum arm11_debug_version
94 debug_version; /**< ARM debug architecture from DIDR */
95 /*@}*/
96
97 u32 last_dscr; /**< Last retrieved DSCR value;
98 Use only for debug message generation */
99
100 bool trst_active;
101 bool halt_requested; /**< Keep track if arm11_halt() calls occured
102 during reset. Otherwise do it ASAP. */
103
104 bool simulate_reset_on_next_halt; /**< Perform cleanups of the ARM state on next halt */
105
106 /** \name Shadow registers to save processor state */
107 /*@{*/
108
109 reg_t * reg_list; /**< target register list */
110 u32 reg_values[ARM11_REGCACHE_COUNT]; /**< data for registers */
111
112 /*@}*/
113
114 arm11_register_history_t
115 reg_history[ARM11_REGCACHE_COUNT]; /**< register state before last resume */
116
117 size_t free_brps; /**< keep track of breakpoints allocated by arm11_add_breakpoint() */
118 size_t free_wrps; /**< keep track of breakpoints allocated by arm11_add_watchpoint() */
119
120 // GA
121 reg_cache_t *core_cache;
122 } arm11_common_t;
123
124
125 /**
126 * ARM11 DBGTAP instructions
127 *
128 * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0301f/I1006229.html
129 */
130 enum arm11_instructions
131 {
132 ARM11_EXTEST = 0x00,
133 ARM11_SCAN_N = 0x02,
134 ARM11_RESTART = 0x04,
135 ARM11_HALT = 0x08,
136 ARM11_INTEST = 0x0C,
137 ARM11_ITRSEL = 0x1D,
138 ARM11_IDCODE = 0x1E,
139 ARM11_BYPASS = 0x1F,
140 };
141
142 enum arm11_dscr
143 {
144 ARM11_DSCR_CORE_HALTED = 1 << 0,
145 ARM11_DSCR_CORE_RESTARTED = 1 << 1,
146
147 ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_MASK = 0x0F << 2,
148 ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_HALT = 0x00 << 2,
149 ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BREAKPOINT = 0x01 << 2,
150 ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_WATCHPOINT = 0x02 << 2,
151 ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BKPT_INSTRUCTION = 0x03 << 2,
152 ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_EDBGRQ = 0x04 << 2,
153 ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_VECTOR_CATCH = 0x05 << 2,
154
155 ARM11_DSCR_STICKY_PRECISE_DATA_ABORT = 1 << 6,
156 ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT = 1 << 7,
157 ARM11_DSCR_INTERRUPTS_DISABLE = 1 << 11,
158 ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE = 1 << 13,
159 ARM11_DSCR_MODE_SELECT = 1 << 14,
160 ARM11_DSCR_WDTR_FULL = 1 << 29,
161 ARM11_DSCR_RDTR_FULL = 1 << 30,
162 };
163
164 enum arm11_cpsr
165 {
166 ARM11_CPSR_T = 1 << 5,
167 ARM11_CPSR_J = 1 << 24,
168 };
169
170 enum arm11_sc7
171 {
172 ARM11_SC7_NULL = 0,
173 ARM11_SC7_VCR = 7,
174 ARM11_SC7_PC = 8,
175 ARM11_SC7_BVR0 = 64,
176 ARM11_SC7_BCR0 = 80,
177 ARM11_SC7_WVR0 = 96,
178 ARM11_SC7_WCR0 = 112,
179 };
180
181 typedef struct arm11_reg_state_s
182 {
183 u32 def_index;
184 target_t * target;
185 } arm11_reg_state_t;
186
187 /* poll current target status */
188 int arm11_poll(struct target_s *target);
189 /* architecture specific status reply */
190 int arm11_arch_state(struct target_s *target);
191
192 /* target request support */
193 int arm11_target_request_data(struct target_s *target, u32 size, u8 *buffer);
194
195 /* target execution control */
196 int arm11_halt(struct target_s *target);
197 int arm11_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution);
198 int arm11_step(struct target_s *target, int current, u32 address, int handle_breakpoints);
199 int arm11_examine(struct target_s *target);
200
201 /* target reset control */
202 int arm11_assert_reset(struct target_s *target);
203 int arm11_deassert_reset(struct target_s *target);
204 int arm11_soft_reset_halt(struct target_s *target);
205
206 /* target register access for gdb */
207 int arm11_get_gdb_reg_list(struct target_s *target, struct reg_s **reg_list[], int *reg_list_size);
208
209 /* target memory access
210 * size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
211 * count: number of items of <size>
212 */
213 int arm11_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
214 int arm11_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
215
216 /* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
217 int arm11_bulk_write_memory(struct target_s *target, u32 address, u32 count, u8 *buffer);
218
219 int arm11_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum);
220
221 /* target break-/watchpoint control
222 * rw: 0 = write, 1 = read, 2 = access
223 */
224 int arm11_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
225 int arm11_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
226 int arm11_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint);
227 int arm11_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint);
228
229 /* target algorithm support */
230 int arm11_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_param, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info);
231
232 int arm11_register_commands(struct command_context_s *cmd_ctx);
233 int arm11_target_create(struct target_s *target, Jim_Interp *interp);
234 int arm11_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
235 int arm11_quit(void);
236
237 /* helpers */
238 int arm11_build_reg_cache(target_t *target);
239 int arm11_set_reg(reg_t *reg, u8 *buf);
240 int arm11_get_reg(reg_t *reg);
241
242 void arm11_record_register_history(arm11_common_t * arm11);
243 void arm11_dump_reg_changes(arm11_common_t * arm11);
244
245 /* internals */
246
247 void arm11_setup_field (arm11_common_t * arm11, int num_bits, void * in_data, void * out_data, scan_field_t * field);
248 void arm11_add_IR (arm11_common_t * arm11, u8 instr, tap_state_t state);
249 void arm11_add_debug_SCAN_N (arm11_common_t * arm11, u8 chain, tap_state_t state);
250 void arm11_add_debug_INST (arm11_common_t * arm11, u32 inst, u8 * flag, tap_state_t state);
251 int arm11_read_DSCR (arm11_common_t * arm11, u32 *dscr);
252 int arm11_write_DSCR (arm11_common_t * arm11, u32 dscr);
253
254 enum target_debug_reason arm11_get_DSCR_debug_reason(u32 dscr);
255
256 void arm11_run_instr_data_prepare (arm11_common_t * arm11);
257 void arm11_run_instr_data_finish (arm11_common_t * arm11);
258 int arm11_run_instr_no_data (arm11_common_t * arm11, u32 * opcode, size_t count);
259 void arm11_run_instr_no_data1 (arm11_common_t * arm11, u32 opcode);
260 int arm11_run_instr_data_to_core (arm11_common_t * arm11, u32 opcode, u32 * data, size_t count);
261 int arm11_run_instr_data_to_core_noack (arm11_common_t * arm11, u32 opcode, u32 * data, size_t count);
262 int arm11_run_instr_data_to_core1 (arm11_common_t * arm11, u32 opcode, u32 data);
263 int arm11_run_instr_data_from_core (arm11_common_t * arm11, u32 opcode, u32 * data, size_t count);
264 void arm11_run_instr_data_from_core_via_r0 (arm11_common_t * arm11, u32 opcode, u32 * data);
265 void arm11_run_instr_data_to_core_via_r0 (arm11_common_t * arm11, u32 opcode, u32 data);
266
267 int arm11_add_dr_scan_vc(int num_fields, scan_field_t *fields, tap_state_t state);
268 int arm11_add_ir_scan_vc(int num_fields, scan_field_t *fields, tap_state_t state);
269
270 /** Used to make a list of read/write commands for scan chain 7
271 *
272 * Use with arm11_sc7_run()
273 */
274 typedef struct arm11_sc7_action_s
275 {
276 bool write; /**< Access mode: true for write, false for read. */
277 u8 address; /**< Register address mode. Use enum #arm11_sc7 */
278 u32 value; /**< If write then set this to value to be written.
279 In read mode this receives the read value when the
280 function returns. */
281 } arm11_sc7_action_t;
282
283 int arm11_sc7_run(arm11_common_t * arm11, arm11_sc7_action_t * actions, size_t count);
284
285 /* Mid-level helper functions */
286 void arm11_sc7_clear_vbw(arm11_common_t * arm11);
287 void arm11_sc7_set_vcr(arm11_common_t * arm11, u32 value);
288
289 int arm11_read_memory_word(arm11_common_t * arm11, u32 address, u32 * result);
290
291 #endif /* ARM11_H */
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