1 /***************************************************************************
2 * Copyright (C) 2008 digenius technology GmbH. *
5 * Copyright (C) 2008,2009 Oyvind Harboe oyvind.harboe@zylin.com *
7 * Copyright (C) 2008 Georg Acher <acher@in.tum.de> *
9 * This program is free software; you can redistribute it and/or modify *
10 * it under the terms of the GNU General Public License as published by *
11 * the Free Software Foundation; either version 2 of the License, or *
12 * (at your option) any later version. *
14 * This program is distributed in the hope that it will be useful, *
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
17 * GNU General Public License for more details. *
19 * You should have received a copy of the GNU General Public License *
20 * along with this program; if not, write to the *
21 * Free Software Foundation, Inc., *
22 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
23 ***************************************************************************/
30 #include "breakpoints.h"
31 #include "arm11_dbgtap.h"
32 #include "arm_simulator.h"
33 #include "time_support.h"
34 #include "target_type.h"
35 #include "algorithm.h"
40 #define _DEBUG_INSTRUCTION_EXECUTION_
43 static bool arm11_config_memwrite_burst
= true;
44 static bool arm11_config_memwrite_error_fatal
= true;
45 static uint32_t arm11_vcr
= 0;
46 static bool arm11_config_step_irq_enable
= false;
47 static bool arm11_config_hardware_step
= false;
64 ARM11_REGISTER_SPSR_FIQ
,
65 ARM11_REGISTER_SPSR_SVC
,
66 ARM11_REGISTER_SPSR_ABT
,
67 ARM11_REGISTER_SPSR_IRQ
,
68 ARM11_REGISTER_SPSR_UND
,
69 ARM11_REGISTER_SPSR_MON
,
83 enum arm11_regtype type
;
86 /* update arm11_regcache_ids when changing this */
87 static const struct arm11_reg_defs arm11_reg_defs
[] =
89 {"r0", 0, 0, ARM11_REGISTER_CORE
},
90 {"r1", 1, 1, ARM11_REGISTER_CORE
},
91 {"r2", 2, 2, ARM11_REGISTER_CORE
},
92 {"r3", 3, 3, ARM11_REGISTER_CORE
},
93 {"r4", 4, 4, ARM11_REGISTER_CORE
},
94 {"r5", 5, 5, ARM11_REGISTER_CORE
},
95 {"r6", 6, 6, ARM11_REGISTER_CORE
},
96 {"r7", 7, 7, ARM11_REGISTER_CORE
},
97 {"r8", 8, 8, ARM11_REGISTER_CORE
},
98 {"r9", 9, 9, ARM11_REGISTER_CORE
},
99 {"r10", 10, 10, ARM11_REGISTER_CORE
},
100 {"r11", 11, 11, ARM11_REGISTER_CORE
},
101 {"r12", 12, 12, ARM11_REGISTER_CORE
},
102 {"sp", 13, 13, ARM11_REGISTER_CORE
},
103 {"lr", 14, 14, ARM11_REGISTER_CORE
},
104 {"pc", 15, 15, ARM11_REGISTER_CORE
},
106 {"cpsr", 0, 25, ARM11_REGISTER_CPSR
},
108 /* Debug Registers */
109 {"dscr", 0, -1, ARM11_REGISTER_DSCR
},
110 {"wdtr", 0, -1, ARM11_REGISTER_WDTR
},
111 {"rdtr", 0, -1, ARM11_REGISTER_RDTR
},
114 enum arm11_regcache_ids
117 ARM11_RC_RX
= ARM11_RC_R0
,
132 ARM11_RC_SP
= ARM11_RC_R13
,
134 ARM11_RC_LR
= ARM11_RC_R14
,
136 ARM11_RC_PC
= ARM11_RC_R15
,
147 /* GDB expects ARMs to give R0..R15, CPSR, and 7 FPA dummies */
148 #define ARM11_GDB_REGISTER_COUNT 26
150 static int arm11_on_enter_debug_state(struct arm11_common
*arm11
);
151 static int arm11_step(struct target
*target
, int current
,
152 uint32_t address
, int handle_breakpoints
);
154 static int arm11_build_reg_cache(struct target
*target
);
155 static int arm11_set_reg(struct reg
*reg
, uint8_t *buf
);
156 static int arm11_get_reg(struct reg
*reg
);
158 static void arm11_record_register_history(struct arm11_common
* arm11
);
159 static void arm11_dump_reg_changes(struct arm11_common
* arm11
);
162 /** Check and if necessary take control of the system
164 * \param arm11 Target state variable.
165 * \param dscr If the current DSCR content is
166 * available a pointer to a word holding the
167 * DSCR can be passed. Otherwise use NULL.
169 static int arm11_check_init(struct arm11_common
*arm11
, uint32_t *dscr
)
171 uint32_t dscr_local_tmp_copy
;
175 dscr
= &dscr_local_tmp_copy
;
177 CHECK_RETVAL(arm11_read_DSCR(arm11
, dscr
));
180 if (!(*dscr
& ARM11_DSCR_MODE_SELECT
))
182 LOG_DEBUG("Bringing target into debug mode");
184 *dscr
|= ARM11_DSCR_MODE_SELECT
; /* Halt debug-mode */
185 arm11_write_DSCR(arm11
, *dscr
);
187 /* add further reset initialization here */
189 arm11
->simulate_reset_on_next_halt
= true;
191 if (*dscr
& ARM11_DSCR_CORE_HALTED
)
193 /** \todo TODO: this needs further scrutiny because
194 * arm11_on_enter_debug_state() never gets properly called.
195 * As a result we don't read the actual register states from
199 arm11
->target
->state
= TARGET_HALTED
;
200 arm11
->target
->debug_reason
= arm11_get_DSCR_debug_reason(*dscr
);
204 arm11
->target
->state
= TARGET_RUNNING
;
205 arm11
->target
->debug_reason
= DBG_REASON_NOTHALTED
;
208 arm11_sc7_clear_vbw(arm11
);
217 (arm11->reg_values[ARM11_RC_##x])
219 /** Save processor state.
221 * This is called when the HALT instruction has succeeded
222 * or on other occasions that stop the processor.
225 static int arm11_on_enter_debug_state(struct arm11_common
*arm11
)
229 for (size_t i
= 0; i
< ARRAY_SIZE(arm11
->reg_values
); i
++)
231 arm11
->reg_list
[i
].valid
= 1;
232 arm11
->reg_list
[i
].dirty
= 0;
236 CHECK_RETVAL(arm11_read_DSCR(arm11
, &R(DSCR
)));
240 if (R(DSCR
) & ARM11_DSCR_WDTR_FULL
)
242 arm11_add_debug_SCAN_N(arm11
, 0x05, ARM11_TAP_DEFAULT
);
244 arm11_add_IR(arm11
, ARM11_INTEST
, ARM11_TAP_DEFAULT
);
246 struct scan_field chain5_fields
[3];
248 arm11_setup_field(arm11
, 32, NULL
, &R(WDTR
), chain5_fields
+ 0);
249 arm11_setup_field(arm11
, 1, NULL
, NULL
, chain5_fields
+ 1);
250 arm11_setup_field(arm11
, 1, NULL
, NULL
, chain5_fields
+ 2);
252 arm11_add_dr_scan_vc(ARRAY_SIZE(chain5_fields
), chain5_fields
, TAP_DRPAUSE
);
256 arm11
->reg_list
[ARM11_RC_WDTR
].valid
= 0;
260 /* DSCR: set ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE */
261 /* ARM1176 spec says this is needed only for wDTR/rDTR's "ITR mode", but not to issue ITRs
262 ARM1136 seems to require this to issue ITR's as well */
264 uint32_t new_dscr
= R(DSCR
) | ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE
;
266 /* this executes JTAG queue: */
268 arm11_write_DSCR(arm11
, new_dscr
);
272 Before executing any instruction in debug state you have to drain the write buffer.
273 This ensures that no imprecise Data Aborts can return at a later point:*/
275 /** \todo TODO: Test drain write buffer. */
280 /* MRC p14,0,R0,c5,c10,0 */
281 // arm11_run_instr_no_data1(arm11, /*0xee150e1a*/0xe320f000);
283 /* mcr 15, 0, r0, cr7, cr10, {4} */
284 arm11_run_instr_no_data1(arm11
, 0xee070f9a);
286 uint32_t dscr
= arm11_read_DSCR(arm11
);
288 LOG_DEBUG("DRAIN, DSCR %08x", dscr
);
290 if (dscr
& ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT
)
292 arm11_run_instr_no_data1(arm11
, 0xe320f000);
294 dscr
= arm11_read_DSCR(arm11
);
296 LOG_DEBUG("DRAIN, DSCR %08x (DONE)", dscr
);
303 retval
= arm11_run_instr_data_prepare(arm11
);
304 if (retval
!= ERROR_OK
)
309 /** \todo TODO: handle other mode registers */
311 for (size_t i
= 0; i
< 15; i
++)
313 /* MCR p14,0,R?,c0,c5,0 */
314 retval
= arm11_run_instr_data_from_core(arm11
, 0xEE000E15 | (i
<< 12), &R(RX
+ i
), 1);
315 if (retval
!= ERROR_OK
)
321 /* check rDTRfull in DSCR */
323 if (R(DSCR
) & ARM11_DSCR_RDTR_FULL
)
325 /* MRC p14,0,R0,c0,c5,0 (move rDTR -> r0 (-> wDTR -> local var)) */
326 retval
= arm11_run_instr_data_from_core_via_r0(arm11
, 0xEE100E15, &R(RDTR
));
327 if (retval
!= ERROR_OK
)
332 arm11
->reg_list
[ARM11_RC_RDTR
].valid
= 0;
337 /* MRS r0,CPSR (move CPSR -> r0 (-> wDTR -> local var)) */
338 retval
= arm11_run_instr_data_from_core_via_r0(arm11
, 0xE10F0000, &R(CPSR
));
339 if (retval
!= ERROR_OK
)
344 /* MOV R0,PC (move PC -> r0 (-> wDTR -> local var)) */
345 retval
= arm11_run_instr_data_from_core_via_r0(arm11
, 0xE1A0000F, &R(PC
));
346 if (retval
!= ERROR_OK
)
349 /* adjust PC depending on ARM state */
351 if (R(CPSR
) & ARM11_CPSR_J
) /* Java state */
353 arm11
->reg_values
[ARM11_RC_PC
] -= 0;
355 else if (R(CPSR
) & ARM11_CPSR_T
) /* Thumb state */
357 arm11
->reg_values
[ARM11_RC_PC
] -= 4;
361 arm11
->reg_values
[ARM11_RC_PC
] -= 8;
364 if (arm11
->simulate_reset_on_next_halt
)
366 arm11
->simulate_reset_on_next_halt
= false;
368 LOG_DEBUG("Reset c1 Control Register");
370 /* Write 0 (reset value) to Control register 0 to disable MMU/Cache etc. */
372 /* MCR p15,0,R0,c1,c0,0 */
373 retval
= arm11_run_instr_data_to_core_via_r0(arm11
, 0xee010f10, 0);
374 if (retval
!= ERROR_OK
)
379 retval
= arm11_run_instr_data_finish(arm11
);
380 if (retval
!= ERROR_OK
)
383 arm11_dump_reg_changes(arm11
);
388 void arm11_dump_reg_changes(struct arm11_common
* arm11
)
391 if (!(debug_level
>= LOG_LVL_DEBUG
))
396 for (size_t i
= 0; i
< ARM11_REGCACHE_COUNT
; i
++)
398 if (!arm11
->reg_list
[i
].valid
)
400 if (arm11
->reg_history
[i
].valid
)
401 LOG_DEBUG("%8s INVALID (%08" PRIx32
")", arm11_reg_defs
[i
].name
, arm11
->reg_history
[i
].value
);
405 if (arm11
->reg_history
[i
].valid
)
407 if (arm11
->reg_history
[i
].value
!= arm11
->reg_values
[i
])
408 LOG_DEBUG("%8s %08" PRIx32
" (%08" PRIx32
")", arm11_reg_defs
[i
].name
, arm11
->reg_values
[i
], arm11
->reg_history
[i
].value
);
412 LOG_DEBUG("%8s %08" PRIx32
" (INVALID)", arm11_reg_defs
[i
].name
, arm11
->reg_values
[i
]);
418 /** Restore processor state
420 * This is called in preparation for the RESTART function.
423 static int arm11_leave_debug_state(struct arm11_common
*arm11
)
427 retval
= arm11_run_instr_data_prepare(arm11
);
428 if (retval
!= ERROR_OK
)
431 /** \todo TODO: handle other mode registers */
433 /* restore R1 - R14 */
435 for (unsigned i
= 1; i
< 15; i
++)
437 if (!arm11
->reg_list
[ARM11_RC_RX
+ i
].dirty
)
440 /* MRC p14,0,r?,c0,c5,0 */
441 arm11_run_instr_data_to_core1(arm11
,
442 0xee100e15 | (i
<< 12), R(RX
+ i
));
444 // LOG_DEBUG("RESTORE R%u %08x", i, R(RX + i));
447 retval
= arm11_run_instr_data_finish(arm11
);
448 if (retval
!= ERROR_OK
)
451 /* spec says clear wDTR and rDTR; we assume they are clear as
452 otherwise our programming would be sloppy */
456 CHECK_RETVAL(arm11_read_DSCR(arm11
, &DSCR
));
458 if (DSCR
& (ARM11_DSCR_RDTR_FULL
| ARM11_DSCR_WDTR_FULL
))
461 The wDTR/rDTR two registers that are used to send/receive data to/from
462 the core in tandem with corresponding instruction codes that are
463 written into the core. The RDTR FULL/WDTR FULL flag indicates that the
464 registers hold data that was written by one side (CPU or JTAG) and not
465 read out by the other side.
467 LOG_ERROR("wDTR/rDTR inconsistent (DSCR %08" PRIx32
")", DSCR
);
472 retval
= arm11_run_instr_data_prepare(arm11
);
473 if (retval
!= ERROR_OK
)
476 /* restore original wDTR */
478 if ((R(DSCR
) & ARM11_DSCR_WDTR_FULL
) || arm11
->reg_list
[ARM11_RC_WDTR
].dirty
)
480 /* MCR p14,0,R0,c0,c5,0 */
481 retval
= arm11_run_instr_data_to_core_via_r0(arm11
, 0xee000e15, R(WDTR
));
482 if (retval
!= ERROR_OK
)
489 retval
= arm11_run_instr_data_to_core_via_r0(arm11
, 0xe129f000, R(CPSR
));
490 if (retval
!= ERROR_OK
)
497 retval
= arm11_run_instr_data_to_core_via_r0(arm11
, 0xe1a0f000, R(PC
));
498 if (retval
!= ERROR_OK
)
504 /* MRC p14,0,r0,c0,c5,0 */
505 arm11_run_instr_data_to_core1(arm11
, 0xee100e15, R(R0
));
507 retval
= arm11_run_instr_data_finish(arm11
);
508 if (retval
!= ERROR_OK
)
513 arm11_write_DSCR(arm11
, R(DSCR
));
517 if (R(DSCR
) & ARM11_DSCR_RDTR_FULL
|| arm11
->reg_list
[ARM11_RC_RDTR
].dirty
)
519 arm11_add_debug_SCAN_N(arm11
, 0x05, ARM11_TAP_DEFAULT
);
521 arm11_add_IR(arm11
, ARM11_EXTEST
, ARM11_TAP_DEFAULT
);
523 struct scan_field chain5_fields
[3];
525 uint8_t Ready
= 0; /* ignored */
526 uint8_t Valid
= 0; /* ignored */
528 arm11_setup_field(arm11
, 32, &R(RDTR
), NULL
, chain5_fields
+ 0);
529 arm11_setup_field(arm11
, 1, &Ready
, NULL
, chain5_fields
+ 1);
530 arm11_setup_field(arm11
, 1, &Valid
, NULL
, chain5_fields
+ 2);
532 arm11_add_dr_scan_vc(ARRAY_SIZE(chain5_fields
), chain5_fields
, TAP_DRPAUSE
);
535 arm11_record_register_history(arm11
);
540 static void arm11_record_register_history(struct arm11_common
*arm11
)
542 for (size_t i
= 0; i
< ARM11_REGCACHE_COUNT
; i
++)
544 arm11
->reg_history
[i
].value
= arm11
->reg_values
[i
];
545 arm11
->reg_history
[i
].valid
= arm11
->reg_list
[i
].valid
;
547 arm11
->reg_list
[i
].valid
= 0;
548 arm11
->reg_list
[i
].dirty
= 0;
553 /* poll current target status */
554 static int arm11_poll(struct target
*target
)
557 struct arm11_common
*arm11
= target_to_arm11(target
);
560 CHECK_RETVAL(arm11_read_DSCR(arm11
, &dscr
));
562 LOG_DEBUG("DSCR %08" PRIx32
"", dscr
);
564 CHECK_RETVAL(arm11_check_init(arm11
, &dscr
));
566 if (dscr
& ARM11_DSCR_CORE_HALTED
)
568 if (target
->state
!= TARGET_HALTED
)
570 enum target_state old_state
= target
->state
;
572 LOG_DEBUG("enter TARGET_HALTED");
573 target
->state
= TARGET_HALTED
;
574 target
->debug_reason
= arm11_get_DSCR_debug_reason(dscr
);
575 retval
= arm11_on_enter_debug_state(arm11
);
576 if (retval
!= ERROR_OK
)
579 target_call_event_callbacks(target
,
580 old_state
== TARGET_DEBUG_RUNNING
? TARGET_EVENT_DEBUG_HALTED
: TARGET_EVENT_HALTED
);
585 if (target
->state
!= TARGET_RUNNING
&& target
->state
!= TARGET_DEBUG_RUNNING
)
587 LOG_DEBUG("enter TARGET_RUNNING");
588 target
->state
= TARGET_RUNNING
;
589 target
->debug_reason
= DBG_REASON_NOTHALTED
;
595 /* architecture specific status reply */
596 static int arm11_arch_state(struct target
*target
)
598 struct arm11_common
*arm11
= target_to_arm11(target
);
600 LOG_USER("target halted due to %s\ncpsr: 0x%8.8" PRIx32
" pc: 0x%8.8" PRIx32
"",
601 Jim_Nvp_value2name_simple(nvp_target_debug_reason
, target
->debug_reason
)->name
,
608 /* target request support */
609 static int arm11_target_request_data(struct target
*target
,
610 uint32_t size
, uint8_t *buffer
)
612 LOG_WARNING("Not implemented: %s", __func__
);
617 /* target execution control */
618 static int arm11_halt(struct target
*target
)
620 struct arm11_common
*arm11
= target_to_arm11(target
);
622 LOG_DEBUG("target->state: %s",
623 target_state_name(target
));
625 if (target
->state
== TARGET_UNKNOWN
)
627 arm11
->simulate_reset_on_next_halt
= true;
630 if (target
->state
== TARGET_HALTED
)
632 LOG_DEBUG("target was already halted");
636 arm11_add_IR(arm11
, ARM11_HALT
, TAP_IDLE
);
638 CHECK_RETVAL(jtag_execute_queue());
645 CHECK_RETVAL(arm11_read_DSCR(arm11
, &dscr
));
647 if (dscr
& ARM11_DSCR_CORE_HALTED
)
658 if ((timeval_ms()-then
) > 1000)
660 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
667 arm11_on_enter_debug_state(arm11
);
669 enum target_state old_state
= target
->state
;
671 target
->state
= TARGET_HALTED
;
672 target
->debug_reason
= arm11_get_DSCR_debug_reason(dscr
);
675 target_call_event_callbacks(target
,
676 old_state
== TARGET_DEBUG_RUNNING
? TARGET_EVENT_DEBUG_HALTED
: TARGET_EVENT_HALTED
));
681 static int arm11_resume(struct target
*target
, int current
,
682 uint32_t address
, int handle_breakpoints
, int debug_execution
)
684 // LOG_DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d",
685 // current, address, handle_breakpoints, debug_execution);
687 struct arm11_common
*arm11
= target_to_arm11(target
);
689 LOG_DEBUG("target->state: %s",
690 target_state_name(target
));
693 if (target
->state
!= TARGET_HALTED
)
695 LOG_ERROR("Target not halted");
696 return ERROR_TARGET_NOT_HALTED
;
702 LOG_DEBUG("RESUME PC %08" PRIx32
"%s", R(PC
), !current
? "!" : "");
704 /* clear breakpoints/watchpoints and VCR*/
705 arm11_sc7_clear_vbw(arm11
);
707 /* Set up breakpoints */
708 if (!debug_execution
)
710 /* check if one matches PC and step over it if necessary */
712 struct breakpoint
* bp
;
714 for (bp
= target
->breakpoints
; bp
; bp
= bp
->next
)
716 if (bp
->address
== R(PC
))
718 LOG_DEBUG("must step over %08" PRIx32
"", bp
->address
);
719 arm11_step(target
, 1, 0, 0);
724 /* set all breakpoints */
726 unsigned brp_num
= 0;
728 for (bp
= target
->breakpoints
; bp
; bp
= bp
->next
)
730 struct arm11_sc7_action brp
[2];
733 brp
[0].address
= ARM11_SC7_BVR0
+ brp_num
;
734 brp
[0].value
= bp
->address
;
736 brp
[1].address
= ARM11_SC7_BCR0
+ brp_num
;
737 brp
[1].value
= 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
739 arm11_sc7_run(arm11
, brp
, ARRAY_SIZE(brp
));
741 LOG_DEBUG("Add BP %d at %08" PRIx32
, brp_num
,
747 arm11_sc7_set_vcr(arm11
, arm11_vcr
);
750 arm11_leave_debug_state(arm11
);
752 arm11_add_IR(arm11
, ARM11_RESTART
, TAP_IDLE
);
754 CHECK_RETVAL(jtag_execute_queue());
761 CHECK_RETVAL(arm11_read_DSCR(arm11
, &dscr
));
763 LOG_DEBUG("DSCR %08" PRIx32
"", dscr
);
765 if (dscr
& ARM11_DSCR_CORE_RESTARTED
)
776 if ((timeval_ms()-then
) > 1000)
778 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
785 if (!debug_execution
)
787 target
->state
= TARGET_RUNNING
;
788 target
->debug_reason
= DBG_REASON_NOTHALTED
;
790 CHECK_RETVAL(target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
));
794 target
->state
= TARGET_DEBUG_RUNNING
;
795 target
->debug_reason
= DBG_REASON_NOTHALTED
;
797 CHECK_RETVAL(target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
));
804 static int armv4_5_to_arm11(int reg
)
811 return ARM11_RC_CPSR
;
813 /* FIX!!! handle thumb better! */
814 return ARM11_RC_CPSR
;
816 LOG_ERROR("BUG: register translation from armv4_5 to arm11 not supported %d", reg
);
822 static uint32_t arm11_sim_get_reg(struct arm_sim_interface
*sim
, int reg
)
824 struct arm11_common
* arm11
= (struct arm11_common
*)sim
->user_data
;
826 reg
=armv4_5_to_arm11(reg
);
828 return buf_get_u32(arm11
->reg_list
[reg
].value
, 0, 32);
831 static void arm11_sim_set_reg(struct arm_sim_interface
*sim
,
832 int reg
, uint32_t value
)
834 struct arm11_common
* arm11
= (struct arm11_common
*)sim
->user_data
;
836 reg
=armv4_5_to_arm11(reg
);
838 buf_set_u32(arm11
->reg_list
[reg
].value
, 0, 32, value
);
841 static uint32_t arm11_sim_get_cpsr(struct arm_sim_interface
*sim
,
844 struct arm11_common
* arm11
= (struct arm11_common
*)sim
->user_data
;
846 return buf_get_u32(arm11
->reg_list
[ARM11_RC_CPSR
].value
, pos
, bits
);
849 static enum armv4_5_state
arm11_sim_get_state(struct arm_sim_interface
*sim
)
851 // struct arm11_common * arm11 = (struct arm11_common *)sim->user_data;
853 /* FIX!!!! we should implement thumb for arm11 */
854 return ARMV4_5_STATE_ARM
;
857 static void arm11_sim_set_state(struct arm_sim_interface
*sim
,
858 enum armv4_5_state mode
)
860 // struct arm11_common * arm11 = (struct arm11_common *)sim->user_data;
862 /* FIX!!!! we should implement thumb for arm11 */
863 LOG_ERROR("Not implemented: %s", __func__
);
867 static enum armv4_5_mode
arm11_sim_get_mode(struct arm_sim_interface
*sim
)
869 //struct arm11_common * arm11 = (struct arm11_common *)sim->user_data;
871 /* FIX!!!! we should implement something that returns the current mode here!!! */
872 return ARMV4_5_MODE_USR
;
875 static int arm11_simulate_step(struct target
*target
, uint32_t *dry_run_pc
)
877 struct arm_sim_interface sim
;
879 sim
.user_data
=target
->arch_info
;
880 sim
.get_reg
=&arm11_sim_get_reg
;
881 sim
.set_reg
=&arm11_sim_set_reg
;
882 sim
.get_reg_mode
=&arm11_sim_get_reg
;
883 sim
.set_reg_mode
=&arm11_sim_set_reg
;
884 sim
.get_cpsr
=&arm11_sim_get_cpsr
;
885 sim
.get_mode
=&arm11_sim_get_mode
;
886 sim
.get_state
=&arm11_sim_get_state
;
887 sim
.set_state
=&arm11_sim_set_state
;
889 return arm_simulate_step_core(target
, dry_run_pc
, &sim
);
893 static int arm11_step(struct target
*target
, int current
,
894 uint32_t address
, int handle_breakpoints
)
896 LOG_DEBUG("target->state: %s",
897 target_state_name(target
));
899 if (target
->state
!= TARGET_HALTED
)
901 LOG_WARNING("target was not halted");
902 return ERROR_TARGET_NOT_HALTED
;
905 struct arm11_common
*arm11
= target_to_arm11(target
);
910 LOG_DEBUG("STEP PC %08" PRIx32
"%s", R(PC
), !current
? "!" : "");
913 /** \todo TODO: Thumb not supported here */
915 uint32_t next_instruction
;
917 CHECK_RETVAL(arm11_read_memory_word(arm11
, R(PC
), &next_instruction
));
920 if ((next_instruction
& 0xFFF00070) == 0xe1200070)
923 arm11
->reg_list
[ARM11_RC_PC
].valid
= 1;
924 arm11
->reg_list
[ARM11_RC_PC
].dirty
= 0;
925 LOG_DEBUG("Skipping BKPT");
927 /* skip over Wait for interrupt / Standby */
928 /* mcr 15, 0, r?, cr7, cr0, {4} */
929 else if ((next_instruction
& 0xFFFF0FFF) == 0xee070f90)
932 arm11
->reg_list
[ARM11_RC_PC
].valid
= 1;
933 arm11
->reg_list
[ARM11_RC_PC
].dirty
= 0;
934 LOG_DEBUG("Skipping WFI");
936 /* ignore B to self */
937 else if ((next_instruction
& 0xFEFFFFFF) == 0xeafffffe)
939 LOG_DEBUG("Not stepping jump to self");
943 /** \todo TODO: check if break-/watchpoints make any sense at all in combination
946 /** \todo TODO: check if disabling IRQs might be a good idea here. Alternatively
947 * the VCR might be something worth looking into. */
950 /* Set up breakpoint for stepping */
952 struct arm11_sc7_action brp
[2];
955 brp
[0].address
= ARM11_SC7_BVR0
;
957 brp
[1].address
= ARM11_SC7_BCR0
;
959 if (arm11_config_hardware_step
)
961 /* hardware single stepping be used if possible or is it better to
962 * always use the same code path? Hardware single stepping is not supported
965 brp
[0].value
= R(PC
);
966 brp
[1].value
= 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (2 << 21);
969 /* sets a breakpoint on the next PC(calculated by simulation),
973 retval
= arm11_simulate_step(target
, &next_pc
);
974 if (retval
!= ERROR_OK
)
977 brp
[0].value
= next_pc
;
978 brp
[1].value
= 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
981 CHECK_RETVAL(arm11_sc7_run(arm11
, brp
, ARRAY_SIZE(brp
)));
986 if (arm11_config_step_irq_enable
)
987 R(DSCR
) &= ~ARM11_DSCR_INTERRUPTS_DISABLE
; /* should be redundant */
989 R(DSCR
) |= ARM11_DSCR_INTERRUPTS_DISABLE
;
992 CHECK_RETVAL(arm11_leave_debug_state(arm11
));
994 arm11_add_IR(arm11
, ARM11_RESTART
, TAP_IDLE
);
996 CHECK_RETVAL(jtag_execute_queue());
1004 CHECK_RETVAL(arm11_read_DSCR(arm11
, &dscr
));
1006 LOG_DEBUG("DSCR %08" PRIx32
"e", dscr
);
1008 if ((dscr
& (ARM11_DSCR_CORE_RESTARTED
| ARM11_DSCR_CORE_HALTED
)) ==
1009 (ARM11_DSCR_CORE_RESTARTED
| ARM11_DSCR_CORE_HALTED
))
1015 then
= timeval_ms();
1019 if ((timeval_ms()-then
) > 1000)
1021 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
1028 /* clear breakpoint */
1029 arm11_sc7_clear_vbw(arm11
);
1032 CHECK_RETVAL(arm11_on_enter_debug_state(arm11
));
1034 /* restore default state */
1035 R(DSCR
) &= ~ARM11_DSCR_INTERRUPTS_DISABLE
;
1039 // target->state = TARGET_HALTED;
1040 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
1042 CHECK_RETVAL(target_call_event_callbacks(target
, TARGET_EVENT_HALTED
));
1047 static int arm11_assert_reset(struct target
*target
)
1050 struct arm11_common
*arm11
= target_to_arm11(target
);
1052 retval
= arm11_check_init(arm11
, NULL
);
1053 if (retval
!= ERROR_OK
)
1056 target
->state
= TARGET_UNKNOWN
;
1058 /* we would very much like to reset into the halted, state,
1059 * but resetting and halting is second best... */
1060 if (target
->reset_halt
)
1062 CHECK_RETVAL(target_halt(target
));
1066 /* srst is funny. We can not do *anything* else while it's asserted
1067 * and it has unkonwn side effects. Make sure no other code runs
1070 * Code below assumes srst:
1072 * - Causes power-on-reset (but of what parts of the system?). Bug
1075 * - Messes us TAP state without asserting trst.
1077 * - There is another bug in the arm11 core. When you generate an access to
1078 * external logic (for example ddr controller via AHB bus) and that block
1079 * is not configured (perhaps it is still held in reset), that transaction
1080 * will never complete. This will hang arm11 core but it will also hang
1081 * JTAG controller. Nothing, short of srst assertion will bring it out of
1086 * - What should the PC be after an srst reset when starting in the halted
1090 jtag_add_reset(0, 1);
1091 jtag_add_reset(0, 0);
1093 /* How long do we have to wait? */
1094 jtag_add_sleep(5000);
1096 /* un-mess up TAP state */
1099 retval
= jtag_execute_queue();
1100 if (retval
!= ERROR_OK
)
1108 static int arm11_deassert_reset(struct target
*target
)
1113 static int arm11_soft_reset_halt(struct target
*target
)
1115 LOG_WARNING("Not implemented: %s", __func__
);
1120 /* target register access for gdb */
1121 static int arm11_get_gdb_reg_list(struct target
*target
,
1122 struct reg
**reg_list
[], int *reg_list_size
)
1124 struct arm11_common
*arm11
= target_to_arm11(target
);
1126 *reg_list_size
= ARM11_GDB_REGISTER_COUNT
;
1127 *reg_list
= malloc(sizeof(struct reg
*) * ARM11_GDB_REGISTER_COUNT
);
1129 /* nine unused legacy FPA registers are expected by GDB */
1130 for (size_t i
= 16; i
< 24; i
++)
1131 (*reg_list
)[i
] = &arm_gdb_dummy_fp_reg
;
1132 (*reg_list
)[24] = &arm_gdb_dummy_fps_reg
;
1134 for (size_t i
= 0; i
< ARM11_REGCACHE_COUNT
; i
++)
1136 if (arm11_reg_defs
[i
].gdb_num
== -1)
1139 (*reg_list
)[arm11_reg_defs
[i
].gdb_num
] = arm11
->reg_list
+ i
;
1145 /* target memory access
1146 * size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
1147 * count: number of items of <size>
1149 * arm11_config_memrw_no_increment - in the future we may want to be able
1150 * to read/write a range of data to a "port". a "port" is an action on
1151 * read memory address for some peripheral.
1153 static int arm11_read_memory_inner(struct target
*target
,
1154 uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
,
1155 bool arm11_config_memrw_no_increment
)
1157 /** \todo TODO: check if buffer cast to uint32_t* and uint16_t* might cause alignment problems */
1160 if (target
->state
!= TARGET_HALTED
)
1162 LOG_WARNING("target was not halted");
1163 return ERROR_TARGET_NOT_HALTED
;
1166 LOG_DEBUG("ADDR %08" PRIx32
" SIZE %08" PRIx32
" COUNT %08" PRIx32
"", address
, size
, count
);
1168 struct arm11_common
*arm11
= target_to_arm11(target
);
1170 retval
= arm11_run_instr_data_prepare(arm11
);
1171 if (retval
!= ERROR_OK
)
1174 /* MRC p14,0,r0,c0,c5,0 */
1175 retval
= arm11_run_instr_data_to_core1(arm11
, 0xee100e15, address
);
1176 if (retval
!= ERROR_OK
)
1182 /** \todo TODO: check if dirty is the right choice to force a rewrite on arm11_resume() */
1183 arm11
->reg_list
[ARM11_RC_R1
].dirty
= 1;
1185 for (size_t i
= 0; i
< count
; i
++)
1187 /* ldrb r1, [r0], #1 */
1189 arm11_run_instr_no_data1(arm11
,
1190 !arm11_config_memrw_no_increment
? 0xe4d01001 : 0xe5d01000);
1193 /* MCR p14,0,R1,c0,c5,0 */
1194 arm11_run_instr_data_from_core(arm11
, 0xEE001E15, &res
, 1);
1203 arm11
->reg_list
[ARM11_RC_R1
].dirty
= 1;
1205 for (size_t i
= 0; i
< count
; i
++)
1207 /* ldrh r1, [r0], #2 */
1208 arm11_run_instr_no_data1(arm11
,
1209 !arm11_config_memrw_no_increment
? 0xe0d010b2 : 0xe1d010b0);
1213 /* MCR p14,0,R1,c0,c5,0 */
1214 arm11_run_instr_data_from_core(arm11
, 0xEE001E15, &res
, 1);
1216 uint16_t svalue
= res
;
1217 memcpy(buffer
+ i
* sizeof(uint16_t), &svalue
, sizeof(uint16_t));
1225 uint32_t instr
= !arm11_config_memrw_no_increment
? 0xecb05e01 : 0xed905e00;
1226 /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
1227 uint32_t *words
= (uint32_t *)buffer
;
1229 /* LDC p14,c5,[R0],#4 */
1230 /* LDC p14,c5,[R0] */
1231 arm11_run_instr_data_from_core(arm11
, instr
, words
, count
);
1236 return arm11_run_instr_data_finish(arm11
);
1239 static int arm11_read_memory(struct target
*target
, uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
)
1241 return arm11_read_memory_inner(target
, address
, size
, count
, buffer
, false);
1245 * arm11_config_memrw_no_increment - in the future we may want to be able
1246 * to read/write a range of data to a "port". a "port" is an action on
1247 * read memory address for some peripheral.
1249 static int arm11_write_memory_inner(struct target
*target
,
1250 uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
,
1251 bool arm11_config_memrw_no_increment
)
1255 if (target
->state
!= TARGET_HALTED
)
1257 LOG_WARNING("target was not halted");
1258 return ERROR_TARGET_NOT_HALTED
;
1261 LOG_DEBUG("ADDR %08" PRIx32
" SIZE %08" PRIx32
" COUNT %08" PRIx32
"", address
, size
, count
);
1263 struct arm11_common
*arm11
= target_to_arm11(target
);
1265 retval
= arm11_run_instr_data_prepare(arm11
);
1266 if (retval
!= ERROR_OK
)
1269 /* MRC p14,0,r0,c0,c5,0 */
1270 retval
= arm11_run_instr_data_to_core1(arm11
, 0xee100e15, address
);
1271 if (retval
!= ERROR_OK
)
1274 /* burst writes are not used for single words as those may well be
1275 * reset init script writes.
1277 * The other advantage is that as burst writes are default, we'll
1278 * now exercise both burst and non-burst code paths with the
1279 * default settings, increasing code coverage.
1281 bool burst
= arm11_config_memwrite_burst
&& (count
> 1);
1287 arm11
->reg_list
[ARM11_RC_R1
].dirty
= 1;
1289 for (size_t i
= 0; i
< count
; i
++)
1291 /* MRC p14,0,r1,c0,c5,0 */
1292 retval
= arm11_run_instr_data_to_core1(arm11
, 0xee101e15, *buffer
++);
1293 if (retval
!= ERROR_OK
)
1296 /* strb r1, [r0], #1 */
1298 retval
= arm11_run_instr_no_data1(arm11
,
1299 !arm11_config_memrw_no_increment
? 0xe4c01001 : 0xe5c01000);
1300 if (retval
!= ERROR_OK
)
1309 arm11
->reg_list
[ARM11_RC_R1
].dirty
= 1;
1311 for (size_t i
= 0; i
< count
; i
++)
1314 memcpy(&value
, buffer
+ i
* sizeof(uint16_t), sizeof(uint16_t));
1316 /* MRC p14,0,r1,c0,c5,0 */
1317 retval
= arm11_run_instr_data_to_core1(arm11
, 0xee101e15, value
);
1318 if (retval
!= ERROR_OK
)
1321 /* strh r1, [r0], #2 */
1323 retval
= arm11_run_instr_no_data1(arm11
,
1324 !arm11_config_memrw_no_increment
? 0xe0c010b2 : 0xe1c010b0);
1325 if (retval
!= ERROR_OK
)
1333 uint32_t instr
= !arm11_config_memrw_no_increment
? 0xeca05e01 : 0xed805e00;
1335 /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
1336 uint32_t *words
= (uint32_t*)buffer
;
1340 /* STC p14,c5,[R0],#4 */
1341 /* STC p14,c5,[R0]*/
1342 retval
= arm11_run_instr_data_to_core(arm11
, instr
, words
, count
);
1343 if (retval
!= ERROR_OK
)
1348 /* STC p14,c5,[R0],#4 */
1349 /* STC p14,c5,[R0]*/
1350 retval
= arm11_run_instr_data_to_core_noack(arm11
, instr
, words
, count
);
1351 if (retval
!= ERROR_OK
)
1359 /* r0 verification */
1360 if (!arm11_config_memrw_no_increment
)
1364 /* MCR p14,0,R0,c0,c5,0 */
1365 retval
= arm11_run_instr_data_from_core(arm11
, 0xEE000E15, &r0
, 1);
1366 if (retval
!= ERROR_OK
)
1369 if (address
+ size
* count
!= r0
)
1371 LOG_ERROR("Data transfer failed. Expected end "
1372 "address 0x%08x, got 0x%08x",
1373 (unsigned) (address
+ size
* count
),
1377 LOG_ERROR("use 'arm11 memwrite burst disable' to disable fast burst mode");
1379 if (arm11_config_memwrite_error_fatal
)
1384 return arm11_run_instr_data_finish(arm11
);
1387 static int arm11_write_memory(struct target
*target
,
1388 uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
)
1390 return arm11_write_memory_inner(target
, address
, size
, count
, buffer
, false);
1393 /* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
1394 static int arm11_bulk_write_memory(struct target
*target
,
1395 uint32_t address
, uint32_t count
, uint8_t *buffer
)
1397 if (target
->state
!= TARGET_HALTED
)
1399 LOG_WARNING("target was not halted");
1400 return ERROR_TARGET_NOT_HALTED
;
1403 return arm11_write_memory(target
, address
, 4, count
, buffer
);
1406 /* target break-/watchpoint control
1407 * rw: 0 = write, 1 = read, 2 = access
1409 static int arm11_add_breakpoint(struct target
*target
,
1410 struct breakpoint
*breakpoint
)
1412 struct arm11_common
*arm11
= target_to_arm11(target
);
1415 if (breakpoint
->type
== BKPT_SOFT
)
1417 LOG_INFO("sw breakpoint requested, but software breakpoints not enabled");
1418 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1422 if (!arm11
->free_brps
)
1424 LOG_DEBUG("no breakpoint unit available for hardware breakpoint");
1425 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1428 if (breakpoint
->length
!= 4)
1430 LOG_DEBUG("only breakpoints of four bytes length supported");
1431 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1439 static int arm11_remove_breakpoint(struct target
*target
,
1440 struct breakpoint
*breakpoint
)
1442 struct arm11_common
*arm11
= target_to_arm11(target
);
1449 static int arm11_add_watchpoint(struct target
*target
,
1450 struct watchpoint
*watchpoint
)
1452 LOG_WARNING("Not implemented: %s", __func__
);
1457 static int arm11_remove_watchpoint(struct target
*target
,
1458 struct watchpoint
*watchpoint
)
1460 LOG_WARNING("Not implemented: %s", __func__
);
1465 // HACKHACKHACK - FIXME mode/state
1466 /* target algorithm support */
1467 static int arm11_run_algorithm(struct target
*target
,
1468 int num_mem_params
, struct mem_param
*mem_params
,
1469 int num_reg_params
, struct reg_param
*reg_params
,
1470 uint32_t entry_point
, uint32_t exit_point
,
1471 int timeout_ms
, void *arch_info
)
1473 struct arm11_common
*arm11
= target_to_arm11(target
);
1474 // enum armv4_5_state core_state = arm11->core_state;
1475 // enum armv4_5_mode core_mode = arm11->core_mode;
1476 uint32_t context
[16];
1478 int exit_breakpoint_size
= 0;
1479 int retval
= ERROR_OK
;
1480 LOG_DEBUG("Running algorithm");
1483 if (target
->state
!= TARGET_HALTED
)
1485 LOG_WARNING("target not halted");
1486 return ERROR_TARGET_NOT_HALTED
;
1490 // if (!is_arm_mode(arm11->core_mode))
1491 // return ERROR_FAIL;
1494 for (unsigned i
= 0; i
< 16; i
++)
1496 context
[i
] = buf_get_u32((uint8_t*)(&arm11
->reg_values
[i
]),0,32);
1497 LOG_DEBUG("Save %u: 0x%" PRIx32
"", i
, context
[i
]);
1500 cpsr
= buf_get_u32((uint8_t*)(arm11
->reg_values
+ ARM11_RC_CPSR
),0,32);
1501 LOG_DEBUG("Save CPSR: 0x%" PRIx32
"", cpsr
);
1503 for (int i
= 0; i
< num_mem_params
; i
++)
1505 target_write_buffer(target
, mem_params
[i
].address
, mem_params
[i
].size
, mem_params
[i
].value
);
1508 // Set register parameters
1509 for (int i
= 0; i
< num_reg_params
; i
++)
1511 struct reg
*reg
= register_get_by_name(arm11
->core_cache
, reg_params
[i
].reg_name
, 0);
1514 LOG_ERROR("BUG: register '%s' not found", reg_params
[i
].reg_name
);
1515 return ERROR_INVALID_ARGUMENTS
;
1518 if (reg
->size
!= reg_params
[i
].size
)
1520 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params
[i
].reg_name
);
1521 return ERROR_INVALID_ARGUMENTS
;
1523 arm11_set_reg(reg
,reg_params
[i
].value
);
1524 // printf("%i: Set %s =%08x\n", i, reg_params[i].reg_name,val);
1527 exit_breakpoint_size
= 4;
1529 /* arm11->core_state = arm11_algorithm_info->core_state;
1530 if (arm11->core_state == ARMV4_5_STATE_ARM)
1531 exit_breakpoint_size = 4;
1532 else if (arm11->core_state == ARMV4_5_STATE_THUMB)
1533 exit_breakpoint_size = 2;
1536 LOG_ERROR("BUG: can't execute algorithms when not in ARM or Thumb state");
1542 /* arm11 at this point only supports ARM not THUMB mode
1543 however if this test needs to be reactivated the current state can be read back
1546 if (arm11_algorithm_info
->core_mode
!= ARMV4_5_MODE_ANY
)
1548 LOG_DEBUG("setting core_mode: 0x%2.2x", arm11_algorithm_info
->core_mode
);
1549 buf_set_u32(arm11
->reg_list
[ARM11_RC_CPSR
].value
, 0, 5, arm11_algorithm_info
->core_mode
);
1550 arm11
->reg_list
[ARM11_RC_CPSR
].dirty
= 1;
1551 arm11
->reg_list
[ARM11_RC_CPSR
].valid
= 1;
1555 if ((retval
= breakpoint_add(target
, exit_point
, exit_breakpoint_size
, BKPT_HARD
)) != ERROR_OK
)
1557 LOG_ERROR("can't add breakpoint to finish algorithm execution");
1558 retval
= ERROR_TARGET_FAILURE
;
1562 // no debug, otherwise breakpoint is not set
1563 CHECK_RETVAL(target_resume(target
, 0, entry_point
, 1, 0));
1565 CHECK_RETVAL(target_wait_state(target
, TARGET_HALTED
, timeout_ms
));
1567 if (target
->state
!= TARGET_HALTED
)
1569 CHECK_RETVAL(target_halt(target
));
1571 CHECK_RETVAL(target_wait_state(target
, TARGET_HALTED
, 500));
1573 retval
= ERROR_TARGET_TIMEOUT
;
1575 goto del_breakpoint
;
1578 if (buf_get_u32(arm11
->reg_list
[15].value
, 0, 32) != exit_point
)
1580 LOG_WARNING("target reentered debug state, but not at the desired exit point: 0x%4.4" PRIx32
"",
1581 buf_get_u32(arm11
->reg_list
[15].value
, 0, 32));
1582 retval
= ERROR_TARGET_TIMEOUT
;
1583 goto del_breakpoint
;
1586 for (int i
= 0; i
< num_mem_params
; i
++)
1588 if (mem_params
[i
].direction
!= PARAM_OUT
)
1589 target_read_buffer(target
, mem_params
[i
].address
, mem_params
[i
].size
, mem_params
[i
].value
);
1592 for (int i
= 0; i
< num_reg_params
; i
++)
1594 if (reg_params
[i
].direction
!= PARAM_OUT
)
1596 struct reg
*reg
= register_get_by_name(arm11
->core_cache
, reg_params
[i
].reg_name
, 0);
1599 LOG_ERROR("BUG: register '%s' not found", reg_params
[i
].reg_name
);
1600 retval
= ERROR_INVALID_ARGUMENTS
;
1601 goto del_breakpoint
;
1604 if (reg
->size
!= reg_params
[i
].size
)
1606 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params
[i
].reg_name
);
1607 retval
= ERROR_INVALID_ARGUMENTS
;
1608 goto del_breakpoint
;
1611 buf_set_u32(reg_params
[i
].value
, 0, 32, buf_get_u32(reg
->value
, 0, 32));
1616 breakpoint_remove(target
, exit_point
);
1620 for (size_t i
= 0; i
< 16; i
++)
1622 LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32
"",
1623 arm11
->reg_list
[i
].name
, context
[i
]);
1624 arm11_set_reg(&arm11
->reg_list
[i
], (uint8_t*)&context
[i
]);
1626 LOG_DEBUG("restoring CPSR with value 0x%8.8" PRIx32
"", cpsr
);
1627 arm11_set_reg(&arm11
->reg_list
[ARM11_RC_CPSR
], (uint8_t*)&cpsr
);
1629 // arm11->core_state = core_state;
1630 // arm11->core_mode = core_mode;
1635 static int arm11_target_create(struct target
*target
, Jim_Interp
*interp
)
1637 struct arm11_common
*arm11
;
1639 if (target
->tap
== NULL
)
1642 if (target
->tap
->ir_length
!= 5)
1644 LOG_ERROR("'target arm11' expects IR LENGTH = 5");
1645 return ERROR_COMMAND_SYNTAX_ERROR
;
1648 arm11
= calloc(1, sizeof *arm11
);
1652 armv4_5_init_arch_info(target
, &arm11
->arm
);
1654 arm11
->target
= target
;
1656 arm11
->jtag_info
.tap
= target
->tap
;
1657 arm11
->jtag_info
.scann_size
= 5;
1658 arm11
->jtag_info
.scann_instr
= ARM11_SCAN_N
;
1659 /* cur_scan_chain == 0 */
1660 arm11
->jtag_info
.intest_instr
= ARM11_INTEST
;
1665 static int arm11_init_target(struct command_context
*cmd_ctx
,
1666 struct target
*target
)
1668 /* Initialize anything we can set up without talking to the target */
1670 /* FIXME Switch to use the standard build_reg_cache() not custom
1671 * code. Do it from examine(), after we check whether we're
1672 * an arm1176 and thus support the Secure Monitor mode.
1674 return arm11_build_reg_cache(target
);
1677 /* talk to the target and set things up */
1678 static int arm11_examine(struct target
*target
)
1682 struct arm11_common
*arm11
= target_to_arm11(target
);
1686 arm11_add_IR(arm11
, ARM11_IDCODE
, ARM11_TAP_DEFAULT
);
1688 struct scan_field idcode_field
;
1690 arm11_setup_field(arm11
, 32, NULL
, &arm11
->device_id
, &idcode_field
);
1692 arm11_add_dr_scan_vc(1, &idcode_field
, TAP_DRPAUSE
);
1696 arm11_add_debug_SCAN_N(arm11
, 0x00, ARM11_TAP_DEFAULT
);
1698 arm11_add_IR(arm11
, ARM11_INTEST
, ARM11_TAP_DEFAULT
);
1700 struct scan_field chain0_fields
[2];
1702 arm11_setup_field(arm11
, 32, NULL
, &arm11
->didr
, chain0_fields
+ 0);
1703 arm11_setup_field(arm11
, 8, NULL
, &arm11
->implementor
, chain0_fields
+ 1);
1705 arm11_add_dr_scan_vc(ARRAY_SIZE(chain0_fields
), chain0_fields
, TAP_IDLE
);
1707 CHECK_RETVAL(jtag_execute_queue());
1709 switch (arm11
->device_id
& 0x0FFFF000)
1718 arm11
->arm
.core_type
= ARM_MODE_MON
;
1722 LOG_ERROR("'target arm11' expects IDCODE 0x*7B*7****");
1725 LOG_INFO("found %s", type
);
1727 arm11
->debug_version
= (arm11
->didr
>> 16) & 0x0F;
1729 if (arm11
->debug_version
!= ARM11_DEBUG_V6
&&
1730 arm11
->debug_version
!= ARM11_DEBUG_V61
)
1732 LOG_ERROR("Only ARMv6 v6 and v6.1 architectures supported.");
1736 arm11
->brp
= ((arm11
->didr
>> 24) & 0x0F) + 1;
1737 arm11
->wrp
= ((arm11
->didr
>> 28) & 0x0F) + 1;
1739 /** \todo TODO: reserve one brp slot if we allow breakpoints during step */
1740 arm11
->free_brps
= arm11
->brp
;
1741 arm11
->free_wrps
= arm11
->wrp
;
1743 LOG_DEBUG("IDCODE %08" PRIx32
" IMPLEMENTOR %02x DIDR %08" PRIx32
"",
1745 (int)(arm11
->implementor
),
1748 /* as a side-effect this reads DSCR and thus
1749 * clears the ARM11_DSCR_STICKY_PRECISE_DATA_ABORT / Sticky Precise Data Abort Flag
1750 * as suggested by the spec.
1753 retval
= arm11_check_init(arm11
, NULL
);
1754 if (retval
!= ERROR_OK
)
1757 /* ETM on ARM11 still uses original scanchain 6 access mode */
1758 if (arm11
->arm
.etm
&& !target_was_examined(target
)) {
1759 *register_get_last_cache_p(&target
->reg_cache
) =
1760 etm_build_reg_cache(target
, &arm11
->jtag_info
,
1762 retval
= etm_setup(target
);
1765 target_set_examined(target
);
1771 /** Load a register that is marked !valid in the register cache */
1772 static int arm11_get_reg(struct reg
*reg
)
1774 struct target
* target
= ((struct arm11_reg_state
*)reg
->arch_info
)->target
;
1776 if (target
->state
!= TARGET_HALTED
)
1778 LOG_WARNING("target was not halted");
1779 return ERROR_TARGET_NOT_HALTED
;
1782 /** \todo TODO: Check this. We assume that all registers are fetched at debug entry. */
1785 struct arm11_common
*arm11
= target_to_arm11(target
);
1786 const struct arm11_reg_defs
*arm11_reg_info
= arm11_reg_defs
+ ((struct arm11_reg_state
*)reg
->arch_info
)->def_index
;
1792 /** Change a value in the register cache */
1793 static int arm11_set_reg(struct reg
*reg
, uint8_t *buf
)
1795 struct target
*target
= ((struct arm11_reg_state
*)reg
->arch_info
)->target
;
1796 struct arm11_common
*arm11
= target_to_arm11(target
);
1797 // const struct arm11_reg_defs *arm11_reg_info = arm11_reg_defs + ((struct arm11_reg_state *)reg->arch_info)->def_index;
1799 arm11
->reg_values
[((struct arm11_reg_state
*)reg
->arch_info
)->def_index
] = buf_get_u32(buf
, 0, 32);
1806 static const struct reg_arch_type arm11_reg_type
= {
1807 .get
= arm11_get_reg
,
1808 .set
= arm11_set_reg
,
1811 static int arm11_build_reg_cache(struct target
*target
)
1813 struct arm11_common
*arm11
= target_to_arm11(target
);
1814 struct reg_cache
*cache
;
1815 struct reg
*reg_list
;
1816 struct arm11_reg_state
*arm11_reg_states
;
1818 cache
= calloc(1, sizeof *cache
);
1819 reg_list
= calloc(ARM11_REGCACHE_COUNT
, sizeof *reg_list
);
1820 arm11_reg_states
= calloc(ARM11_REGCACHE_COUNT
,
1821 sizeof *arm11_reg_states
);
1822 if (!cache
|| !reg_list
|| !arm11_reg_states
) {
1825 free(arm11_reg_states
);
1829 arm11
->reg_list
= reg_list
;
1831 /* Build the process context cache */
1832 cache
->name
= "arm11 registers";
1834 cache
->reg_list
= reg_list
;
1835 cache
->num_regs
= ARM11_REGCACHE_COUNT
;
1837 struct reg_cache
**cache_p
= register_get_last_cache_p(&target
->reg_cache
);
1840 arm11
->core_cache
= cache
;
1841 // armv7m->process_context = cache;
1845 /* Not very elegant assertion */
1846 if (ARM11_REGCACHE_COUNT
!= ARRAY_SIZE(arm11
->reg_values
) ||
1847 ARM11_REGCACHE_COUNT
!= ARRAY_SIZE(arm11_reg_defs
) ||
1848 ARM11_REGCACHE_COUNT
!= ARM11_RC_MAX
)
1850 LOG_ERROR("BUG: arm11->reg_values inconsistent (%d %u %u %d)",
1851 ARM11_REGCACHE_COUNT
,
1852 (unsigned) ARRAY_SIZE(arm11
->reg_values
),
1853 (unsigned) ARRAY_SIZE(arm11_reg_defs
),
1855 /* FIXME minimally, use a build_bug_on(X) mechanism;
1856 * runtime exit() here is bad!
1861 for (i
= 0; i
< ARM11_REGCACHE_COUNT
; i
++)
1863 struct reg
* r
= reg_list
+ i
;
1864 const struct arm11_reg_defs
* rd
= arm11_reg_defs
+ i
;
1865 struct arm11_reg_state
* rs
= arm11_reg_states
+ i
;
1869 r
->value
= (uint8_t *)(arm11
->reg_values
+ i
);
1872 r
->type
= &arm11_reg_type
;
1876 rs
->target
= target
;
1882 #define ARM11_BOOL_WRAPPER(name, print_name) \
1883 COMMAND_HANDLER(arm11_handle_bool_##name) \
1885 return CALL_COMMAND_HANDLER(handle_command_parse_bool, \
1886 &arm11_config_##name, print_name); \
1889 ARM11_BOOL_WRAPPER(memwrite_burst
, "memory write burst mode")
1890 ARM11_BOOL_WRAPPER(memwrite_error_fatal
, "fatal error mode for memory writes")
1891 ARM11_BOOL_WRAPPER(step_irq_enable
, "IRQs while stepping")
1892 ARM11_BOOL_WRAPPER(hardware_step
, "hardware single step")
1894 COMMAND_HANDLER(arm11_handle_vcr
)
1900 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], arm11_vcr
);
1903 return ERROR_COMMAND_SYNTAX_ERROR
;
1906 LOG_INFO("VCR 0x%08" PRIx32
"", arm11_vcr
);
1910 static const uint32_t arm11_coproc_instruction_limits
[] =
1912 15, /* coprocessor */
1917 0xFFFFFFFF, /* value */
1920 static int arm11_mrc_inner(struct target
*target
, int cpnum
,
1921 uint32_t op1
, uint32_t op2
, uint32_t CRn
, uint32_t CRm
,
1922 uint32_t *value
, bool read
)
1925 struct arm11_common
*arm11
= target_to_arm11(target
);
1927 if (target
->state
!= TARGET_HALTED
)
1929 LOG_ERROR("Target not halted");
1933 uint32_t instr
= 0xEE000010 |
1941 instr
|= 0x00100000;
1943 retval
= arm11_run_instr_data_prepare(arm11
);
1944 if (retval
!= ERROR_OK
)
1949 retval
= arm11_run_instr_data_from_core_via_r0(arm11
, instr
, value
);
1950 if (retval
!= ERROR_OK
)
1955 retval
= arm11_run_instr_data_to_core_via_r0(arm11
, instr
, *value
);
1956 if (retval
!= ERROR_OK
)
1960 return arm11_run_instr_data_finish(arm11
);
1963 static int arm11_mrc(struct target
*target
, int cpnum
,
1964 uint32_t op1
, uint32_t op2
, uint32_t CRn
, uint32_t CRm
, uint32_t *value
)
1966 return arm11_mrc_inner(target
, cpnum
, op1
, op2
, CRn
, CRm
, value
, true);
1969 static int arm11_mcr(struct target
*target
, int cpnum
,
1970 uint32_t op1
, uint32_t op2
, uint32_t CRn
, uint32_t CRm
, uint32_t value
)
1972 return arm11_mrc_inner(target
, cpnum
, op1
, op2
, CRn
, CRm
, &value
, false);
1975 static int arm11_register_commands(struct command_context
*cmd_ctx
)
1977 struct command
*top_cmd
, *mw_cmd
;
1979 armv4_5_register_commands(cmd_ctx
);
1981 top_cmd
= register_command(cmd_ctx
, NULL
, "arm11",
1982 NULL
, COMMAND_ANY
, NULL
);
1984 /* "hardware_step" is only here to check if the default
1985 * simulate + breakpoint implementation is broken.
1986 * TEMPORARY! NOT DOCUMENTED!
1988 register_command(cmd_ctx
, top_cmd
, "hardware_step",
1989 arm11_handle_bool_hardware_step
, COMMAND_ANY
,
1990 "DEBUG ONLY - Hardware single stepping"
1991 " (default: disabled)");
1993 mw_cmd
= register_command(cmd_ctx
, top_cmd
, "memwrite",
1994 NULL
, COMMAND_ANY
, NULL
);
1995 register_command(cmd_ctx
, mw_cmd
, "burst",
1996 arm11_handle_bool_memwrite_burst
, COMMAND_ANY
,
1997 "Enable/Disable non-standard but fast burst mode"
1998 " (default: enabled)");
1999 register_command(cmd_ctx
, mw_cmd
, "error_fatal",
2000 arm11_handle_bool_memwrite_error_fatal
, COMMAND_ANY
,
2001 "Terminate program if transfer error was found"
2002 " (default: enabled)");
2004 register_command(cmd_ctx
, top_cmd
, "step_irq_enable",
2005 arm11_handle_bool_step_irq_enable
, COMMAND_ANY
,
2006 "Enable interrupts while stepping"
2007 " (default: disabled)");
2008 register_command(cmd_ctx
, top_cmd
, "vcr",
2009 arm11_handle_vcr
, COMMAND_ANY
,
2010 "Control (Interrupt) Vector Catch Register");
2012 return etm_register_commands(cmd_ctx
);
2015 /** Holds methods for ARM11xx targets. */
2016 struct target_type arm11_target
= {
2020 .arch_state
= arm11_arch_state
,
2022 .target_request_data
= arm11_target_request_data
,
2025 .resume
= arm11_resume
,
2028 .assert_reset
= arm11_assert_reset
,
2029 .deassert_reset
= arm11_deassert_reset
,
2030 .soft_reset_halt
= arm11_soft_reset_halt
,
2032 .get_gdb_reg_list
= arm11_get_gdb_reg_list
,
2034 .read_memory
= arm11_read_memory
,
2035 .write_memory
= arm11_write_memory
,
2037 .bulk_write_memory
= arm11_bulk_write_memory
,
2039 .checksum_memory
= arm_checksum_memory
,
2040 .blank_check_memory
= arm_blank_check_memory
,
2042 .add_breakpoint
= arm11_add_breakpoint
,
2043 .remove_breakpoint
= arm11_remove_breakpoint
,
2044 .add_watchpoint
= arm11_add_watchpoint
,
2045 .remove_watchpoint
= arm11_remove_watchpoint
,
2047 .run_algorithm
= arm11_run_algorithm
,
2049 .register_commands
= arm11_register_commands
,
2050 .target_create
= arm11_target_create
,
2051 .init_target
= arm11_init_target
,
2052 .examine
= arm11_examine
,
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