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ARM11: partial support for standard ARM register interfaces.
[openocd.git] / src / target / arm11.c
1 /***************************************************************************
2 * Copyright (C) 2008 digenius technology GmbH. *
3 * Michael Bruck *
4 * *
5 * Copyright (C) 2008,2009 Oyvind Harboe oyvind.harboe@zylin.com *
6 * *
7 * Copyright (C) 2008 Georg Acher <acher@in.tum.de> *
8 * *
9 * This program is free software; you can redistribute it and/or modify *
10 * it under the terms of the GNU General Public License as published by *
11 * the Free Software Foundation; either version 2 of the License, or *
12 * (at your option) any later version. *
13 * *
14 * This program is distributed in the hope that it will be useful, *
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
17 * GNU General Public License for more details. *
18 * *
19 * You should have received a copy of the GNU General Public License *
20 * along with this program; if not, write to the *
21 * Free Software Foundation, Inc., *
22 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
23 ***************************************************************************/
24
25 #ifdef HAVE_CONFIG_H
26 #include "config.h"
27 #endif
28
29 #include "etm.h"
30 #include "breakpoints.h"
31 #include "arm11_dbgtap.h"
32 #include "arm_simulator.h"
33 #include "time_support.h"
34 #include "target_type.h"
35 #include "algorithm.h"
36 #include "register.h"
37
38
39 #if 0
40 #define _DEBUG_INSTRUCTION_EXECUTION_
41 #endif
42
43 static bool arm11_config_memwrite_burst = true;
44 static bool arm11_config_memwrite_error_fatal = true;
45 static uint32_t arm11_vcr = 0;
46 static bool arm11_config_step_irq_enable = false;
47 static bool arm11_config_hardware_step = false;
48
49 enum arm11_regtype
50 {
51 ARM11_REGISTER_CORE,
52 ARM11_REGISTER_CPSR,
53
54 ARM11_REGISTER_FX,
55 ARM11_REGISTER_FPS,
56
57 ARM11_REGISTER_FIQ,
58 ARM11_REGISTER_SVC,
59 ARM11_REGISTER_ABT,
60 ARM11_REGISTER_IRQ,
61 ARM11_REGISTER_UND,
62 ARM11_REGISTER_MON,
63
64 ARM11_REGISTER_SPSR_FIQ,
65 ARM11_REGISTER_SPSR_SVC,
66 ARM11_REGISTER_SPSR_ABT,
67 ARM11_REGISTER_SPSR_IRQ,
68 ARM11_REGISTER_SPSR_UND,
69 ARM11_REGISTER_SPSR_MON,
70
71 /* debug regs */
72 ARM11_REGISTER_DSCR,
73 ARM11_REGISTER_WDTR,
74 ARM11_REGISTER_RDTR,
75 };
76
77
78 struct arm11_reg_defs
79 {
80 char * name;
81 uint32_t num;
82 int gdb_num;
83 enum arm11_regtype type;
84 };
85
86 /* update arm11_regcache_ids when changing this */
87 static const struct arm11_reg_defs arm11_reg_defs[] =
88 {
89 {"r0", 0, 0, ARM11_REGISTER_CORE},
90 {"r1", 1, 1, ARM11_REGISTER_CORE},
91 {"r2", 2, 2, ARM11_REGISTER_CORE},
92 {"r3", 3, 3, ARM11_REGISTER_CORE},
93 {"r4", 4, 4, ARM11_REGISTER_CORE},
94 {"r5", 5, 5, ARM11_REGISTER_CORE},
95 {"r6", 6, 6, ARM11_REGISTER_CORE},
96 {"r7", 7, 7, ARM11_REGISTER_CORE},
97 {"r8", 8, 8, ARM11_REGISTER_CORE},
98 {"r9", 9, 9, ARM11_REGISTER_CORE},
99 {"r10", 10, 10, ARM11_REGISTER_CORE},
100 {"r11", 11, 11, ARM11_REGISTER_CORE},
101 {"r12", 12, 12, ARM11_REGISTER_CORE},
102 {"sp", 13, 13, ARM11_REGISTER_CORE},
103 {"lr", 14, 14, ARM11_REGISTER_CORE},
104 {"pc", 15, 15, ARM11_REGISTER_CORE},
105
106 {"cpsr", 0, 25, ARM11_REGISTER_CPSR},
107
108 /* Debug Registers */
109 {"dscr", 0, -1, ARM11_REGISTER_DSCR},
110 {"wdtr", 0, -1, ARM11_REGISTER_WDTR},
111 {"rdtr", 0, -1, ARM11_REGISTER_RDTR},
112 };
113
114 enum arm11_regcache_ids
115 {
116 ARM11_RC_R0,
117 ARM11_RC_RX = ARM11_RC_R0,
118
119 ARM11_RC_R1,
120 ARM11_RC_R2,
121 ARM11_RC_R3,
122 ARM11_RC_R4,
123 ARM11_RC_R5,
124 ARM11_RC_R6,
125 ARM11_RC_R7,
126 ARM11_RC_R8,
127 ARM11_RC_R9,
128 ARM11_RC_R10,
129 ARM11_RC_R11,
130 ARM11_RC_R12,
131 ARM11_RC_R13,
132 ARM11_RC_SP = ARM11_RC_R13,
133 ARM11_RC_R14,
134 ARM11_RC_LR = ARM11_RC_R14,
135 ARM11_RC_R15,
136 ARM11_RC_PC = ARM11_RC_R15,
137
138 ARM11_RC_CPSR,
139
140 ARM11_RC_DSCR,
141 ARM11_RC_WDTR,
142 ARM11_RC_RDTR,
143
144 ARM11_RC_MAX,
145 };
146
147 static int arm11_on_enter_debug_state(struct arm11_common *arm11);
148 static int arm11_step(struct target *target, int current,
149 uint32_t address, int handle_breakpoints);
150 /* helpers */
151 static int arm11_build_reg_cache(struct target *target);
152 static int arm11_set_reg(struct reg *reg, uint8_t *buf);
153 static int arm11_get_reg(struct reg *reg);
154
155
156 /** Check and if necessary take control of the system
157 *
158 * \param arm11 Target state variable.
159 * \param dscr If the current DSCR content is
160 * available a pointer to a word holding the
161 * DSCR can be passed. Otherwise use NULL.
162 */
163 static int arm11_check_init(struct arm11_common *arm11, uint32_t *dscr)
164 {
165 uint32_t dscr_local_tmp_copy;
166
167 if (!dscr)
168 {
169 dscr = &dscr_local_tmp_copy;
170
171 CHECK_RETVAL(arm11_read_DSCR(arm11, dscr));
172 }
173
174 if (!(*dscr & ARM11_DSCR_MODE_SELECT))
175 {
176 LOG_DEBUG("Bringing target into debug mode");
177
178 *dscr |= ARM11_DSCR_MODE_SELECT; /* Halt debug-mode */
179 arm11_write_DSCR(arm11, *dscr);
180
181 /* add further reset initialization here */
182
183 arm11->simulate_reset_on_next_halt = true;
184
185 if (*dscr & ARM11_DSCR_CORE_HALTED)
186 {
187 /** \todo TODO: this needs further scrutiny because
188 * arm11_on_enter_debug_state() never gets properly called.
189 * As a result we don't read the actual register states from
190 * the target.
191 */
192
193 arm11->target->state = TARGET_HALTED;
194 arm11->target->debug_reason = arm11_get_DSCR_debug_reason(*dscr);
195 }
196 else
197 {
198 arm11->target->state = TARGET_RUNNING;
199 arm11->target->debug_reason = DBG_REASON_NOTHALTED;
200 }
201
202 arm11_sc7_clear_vbw(arm11);
203 }
204
205 return ERROR_OK;
206 }
207
208
209
210 #define R(x) \
211 (arm11->reg_values[ARM11_RC_##x])
212
213 /** Save processor state.
214 *
215 * This is called when the HALT instruction has succeeded
216 * or on other occasions that stop the processor.
217 *
218 */
219 static int arm11_on_enter_debug_state(struct arm11_common *arm11)
220 {
221 int retval;
222
223 /* REVISIT entire cache should already be invalid !!! */
224 register_cache_invalidate(arm11->arm.core_cache);
225
226 for (size_t i = 0; i < ARRAY_SIZE(arm11->reg_values); i++)
227 {
228 arm11->reg_list[i].valid = 1;
229 arm11->reg_list[i].dirty = 0;
230 }
231
232 /* Save DSCR */
233 CHECK_RETVAL(arm11_read_DSCR(arm11, &R(DSCR)));
234
235 /* Save wDTR */
236
237 if (R(DSCR) & ARM11_DSCR_WDTR_FULL)
238 {
239 arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
240
241 arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
242
243 struct scan_field chain5_fields[3];
244
245 arm11_setup_field(arm11, 32, NULL, &R(WDTR), chain5_fields + 0);
246 arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 1);
247 arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 2);
248
249 arm11_add_dr_scan_vc(ARRAY_SIZE(chain5_fields), chain5_fields, TAP_DRPAUSE);
250 }
251 else
252 {
253 arm11->reg_list[ARM11_RC_WDTR].valid = 0;
254 }
255
256
257 /* DSCR: set ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE */
258 /* ARM1176 spec says this is needed only for wDTR/rDTR's "ITR mode", but not to issue ITRs
259 ARM1136 seems to require this to issue ITR's as well */
260
261 uint32_t new_dscr = R(DSCR) | ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE;
262
263 /* this executes JTAG queue: */
264
265 arm11_write_DSCR(arm11, new_dscr);
266
267
268 /* From the spec:
269 Before executing any instruction in debug state you have to drain the write buffer.
270 This ensures that no imprecise Data Aborts can return at a later point:*/
271
272 /** \todo TODO: Test drain write buffer. */
273
274 #if 0
275 while (1)
276 {
277 /* MRC p14,0,R0,c5,c10,0 */
278 // arm11_run_instr_no_data1(arm11, /*0xee150e1a*/0xe320f000);
279
280 /* mcr 15, 0, r0, cr7, cr10, {4} */
281 arm11_run_instr_no_data1(arm11, 0xee070f9a);
282
283 uint32_t dscr = arm11_read_DSCR(arm11);
284
285 LOG_DEBUG("DRAIN, DSCR %08x", dscr);
286
287 if (dscr & ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT)
288 {
289 arm11_run_instr_no_data1(arm11, 0xe320f000);
290
291 dscr = arm11_read_DSCR(arm11);
292
293 LOG_DEBUG("DRAIN, DSCR %08x (DONE)", dscr);
294
295 break;
296 }
297 }
298 #endif
299
300 retval = arm_dpm_read_current_registers(&arm11->dpm);
301 if (retval != ERROR_OK)
302 LOG_ERROR("DPM REG READ -- fail %d", retval);
303
304 retval = arm11_run_instr_data_prepare(arm11);
305 if (retval != ERROR_OK)
306 return retval;
307
308 /* save r0 - r14 */
309
310 /** \todo TODO: handle other mode registers */
311
312 for (size_t i = 0; i < 15; i++)
313 {
314 /* MCR p14,0,R?,c0,c5,0 */
315 retval = arm11_run_instr_data_from_core(arm11, 0xEE000E15 | (i << 12), &R(RX + i), 1);
316 if (retval != ERROR_OK)
317 return retval;
318 }
319
320 /* save rDTR */
321
322 /* check rDTRfull in DSCR */
323
324 if (R(DSCR) & ARM11_DSCR_RDTR_FULL)
325 {
326 /* MRC p14,0,R0,c0,c5,0 (move rDTR -> r0 (-> wDTR -> local var)) */
327 retval = arm11_run_instr_data_from_core_via_r0(arm11, 0xEE100E15, &R(RDTR));
328 if (retval != ERROR_OK)
329 return retval;
330 }
331 else
332 {
333 arm11->reg_list[ARM11_RC_RDTR].valid = 0;
334 }
335
336 /* save CPSR */
337
338 /* MRS r0,CPSR (move CPSR -> r0 (-> wDTR -> local var)) */
339 retval = arm11_run_instr_data_from_core_via_r0(arm11, 0xE10F0000, &R(CPSR));
340 if (retval != ERROR_OK)
341 return retval;
342
343 /* save PC */
344
345 /* MOV R0,PC (move PC -> r0 (-> wDTR -> local var)) */
346 retval = arm11_run_instr_data_from_core_via_r0(arm11, 0xE1A0000F, &R(PC));
347 if (retval != ERROR_OK)
348 return retval;
349
350 /* adjust PC depending on ARM state */
351
352 if (R(CPSR) & ARM11_CPSR_J) /* Java state */
353 {
354 arm11->reg_values[ARM11_RC_PC] -= 0;
355 }
356 else if (R(CPSR) & ARM11_CPSR_T) /* Thumb state */
357 {
358 arm11->reg_values[ARM11_RC_PC] -= 4;
359 }
360 else /* ARM state */
361 {
362 arm11->reg_values[ARM11_RC_PC] -= 8;
363 }
364
365 if (arm11->simulate_reset_on_next_halt)
366 {
367 arm11->simulate_reset_on_next_halt = false;
368
369 LOG_DEBUG("Reset c1 Control Register");
370
371 /* Write 0 (reset value) to Control register 0 to disable MMU/Cache etc. */
372
373 /* MCR p15,0,R0,c1,c0,0 */
374 retval = arm11_run_instr_data_to_core_via_r0(arm11, 0xee010f10, 0);
375 if (retval != ERROR_OK)
376 return retval;
377
378 }
379
380 retval = arm11_run_instr_data_finish(arm11);
381 if (retval != ERROR_OK)
382 return retval;
383
384 return ERROR_OK;
385 }
386
387 /** Restore processor state
388 *
389 * This is called in preparation for the RESTART function.
390 *
391 */
392 static int arm11_leave_debug_state(struct arm11_common *arm11)
393 {
394 int retval;
395
396 retval = arm11_run_instr_data_prepare(arm11);
397 if (retval != ERROR_OK)
398 return retval;
399
400 /** \todo TODO: handle other mode registers */
401
402 /* restore R1 - R14 */
403
404 for (unsigned i = 1; i < 15; i++)
405 {
406 if (!arm11->reg_list[ARM11_RC_RX + i].dirty)
407 continue;
408
409 /* MRC p14,0,r?,c0,c5,0 */
410 arm11_run_instr_data_to_core1(arm11,
411 0xee100e15 | (i << 12), R(RX + i));
412
413 // LOG_DEBUG("RESTORE R%u %08x", i, R(RX + i));
414 }
415
416 retval = arm11_run_instr_data_finish(arm11);
417 if (retval != ERROR_OK)
418 return retval;
419
420 /* spec says clear wDTR and rDTR; we assume they are clear as
421 otherwise our programming would be sloppy */
422 {
423 uint32_t DSCR;
424
425 CHECK_RETVAL(arm11_read_DSCR(arm11, &DSCR));
426
427 if (DSCR & (ARM11_DSCR_RDTR_FULL | ARM11_DSCR_WDTR_FULL))
428 {
429 /*
430 The wDTR/rDTR two registers that are used to send/receive data to/from
431 the core in tandem with corresponding instruction codes that are
432 written into the core. The RDTR FULL/WDTR FULL flag indicates that the
433 registers hold data that was written by one side (CPU or JTAG) and not
434 read out by the other side.
435 */
436 LOG_ERROR("wDTR/rDTR inconsistent (DSCR %08" PRIx32 ")", DSCR);
437 return ERROR_FAIL;
438 }
439 }
440
441 /* DEBUG for now, trust "new" code only for shadowed registers */
442 retval = arm_dpm_write_dirty_registers(&arm11->dpm);
443
444 retval = arm11_run_instr_data_prepare(arm11);
445 if (retval != ERROR_OK)
446 return retval;
447
448 /* restore original wDTR */
449
450 if ((R(DSCR) & ARM11_DSCR_WDTR_FULL) || arm11->reg_list[ARM11_RC_WDTR].dirty)
451 {
452 /* MCR p14,0,R0,c0,c5,0 */
453 retval = arm11_run_instr_data_to_core_via_r0(arm11, 0xee000e15, R(WDTR));
454 if (retval != ERROR_OK)
455 return retval;
456 }
457
458 /* restore CPSR */
459
460 /* MSR CPSR,R0*/
461 retval = arm11_run_instr_data_to_core_via_r0(arm11, 0xe129f000, R(CPSR));
462 if (retval != ERROR_OK)
463 return retval;
464
465
466 /* restore PC */
467
468 /* MOV PC,R0 */
469 retval = arm11_run_instr_data_to_core_via_r0(arm11, 0xe1a0f000, R(PC));
470 if (retval != ERROR_OK)
471 return retval;
472
473
474 /* restore R0 */
475
476 /* MRC p14,0,r0,c0,c5,0 */
477 arm11_run_instr_data_to_core1(arm11, 0xee100e15, R(R0));
478
479 retval = arm11_run_instr_data_finish(arm11);
480 if (retval != ERROR_OK)
481 return retval;
482
483 /* DEBUG use this when "new" code is really managing core registers */
484 // retval = arm_dpm_write_dirty_registers(&arm11->dpm);
485
486 register_cache_invalidate(arm11->arm.core_cache);
487
488 /* restore DSCR */
489
490 arm11_write_DSCR(arm11, R(DSCR));
491
492 /* restore rDTR */
493
494 if (R(DSCR) & ARM11_DSCR_RDTR_FULL || arm11->reg_list[ARM11_RC_RDTR].dirty)
495 {
496 arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
497
498 arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT);
499
500 struct scan_field chain5_fields[3];
501
502 uint8_t Ready = 0; /* ignored */
503 uint8_t Valid = 0; /* ignored */
504
505 arm11_setup_field(arm11, 32, &R(RDTR), NULL, chain5_fields + 0);
506 arm11_setup_field(arm11, 1, &Ready, NULL, chain5_fields + 1);
507 arm11_setup_field(arm11, 1, &Valid, NULL, chain5_fields + 2);
508
509 arm11_add_dr_scan_vc(ARRAY_SIZE(chain5_fields), chain5_fields, TAP_DRPAUSE);
510 }
511
512 return ERROR_OK;
513 }
514
515 /* poll current target status */
516 static int arm11_poll(struct target *target)
517 {
518 int retval;
519 struct arm11_common *arm11 = target_to_arm11(target);
520 uint32_t dscr;
521
522 CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
523
524 LOG_DEBUG("DSCR %08" PRIx32 "", dscr);
525
526 CHECK_RETVAL(arm11_check_init(arm11, &dscr));
527
528 if (dscr & ARM11_DSCR_CORE_HALTED)
529 {
530 if (target->state != TARGET_HALTED)
531 {
532 enum target_state old_state = target->state;
533
534 LOG_DEBUG("enter TARGET_HALTED");
535 target->state = TARGET_HALTED;
536 target->debug_reason = arm11_get_DSCR_debug_reason(dscr);
537 retval = arm11_on_enter_debug_state(arm11);
538 if (retval != ERROR_OK)
539 return retval;
540
541 target_call_event_callbacks(target,
542 old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED);
543 }
544 }
545 else
546 {
547 if (target->state != TARGET_RUNNING && target->state != TARGET_DEBUG_RUNNING)
548 {
549 LOG_DEBUG("enter TARGET_RUNNING");
550 target->state = TARGET_RUNNING;
551 target->debug_reason = DBG_REASON_NOTHALTED;
552 }
553 }
554
555 return ERROR_OK;
556 }
557 /* architecture specific status reply */
558 static int arm11_arch_state(struct target *target)
559 {
560 int retval;
561
562 retval = armv4_5_arch_state(target);
563
564 /* REVISIT also display ARM11-specific MMU and cache status ... */
565
566 return retval;
567 }
568
569 /* target request support */
570 static int arm11_target_request_data(struct target *target,
571 uint32_t size, uint8_t *buffer)
572 {
573 LOG_WARNING("Not implemented: %s", __func__);
574
575 return ERROR_FAIL;
576 }
577
578 /* target execution control */
579 static int arm11_halt(struct target *target)
580 {
581 struct arm11_common *arm11 = target_to_arm11(target);
582
583 LOG_DEBUG("target->state: %s",
584 target_state_name(target));
585
586 if (target->state == TARGET_UNKNOWN)
587 {
588 arm11->simulate_reset_on_next_halt = true;
589 }
590
591 if (target->state == TARGET_HALTED)
592 {
593 LOG_DEBUG("target was already halted");
594 return ERROR_OK;
595 }
596
597 arm11_add_IR(arm11, ARM11_HALT, TAP_IDLE);
598
599 CHECK_RETVAL(jtag_execute_queue());
600
601 uint32_t dscr;
602
603 int i = 0;
604 while (1)
605 {
606 CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
607
608 if (dscr & ARM11_DSCR_CORE_HALTED)
609 break;
610
611
612 long long then = 0;
613 if (i == 1000)
614 {
615 then = timeval_ms();
616 }
617 if (i >= 1000)
618 {
619 if ((timeval_ms()-then) > 1000)
620 {
621 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
622 return ERROR_FAIL;
623 }
624 }
625 i++;
626 }
627
628 arm11_on_enter_debug_state(arm11);
629
630 enum target_state old_state = target->state;
631
632 target->state = TARGET_HALTED;
633 target->debug_reason = arm11_get_DSCR_debug_reason(dscr);
634
635 CHECK_RETVAL(
636 target_call_event_callbacks(target,
637 old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED));
638
639 return ERROR_OK;
640 }
641
642 static int arm11_resume(struct target *target, int current,
643 uint32_t address, int handle_breakpoints, int debug_execution)
644 {
645 // LOG_DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d",
646 // current, address, handle_breakpoints, debug_execution);
647
648 struct arm11_common *arm11 = target_to_arm11(target);
649
650 LOG_DEBUG("target->state: %s",
651 target_state_name(target));
652
653
654 if (target->state != TARGET_HALTED)
655 {
656 LOG_ERROR("Target not halted");
657 return ERROR_TARGET_NOT_HALTED;
658 }
659
660 if (!current)
661 R(PC) = address;
662
663 LOG_DEBUG("RESUME PC %08" PRIx32 "%s", R(PC), !current ? "!" : "");
664
665 /* clear breakpoints/watchpoints and VCR*/
666 arm11_sc7_clear_vbw(arm11);
667
668 /* Set up breakpoints */
669 if (!debug_execution)
670 {
671 /* check if one matches PC and step over it if necessary */
672
673 struct breakpoint * bp;
674
675 for (bp = target->breakpoints; bp; bp = bp->next)
676 {
677 if (bp->address == R(PC))
678 {
679 LOG_DEBUG("must step over %08" PRIx32 "", bp->address);
680 arm11_step(target, 1, 0, 0);
681 break;
682 }
683 }
684
685 /* set all breakpoints */
686
687 unsigned brp_num = 0;
688
689 for (bp = target->breakpoints; bp; bp = bp->next)
690 {
691 struct arm11_sc7_action brp[2];
692
693 brp[0].write = 1;
694 brp[0].address = ARM11_SC7_BVR0 + brp_num;
695 brp[0].value = bp->address;
696 brp[1].write = 1;
697 brp[1].address = ARM11_SC7_BCR0 + brp_num;
698 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
699
700 arm11_sc7_run(arm11, brp, ARRAY_SIZE(brp));
701
702 LOG_DEBUG("Add BP %d at %08" PRIx32, brp_num,
703 bp->address);
704
705 brp_num++;
706 }
707
708 arm11_sc7_set_vcr(arm11, arm11_vcr);
709 }
710
711 arm11_leave_debug_state(arm11);
712
713 arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
714
715 CHECK_RETVAL(jtag_execute_queue());
716
717 int i = 0;
718 while (1)
719 {
720 uint32_t dscr;
721
722 CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
723
724 LOG_DEBUG("DSCR %08" PRIx32 "", dscr);
725
726 if (dscr & ARM11_DSCR_CORE_RESTARTED)
727 break;
728
729
730 long long then = 0;
731 if (i == 1000)
732 {
733 then = timeval_ms();
734 }
735 if (i >= 1000)
736 {
737 if ((timeval_ms()-then) > 1000)
738 {
739 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
740 return ERROR_FAIL;
741 }
742 }
743 i++;
744 }
745
746 if (!debug_execution)
747 {
748 target->state = TARGET_RUNNING;
749 target->debug_reason = DBG_REASON_NOTHALTED;
750
751 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
752 }
753 else
754 {
755 target->state = TARGET_DEBUG_RUNNING;
756 target->debug_reason = DBG_REASON_NOTHALTED;
757
758 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
759 }
760
761 return ERROR_OK;
762 }
763
764
765 static int armv4_5_to_arm11(int reg)
766 {
767 if (reg < 16)
768 return reg;
769 switch (reg)
770 {
771 case ARMV4_5_CPSR:
772 return ARM11_RC_CPSR;
773 case 16:
774 /* FIX!!! handle thumb better! */
775 return ARM11_RC_CPSR;
776 default:
777 LOG_ERROR("BUG: register translation from armv4_5 to arm11 not supported %d", reg);
778 exit(-1);
779 }
780 }
781
782
783 static uint32_t arm11_sim_get_reg(struct arm_sim_interface *sim, int reg)
784 {
785 struct arm11_common * arm11 = (struct arm11_common *)sim->user_data;
786
787 reg=armv4_5_to_arm11(reg);
788
789 return buf_get_u32(arm11->reg_list[reg].value, 0, 32);
790 }
791
792 static void arm11_sim_set_reg(struct arm_sim_interface *sim,
793 int reg, uint32_t value)
794 {
795 struct arm11_common * arm11 = (struct arm11_common *)sim->user_data;
796
797 reg=armv4_5_to_arm11(reg);
798
799 buf_set_u32(arm11->reg_list[reg].value, 0, 32, value);
800 }
801
802 static uint32_t arm11_sim_get_cpsr(struct arm_sim_interface *sim,
803 int pos, int bits)
804 {
805 struct arm11_common * arm11 = (struct arm11_common *)sim->user_data;
806
807 return buf_get_u32(arm11->reg_list[ARM11_RC_CPSR].value, pos, bits);
808 }
809
810 static enum armv4_5_state arm11_sim_get_state(struct arm_sim_interface *sim)
811 {
812 // struct arm11_common * arm11 = (struct arm11_common *)sim->user_data;
813
814 /* FIX!!!! we should implement thumb for arm11 */
815 return ARMV4_5_STATE_ARM;
816 }
817
818 static void arm11_sim_set_state(struct arm_sim_interface *sim,
819 enum armv4_5_state mode)
820 {
821 // struct arm11_common * arm11 = (struct arm11_common *)sim->user_data;
822
823 /* FIX!!!! we should implement thumb for arm11 */
824 LOG_ERROR("Not implemented: %s", __func__);
825 }
826
827
828 static enum armv4_5_mode arm11_sim_get_mode(struct arm_sim_interface *sim)
829 {
830 //struct arm11_common * arm11 = (struct arm11_common *)sim->user_data;
831
832 /* FIX!!!! we should implement something that returns the current mode here!!! */
833 return ARMV4_5_MODE_USR;
834 }
835
836 static int arm11_simulate_step(struct target *target, uint32_t *dry_run_pc)
837 {
838 struct arm_sim_interface sim;
839
840 sim.user_data=target->arch_info;
841 sim.get_reg=&arm11_sim_get_reg;
842 sim.set_reg=&arm11_sim_set_reg;
843 sim.get_reg_mode=&arm11_sim_get_reg;
844 sim.set_reg_mode=&arm11_sim_set_reg;
845 sim.get_cpsr=&arm11_sim_get_cpsr;
846 sim.get_mode=&arm11_sim_get_mode;
847 sim.get_state=&arm11_sim_get_state;
848 sim.set_state=&arm11_sim_set_state;
849
850 return arm_simulate_step_core(target, dry_run_pc, &sim);
851
852 }
853
854 static int arm11_step(struct target *target, int current,
855 uint32_t address, int handle_breakpoints)
856 {
857 LOG_DEBUG("target->state: %s",
858 target_state_name(target));
859
860 if (target->state != TARGET_HALTED)
861 {
862 LOG_WARNING("target was not halted");
863 return ERROR_TARGET_NOT_HALTED;
864 }
865
866 struct arm11_common *arm11 = target_to_arm11(target);
867
868 if (!current)
869 R(PC) = address;
870
871 LOG_DEBUG("STEP PC %08" PRIx32 "%s", R(PC), !current ? "!" : "");
872
873
874 /** \todo TODO: Thumb not supported here */
875
876 uint32_t next_instruction;
877
878 CHECK_RETVAL(arm11_read_memory_word(arm11, R(PC), &next_instruction));
879
880 /* skip over BKPT */
881 if ((next_instruction & 0xFFF00070) == 0xe1200070)
882 {
883 R(PC) += 4;
884 arm11->reg_list[ARM11_RC_PC].valid = 1;
885 arm11->reg_list[ARM11_RC_PC].dirty = 0;
886 LOG_DEBUG("Skipping BKPT");
887 }
888 /* skip over Wait for interrupt / Standby */
889 /* mcr 15, 0, r?, cr7, cr0, {4} */
890 else if ((next_instruction & 0xFFFF0FFF) == 0xee070f90)
891 {
892 R(PC) += 4;
893 arm11->reg_list[ARM11_RC_PC].valid = 1;
894 arm11->reg_list[ARM11_RC_PC].dirty = 0;
895 LOG_DEBUG("Skipping WFI");
896 }
897 /* ignore B to self */
898 else if ((next_instruction & 0xFEFFFFFF) == 0xeafffffe)
899 {
900 LOG_DEBUG("Not stepping jump to self");
901 }
902 else
903 {
904 /** \todo TODO: check if break-/watchpoints make any sense at all in combination
905 * with this. */
906
907 /** \todo TODO: check if disabling IRQs might be a good idea here. Alternatively
908 * the VCR might be something worth looking into. */
909
910
911 /* Set up breakpoint for stepping */
912
913 struct arm11_sc7_action brp[2];
914
915 brp[0].write = 1;
916 brp[0].address = ARM11_SC7_BVR0;
917 brp[1].write = 1;
918 brp[1].address = ARM11_SC7_BCR0;
919
920 if (arm11_config_hardware_step)
921 {
922 /* hardware single stepping be used if possible or is it better to
923 * always use the same code path? Hardware single stepping is not supported
924 * on all hardware
925 */
926 brp[0].value = R(PC);
927 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (2 << 21);
928 } else
929 {
930 /* sets a breakpoint on the next PC(calculated by simulation),
931 */
932 uint32_t next_pc;
933 int retval;
934 retval = arm11_simulate_step(target, &next_pc);
935 if (retval != ERROR_OK)
936 return retval;
937
938 brp[0].value = next_pc;
939 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
940 }
941
942 CHECK_RETVAL(arm11_sc7_run(arm11, brp, ARRAY_SIZE(brp)));
943
944 /* resume */
945
946
947 if (arm11_config_step_irq_enable)
948 R(DSCR) &= ~ARM11_DSCR_INTERRUPTS_DISABLE; /* should be redundant */
949 else
950 R(DSCR) |= ARM11_DSCR_INTERRUPTS_DISABLE;
951
952
953 CHECK_RETVAL(arm11_leave_debug_state(arm11));
954
955 arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
956
957 CHECK_RETVAL(jtag_execute_queue());
958
959 /* wait for halt */
960 int i = 0;
961 while (1)
962 {
963 uint32_t dscr;
964
965 CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
966
967 LOG_DEBUG("DSCR %08" PRIx32 "e", dscr);
968
969 if ((dscr & (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED)) ==
970 (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED))
971 break;
972
973 long long then = 0;
974 if (i == 1000)
975 {
976 then = timeval_ms();
977 }
978 if (i >= 1000)
979 {
980 if ((timeval_ms()-then) > 1000)
981 {
982 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
983 return ERROR_FAIL;
984 }
985 }
986 i++;
987 }
988
989 /* clear breakpoint */
990 arm11_sc7_clear_vbw(arm11);
991
992 /* save state */
993 CHECK_RETVAL(arm11_on_enter_debug_state(arm11));
994
995 /* restore default state */
996 R(DSCR) &= ~ARM11_DSCR_INTERRUPTS_DISABLE;
997
998 }
999
1000 // target->state = TARGET_HALTED;
1001 target->debug_reason = DBG_REASON_SINGLESTEP;
1002
1003 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_HALTED));
1004
1005 return ERROR_OK;
1006 }
1007
1008 static int arm11_assert_reset(struct target *target)
1009 {
1010 int retval;
1011 struct arm11_common *arm11 = target_to_arm11(target);
1012
1013 retval = arm11_check_init(arm11, NULL);
1014 if (retval != ERROR_OK)
1015 return retval;
1016
1017 target->state = TARGET_UNKNOWN;
1018
1019 /* we would very much like to reset into the halted, state,
1020 * but resetting and halting is second best... */
1021 if (target->reset_halt)
1022 {
1023 CHECK_RETVAL(target_halt(target));
1024 }
1025
1026
1027 /* srst is funny. We can not do *anything* else while it's asserted
1028 * and it has unkonwn side effects. Make sure no other code runs
1029 * meanwhile.
1030 *
1031 * Code below assumes srst:
1032 *
1033 * - Causes power-on-reset (but of what parts of the system?). Bug
1034 * in arm11?
1035 *
1036 * - Messes us TAP state without asserting trst.
1037 *
1038 * - There is another bug in the arm11 core. When you generate an access to
1039 * external logic (for example ddr controller via AHB bus) and that block
1040 * is not configured (perhaps it is still held in reset), that transaction
1041 * will never complete. This will hang arm11 core but it will also hang
1042 * JTAG controller. Nothing, short of srst assertion will bring it out of
1043 * this.
1044 *
1045 * Mysteries:
1046 *
1047 * - What should the PC be after an srst reset when starting in the halted
1048 * state?
1049 */
1050
1051 jtag_add_reset(0, 1);
1052 jtag_add_reset(0, 0);
1053
1054 /* How long do we have to wait? */
1055 jtag_add_sleep(5000);
1056
1057 /* un-mess up TAP state */
1058 jtag_add_tlr();
1059
1060 retval = jtag_execute_queue();
1061 if (retval != ERROR_OK)
1062 {
1063 return retval;
1064 }
1065
1066 return ERROR_OK;
1067 }
1068
1069 static int arm11_deassert_reset(struct target *target)
1070 {
1071 return ERROR_OK;
1072 }
1073
1074 static int arm11_soft_reset_halt(struct target *target)
1075 {
1076 LOG_WARNING("Not implemented: %s", __func__);
1077
1078 return ERROR_FAIL;
1079 }
1080
1081 /* target memory access
1082 * size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
1083 * count: number of items of <size>
1084 *
1085 * arm11_config_memrw_no_increment - in the future we may want to be able
1086 * to read/write a range of data to a "port". a "port" is an action on
1087 * read memory address for some peripheral.
1088 */
1089 static int arm11_read_memory_inner(struct target *target,
1090 uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer,
1091 bool arm11_config_memrw_no_increment)
1092 {
1093 /** \todo TODO: check if buffer cast to uint32_t* and uint16_t* might cause alignment problems */
1094 int retval;
1095
1096 if (target->state != TARGET_HALTED)
1097 {
1098 LOG_WARNING("target was not halted");
1099 return ERROR_TARGET_NOT_HALTED;
1100 }
1101
1102 LOG_DEBUG("ADDR %08" PRIx32 " SIZE %08" PRIx32 " COUNT %08" PRIx32 "", address, size, count);
1103
1104 struct arm11_common *arm11 = target_to_arm11(target);
1105
1106 retval = arm11_run_instr_data_prepare(arm11);
1107 if (retval != ERROR_OK)
1108 return retval;
1109
1110 /* MRC p14,0,r0,c0,c5,0 */
1111 retval = arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
1112 if (retval != ERROR_OK)
1113 return retval;
1114
1115 switch (size)
1116 {
1117 case 1:
1118 /** \todo TODO: check if dirty is the right choice to force a rewrite on arm11_resume() */
1119 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1120
1121 for (size_t i = 0; i < count; i++)
1122 {
1123 /* ldrb r1, [r0], #1 */
1124 /* ldrb r1, [r0] */
1125 arm11_run_instr_no_data1(arm11,
1126 !arm11_config_memrw_no_increment ? 0xe4d01001 : 0xe5d01000);
1127
1128 uint32_t res;
1129 /* MCR p14,0,R1,c0,c5,0 */
1130 arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
1131
1132 *buffer++ = res;
1133 }
1134
1135 break;
1136
1137 case 2:
1138 {
1139 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1140
1141 for (size_t i = 0; i < count; i++)
1142 {
1143 /* ldrh r1, [r0], #2 */
1144 arm11_run_instr_no_data1(arm11,
1145 !arm11_config_memrw_no_increment ? 0xe0d010b2 : 0xe1d010b0);
1146
1147 uint32_t res;
1148
1149 /* MCR p14,0,R1,c0,c5,0 */
1150 arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
1151
1152 uint16_t svalue = res;
1153 memcpy(buffer + i * sizeof(uint16_t), &svalue, sizeof(uint16_t));
1154 }
1155
1156 break;
1157 }
1158
1159 case 4:
1160 {
1161 uint32_t instr = !arm11_config_memrw_no_increment ? 0xecb05e01 : 0xed905e00;
1162 /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
1163 uint32_t *words = (uint32_t *)buffer;
1164
1165 /* LDC p14,c5,[R0],#4 */
1166 /* LDC p14,c5,[R0] */
1167 arm11_run_instr_data_from_core(arm11, instr, words, count);
1168 break;
1169 }
1170 }
1171
1172 return arm11_run_instr_data_finish(arm11);
1173 }
1174
1175 static int arm11_read_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
1176 {
1177 return arm11_read_memory_inner(target, address, size, count, buffer, false);
1178 }
1179
1180 /*
1181 * arm11_config_memrw_no_increment - in the future we may want to be able
1182 * to read/write a range of data to a "port". a "port" is an action on
1183 * read memory address for some peripheral.
1184 */
1185 static int arm11_write_memory_inner(struct target *target,
1186 uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer,
1187 bool arm11_config_memrw_no_increment)
1188 {
1189 int retval;
1190
1191 if (target->state != TARGET_HALTED)
1192 {
1193 LOG_WARNING("target was not halted");
1194 return ERROR_TARGET_NOT_HALTED;
1195 }
1196
1197 LOG_DEBUG("ADDR %08" PRIx32 " SIZE %08" PRIx32 " COUNT %08" PRIx32 "", address, size, count);
1198
1199 struct arm11_common *arm11 = target_to_arm11(target);
1200
1201 retval = arm11_run_instr_data_prepare(arm11);
1202 if (retval != ERROR_OK)
1203 return retval;
1204
1205 /* MRC p14,0,r0,c0,c5,0 */
1206 retval = arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
1207 if (retval != ERROR_OK)
1208 return retval;
1209
1210 /* burst writes are not used for single words as those may well be
1211 * reset init script writes.
1212 *
1213 * The other advantage is that as burst writes are default, we'll
1214 * now exercise both burst and non-burst code paths with the
1215 * default settings, increasing code coverage.
1216 */
1217 bool burst = arm11_config_memwrite_burst && (count > 1);
1218
1219 switch (size)
1220 {
1221 case 1:
1222 {
1223 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1224
1225 for (size_t i = 0; i < count; i++)
1226 {
1227 /* MRC p14,0,r1,c0,c5,0 */
1228 retval = arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buffer++);
1229 if (retval != ERROR_OK)
1230 return retval;
1231
1232 /* strb r1, [r0], #1 */
1233 /* strb r1, [r0] */
1234 retval = arm11_run_instr_no_data1(arm11,
1235 !arm11_config_memrw_no_increment ? 0xe4c01001 : 0xe5c01000);
1236 if (retval != ERROR_OK)
1237 return retval;
1238 }
1239
1240 break;
1241 }
1242
1243 case 2:
1244 {
1245 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1246
1247 for (size_t i = 0; i < count; i++)
1248 {
1249 uint16_t value;
1250 memcpy(&value, buffer + i * sizeof(uint16_t), sizeof(uint16_t));
1251
1252 /* MRC p14,0,r1,c0,c5,0 */
1253 retval = arm11_run_instr_data_to_core1(arm11, 0xee101e15, value);
1254 if (retval != ERROR_OK)
1255 return retval;
1256
1257 /* strh r1, [r0], #2 */
1258 /* strh r1, [r0] */
1259 retval = arm11_run_instr_no_data1(arm11,
1260 !arm11_config_memrw_no_increment ? 0xe0c010b2 : 0xe1c010b0);
1261 if (retval != ERROR_OK)
1262 return retval;
1263 }
1264
1265 break;
1266 }
1267
1268 case 4: {
1269 uint32_t instr = !arm11_config_memrw_no_increment ? 0xeca05e01 : 0xed805e00;
1270
1271 /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
1272 uint32_t *words = (uint32_t*)buffer;
1273
1274 if (!burst)
1275 {
1276 /* STC p14,c5,[R0],#4 */
1277 /* STC p14,c5,[R0]*/
1278 retval = arm11_run_instr_data_to_core(arm11, instr, words, count);
1279 if (retval != ERROR_OK)
1280 return retval;
1281 }
1282 else
1283 {
1284 /* STC p14,c5,[R0],#4 */
1285 /* STC p14,c5,[R0]*/
1286 retval = arm11_run_instr_data_to_core_noack(arm11, instr, words, count);
1287 if (retval != ERROR_OK)
1288 return retval;
1289 }
1290
1291 break;
1292 }
1293 }
1294
1295 /* r0 verification */
1296 if (!arm11_config_memrw_no_increment)
1297 {
1298 uint32_t r0;
1299
1300 /* MCR p14,0,R0,c0,c5,0 */
1301 retval = arm11_run_instr_data_from_core(arm11, 0xEE000E15, &r0, 1);
1302 if (retval != ERROR_OK)
1303 return retval;
1304
1305 if (address + size * count != r0)
1306 {
1307 LOG_ERROR("Data transfer failed. Expected end "
1308 "address 0x%08x, got 0x%08x",
1309 (unsigned) (address + size * count),
1310 (unsigned) r0);
1311
1312 if (burst)
1313 LOG_ERROR("use 'arm11 memwrite burst disable' to disable fast burst mode");
1314
1315 if (arm11_config_memwrite_error_fatal)
1316 return ERROR_FAIL;
1317 }
1318 }
1319
1320 return arm11_run_instr_data_finish(arm11);
1321 }
1322
1323 static int arm11_write_memory(struct target *target,
1324 uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
1325 {
1326 return arm11_write_memory_inner(target, address, size, count, buffer, false);
1327 }
1328
1329 /* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
1330 static int arm11_bulk_write_memory(struct target *target,
1331 uint32_t address, uint32_t count, uint8_t *buffer)
1332 {
1333 if (target->state != TARGET_HALTED)
1334 {
1335 LOG_WARNING("target was not halted");
1336 return ERROR_TARGET_NOT_HALTED;
1337 }
1338
1339 return arm11_write_memory(target, address, 4, count, buffer);
1340 }
1341
1342 /* target break-/watchpoint control
1343 * rw: 0 = write, 1 = read, 2 = access
1344 */
1345 static int arm11_add_breakpoint(struct target *target,
1346 struct breakpoint *breakpoint)
1347 {
1348 struct arm11_common *arm11 = target_to_arm11(target);
1349
1350 #if 0
1351 if (breakpoint->type == BKPT_SOFT)
1352 {
1353 LOG_INFO("sw breakpoint requested, but software breakpoints not enabled");
1354 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1355 }
1356 #endif
1357
1358 if (!arm11->free_brps)
1359 {
1360 LOG_DEBUG("no breakpoint unit available for hardware breakpoint");
1361 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1362 }
1363
1364 if (breakpoint->length != 4)
1365 {
1366 LOG_DEBUG("only breakpoints of four bytes length supported");
1367 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1368 }
1369
1370 arm11->free_brps--;
1371
1372 return ERROR_OK;
1373 }
1374
1375 static int arm11_remove_breakpoint(struct target *target,
1376 struct breakpoint *breakpoint)
1377 {
1378 struct arm11_common *arm11 = target_to_arm11(target);
1379
1380 arm11->free_brps++;
1381
1382 return ERROR_OK;
1383 }
1384
1385 static int arm11_add_watchpoint(struct target *target,
1386 struct watchpoint *watchpoint)
1387 {
1388 LOG_WARNING("Not implemented: %s", __func__);
1389
1390 return ERROR_FAIL;
1391 }
1392
1393 static int arm11_remove_watchpoint(struct target *target,
1394 struct watchpoint *watchpoint)
1395 {
1396 LOG_WARNING("Not implemented: %s", __func__);
1397
1398 return ERROR_FAIL;
1399 }
1400
1401 // HACKHACKHACK - FIXME mode/state
1402 /* target algorithm support */
1403 static int arm11_run_algorithm(struct target *target,
1404 int num_mem_params, struct mem_param *mem_params,
1405 int num_reg_params, struct reg_param *reg_params,
1406 uint32_t entry_point, uint32_t exit_point,
1407 int timeout_ms, void *arch_info)
1408 {
1409 struct arm11_common *arm11 = target_to_arm11(target);
1410 // enum armv4_5_state core_state = arm11->core_state;
1411 // enum armv4_5_mode core_mode = arm11->core_mode;
1412 uint32_t context[16];
1413 uint32_t cpsr;
1414 int exit_breakpoint_size = 0;
1415 int retval = ERROR_OK;
1416 LOG_DEBUG("Running algorithm");
1417
1418
1419 if (target->state != TARGET_HALTED)
1420 {
1421 LOG_WARNING("target not halted");
1422 return ERROR_TARGET_NOT_HALTED;
1423 }
1424
1425 // FIXME
1426 // if (!is_arm_mode(arm11->core_mode))
1427 // return ERROR_FAIL;
1428
1429 // Save regs
1430 for (unsigned i = 0; i < 16; i++)
1431 {
1432 context[i] = buf_get_u32((uint8_t*)(&arm11->reg_values[i]),0,32);
1433 LOG_DEBUG("Save %u: 0x%" PRIx32 "", i, context[i]);
1434 }
1435
1436 cpsr = buf_get_u32((uint8_t*)(arm11->reg_values + ARM11_RC_CPSR),0,32);
1437 LOG_DEBUG("Save CPSR: 0x%" PRIx32 "", cpsr);
1438
1439 for (int i = 0; i < num_mem_params; i++)
1440 {
1441 target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
1442 }
1443
1444 // Set register parameters
1445 for (int i = 0; i < num_reg_params; i++)
1446 {
1447 struct reg *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0);
1448 if (!reg)
1449 {
1450 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
1451 return ERROR_INVALID_ARGUMENTS;
1452 }
1453
1454 if (reg->size != reg_params[i].size)
1455 {
1456 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
1457 return ERROR_INVALID_ARGUMENTS;
1458 }
1459 arm11_set_reg(reg,reg_params[i].value);
1460 // printf("%i: Set %s =%08x\n", i, reg_params[i].reg_name,val);
1461 }
1462
1463 exit_breakpoint_size = 4;
1464
1465 /* arm11->core_state = arm11_algorithm_info->core_state;
1466 if (arm11->core_state == ARMV4_5_STATE_ARM)
1467 exit_breakpoint_size = 4;
1468 else if (arm11->core_state == ARMV4_5_STATE_THUMB)
1469 exit_breakpoint_size = 2;
1470 else
1471 {
1472 LOG_ERROR("BUG: can't execute algorithms when not in ARM or Thumb state");
1473 exit(-1);
1474 }
1475 */
1476
1477
1478 /* arm11 at this point only supports ARM not THUMB mode
1479 however if this test needs to be reactivated the current state can be read back
1480 from CPSR */
1481 #if 0
1482 if (arm11_algorithm_info->core_mode != ARMV4_5_MODE_ANY)
1483 {
1484 LOG_DEBUG("setting core_mode: 0x%2.2x", arm11_algorithm_info->core_mode);
1485 buf_set_u32(arm11->reg_list[ARM11_RC_CPSR].value, 0, 5, arm11_algorithm_info->core_mode);
1486 arm11->reg_list[ARM11_RC_CPSR].dirty = 1;
1487 arm11->reg_list[ARM11_RC_CPSR].valid = 1;
1488 }
1489 #endif
1490
1491 if ((retval = breakpoint_add(target, exit_point, exit_breakpoint_size, BKPT_HARD)) != ERROR_OK)
1492 {
1493 LOG_ERROR("can't add breakpoint to finish algorithm execution");
1494 retval = ERROR_TARGET_FAILURE;
1495 goto restore;
1496 }
1497
1498 // no debug, otherwise breakpoint is not set
1499 CHECK_RETVAL(target_resume(target, 0, entry_point, 1, 0));
1500
1501 CHECK_RETVAL(target_wait_state(target, TARGET_HALTED, timeout_ms));
1502
1503 if (target->state != TARGET_HALTED)
1504 {
1505 CHECK_RETVAL(target_halt(target));
1506
1507 CHECK_RETVAL(target_wait_state(target, TARGET_HALTED, 500));
1508
1509 retval = ERROR_TARGET_TIMEOUT;
1510
1511 goto del_breakpoint;
1512 }
1513
1514 if (buf_get_u32(arm11->reg_list[15].value, 0, 32) != exit_point)
1515 {
1516 LOG_WARNING("target reentered debug state, but not at the desired exit point: 0x%4.4" PRIx32 "",
1517 buf_get_u32(arm11->reg_list[15].value, 0, 32));
1518 retval = ERROR_TARGET_TIMEOUT;
1519 goto del_breakpoint;
1520 }
1521
1522 for (int i = 0; i < num_mem_params; i++)
1523 {
1524 if (mem_params[i].direction != PARAM_OUT)
1525 target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
1526 }
1527
1528 for (int i = 0; i < num_reg_params; i++)
1529 {
1530 if (reg_params[i].direction != PARAM_OUT)
1531 {
1532 struct reg *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0);
1533 if (!reg)
1534 {
1535 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
1536 retval = ERROR_INVALID_ARGUMENTS;
1537 goto del_breakpoint;
1538 }
1539
1540 if (reg->size != reg_params[i].size)
1541 {
1542 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
1543 retval = ERROR_INVALID_ARGUMENTS;
1544 goto del_breakpoint;
1545 }
1546
1547 buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
1548 }
1549 }
1550
1551 del_breakpoint:
1552 breakpoint_remove(target, exit_point);
1553
1554 restore:
1555 // Restore context
1556 for (size_t i = 0; i < 16; i++)
1557 {
1558 LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32 "",
1559 arm11->reg_list[i].name, context[i]);
1560 arm11_set_reg(&arm11->reg_list[i], (uint8_t*)&context[i]);
1561 }
1562 LOG_DEBUG("restoring CPSR with value 0x%8.8" PRIx32 "", cpsr);
1563 arm11_set_reg(&arm11->reg_list[ARM11_RC_CPSR], (uint8_t*)&cpsr);
1564
1565 // arm11->core_state = core_state;
1566 // arm11->core_mode = core_mode;
1567
1568 return retval;
1569 }
1570
1571 static int arm11_target_create(struct target *target, Jim_Interp *interp)
1572 {
1573 struct arm11_common *arm11;
1574
1575 if (target->tap == NULL)
1576 return ERROR_FAIL;
1577
1578 if (target->tap->ir_length != 5)
1579 {
1580 LOG_ERROR("'target arm11' expects IR LENGTH = 5");
1581 return ERROR_COMMAND_SYNTAX_ERROR;
1582 }
1583
1584 arm11 = calloc(1, sizeof *arm11);
1585 if (!arm11)
1586 return ERROR_FAIL;
1587
1588 armv4_5_init_arch_info(target, &arm11->arm);
1589
1590 arm11->target = target;
1591
1592 arm11->jtag_info.tap = target->tap;
1593 arm11->jtag_info.scann_size = 5;
1594 arm11->jtag_info.scann_instr = ARM11_SCAN_N;
1595 /* cur_scan_chain == 0 */
1596 arm11->jtag_info.intest_instr = ARM11_INTEST;
1597
1598 return ERROR_OK;
1599 }
1600
1601 static int arm11_init_target(struct command_context *cmd_ctx,
1602 struct target *target)
1603 {
1604 /* Initialize anything we can set up without talking to the target */
1605
1606 /* FIXME Switch to use the standard build_reg_cache() not custom
1607 * code. Do it from examine(), after we check whether we're
1608 * an arm1176 and thus support the Secure Monitor mode.
1609 */
1610 return arm11_build_reg_cache(target);
1611 }
1612
1613 /* talk to the target and set things up */
1614 static int arm11_examine(struct target *target)
1615 {
1616 int retval;
1617 char *type;
1618 struct arm11_common *arm11 = target_to_arm11(target);
1619 uint32_t didr, device_id;
1620 uint8_t implementor;
1621
1622 /* FIXME split into do-first-time and do-every-time logic ... */
1623
1624 /* check IDCODE */
1625
1626 arm11_add_IR(arm11, ARM11_IDCODE, ARM11_TAP_DEFAULT);
1627
1628 struct scan_field idcode_field;
1629
1630 arm11_setup_field(arm11, 32, NULL, &device_id, &idcode_field);
1631
1632 arm11_add_dr_scan_vc(1, &idcode_field, TAP_DRPAUSE);
1633
1634 /* check DIDR */
1635
1636 arm11_add_debug_SCAN_N(arm11, 0x00, ARM11_TAP_DEFAULT);
1637
1638 arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
1639
1640 struct scan_field chain0_fields[2];
1641
1642 arm11_setup_field(arm11, 32, NULL, &didr, chain0_fields + 0);
1643 arm11_setup_field(arm11, 8, NULL, &implementor, chain0_fields + 1);
1644
1645 arm11_add_dr_scan_vc(ARRAY_SIZE(chain0_fields), chain0_fields, TAP_IDLE);
1646
1647 CHECK_RETVAL(jtag_execute_queue());
1648
1649 switch (device_id & 0x0FFFF000)
1650 {
1651 case 0x07B36000:
1652 type = "ARM1136";
1653 break;
1654 case 0x07B56000:
1655 type = "ARM1156";
1656 break;
1657 case 0x07B76000:
1658 arm11->arm.core_type = ARM_MODE_MON;
1659 type = "ARM1176";
1660 break;
1661 default:
1662 LOG_ERROR("'target arm11' expects IDCODE 0x*7B*7****");
1663 return ERROR_FAIL;
1664 }
1665 LOG_INFO("found %s", type);
1666
1667 /* unlikely this could ever fail, but ... */
1668 switch ((didr >> 16) & 0x0F) {
1669 case ARM11_DEBUG_V6:
1670 case ARM11_DEBUG_V61: /* supports security extensions */
1671 break;
1672 default:
1673 LOG_ERROR("Only ARM v6 and v6.1 debug supported.");
1674 return ERROR_FAIL;
1675 }
1676
1677 arm11->brp = ((didr >> 24) & 0x0F) + 1;
1678 arm11->wrp = ((didr >> 28) & 0x0F) + 1;
1679
1680 /** \todo TODO: reserve one brp slot if we allow breakpoints during step */
1681 arm11->free_brps = arm11->brp;
1682 arm11->free_wrps = arm11->wrp;
1683
1684 LOG_DEBUG("IDCODE %08" PRIx32 " IMPLEMENTOR %02x DIDR %08" PRIx32,
1685 device_id, implementor, didr);
1686
1687 /* as a side-effect this reads DSCR and thus
1688 * clears the ARM11_DSCR_STICKY_PRECISE_DATA_ABORT / Sticky Precise Data Abort Flag
1689 * as suggested by the spec.
1690 */
1691
1692 retval = arm11_check_init(arm11, NULL);
1693 if (retval != ERROR_OK)
1694 return retval;
1695
1696 /* Build register cache "late", after target_init(), since we
1697 * want to know if this core supports Secure Monitor mode.
1698 */
1699 if (!target_was_examined(target)) {
1700 arm11_dpm_init(arm11, didr);
1701 retval = arm_dpm_setup(&arm11->dpm);
1702 }
1703
1704 /* ETM on ARM11 still uses original scanchain 6 access mode */
1705 if (arm11->arm.etm && !target_was_examined(target)) {
1706 *register_get_last_cache_p(&target->reg_cache) =
1707 etm_build_reg_cache(target, &arm11->jtag_info,
1708 arm11->arm.etm);
1709 retval = etm_setup(target);
1710 }
1711
1712 target_set_examined(target);
1713
1714 return ERROR_OK;
1715 }
1716
1717
1718 /** Load a register that is marked !valid in the register cache */
1719 static int arm11_get_reg(struct reg *reg)
1720 {
1721 struct target * target = ((struct arm11_reg_state *)reg->arch_info)->target;
1722
1723 if (target->state != TARGET_HALTED)
1724 {
1725 LOG_WARNING("target was not halted");
1726 return ERROR_TARGET_NOT_HALTED;
1727 }
1728
1729 /** \todo TODO: Check this. We assume that all registers are fetched at debug entry. */
1730
1731 #if 0
1732 struct arm11_common *arm11 = target_to_arm11(target);
1733 const struct arm11_reg_defs *arm11_reg_info = arm11_reg_defs + ((struct arm11_reg_state *)reg->arch_info)->def_index;
1734 #endif
1735
1736 return ERROR_OK;
1737 }
1738
1739 /** Change a value in the register cache */
1740 static int arm11_set_reg(struct reg *reg, uint8_t *buf)
1741 {
1742 struct target *target = ((struct arm11_reg_state *)reg->arch_info)->target;
1743 struct arm11_common *arm11 = target_to_arm11(target);
1744 // const struct arm11_reg_defs *arm11_reg_info = arm11_reg_defs + ((struct arm11_reg_state *)reg->arch_info)->def_index;
1745
1746 arm11->reg_values[((struct arm11_reg_state *)reg->arch_info)->def_index] = buf_get_u32(buf, 0, 32);
1747 reg->valid = 1;
1748 reg->dirty = 1;
1749
1750 return ERROR_OK;
1751 }
1752
1753 static const struct reg_arch_type arm11_reg_type = {
1754 .get = arm11_get_reg,
1755 .set = arm11_set_reg,
1756 };
1757
1758 static int arm11_build_reg_cache(struct target *target)
1759 {
1760 struct arm11_common *arm11 = target_to_arm11(target);
1761 struct reg_cache *cache;
1762 struct reg *reg_list;
1763 struct arm11_reg_state *arm11_reg_states;
1764
1765 cache = calloc(1, sizeof *cache);
1766 reg_list = calloc(ARM11_REGCACHE_COUNT, sizeof *reg_list);
1767 arm11_reg_states = calloc(ARM11_REGCACHE_COUNT,
1768 sizeof *arm11_reg_states);
1769 if (!cache || !reg_list || !arm11_reg_states) {
1770 free(cache);
1771 free(reg_list);
1772 free(arm11_reg_states);
1773 return ERROR_FAIL;
1774 }
1775
1776 arm11->reg_list = reg_list;
1777
1778 /* Build the process context cache */
1779 cache->name = "arm11 registers";
1780 cache->next = NULL;
1781 cache->reg_list = reg_list;
1782 cache->num_regs = ARM11_REGCACHE_COUNT;
1783
1784 struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
1785 (*cache_p) = cache;
1786
1787 arm11->core_cache = cache;
1788 // armv7m->process_context = cache;
1789
1790 size_t i;
1791
1792 /* Not very elegant assertion */
1793 if (ARM11_REGCACHE_COUNT != ARRAY_SIZE(arm11->reg_values) ||
1794 ARM11_REGCACHE_COUNT != ARRAY_SIZE(arm11_reg_defs) ||
1795 ARM11_REGCACHE_COUNT != ARM11_RC_MAX)
1796 {
1797 LOG_ERROR("BUG: arm11->reg_values inconsistent (%d %u %u %d)",
1798 ARM11_REGCACHE_COUNT,
1799 (unsigned) ARRAY_SIZE(arm11->reg_values),
1800 (unsigned) ARRAY_SIZE(arm11_reg_defs),
1801 ARM11_RC_MAX);
1802 /* FIXME minimally, use a build_bug_on(X) mechanism;
1803 * runtime exit() here is bad!
1804 */
1805 exit(-1);
1806 }
1807
1808 for (i = 0; i < ARM11_REGCACHE_COUNT; i++)
1809 {
1810 struct reg * r = reg_list + i;
1811 const struct arm11_reg_defs * rd = arm11_reg_defs + i;
1812 struct arm11_reg_state * rs = arm11_reg_states + i;
1813
1814 r->name = rd->name;
1815 r->size = 32;
1816 r->value = (uint8_t *)(arm11->reg_values + i);
1817 r->dirty = 0;
1818 r->valid = 0;
1819 r->type = &arm11_reg_type;
1820 r->arch_info = rs;
1821
1822 rs->def_index = i;
1823 rs->target = target;
1824 }
1825
1826 return ERROR_OK;
1827 }
1828
1829 #define ARM11_BOOL_WRAPPER(name, print_name) \
1830 COMMAND_HANDLER(arm11_handle_bool_##name) \
1831 { \
1832 return CALL_COMMAND_HANDLER(handle_command_parse_bool, \
1833 &arm11_config_##name, print_name); \
1834 }
1835
1836 ARM11_BOOL_WRAPPER(memwrite_burst, "memory write burst mode")
1837 ARM11_BOOL_WRAPPER(memwrite_error_fatal, "fatal error mode for memory writes")
1838 ARM11_BOOL_WRAPPER(step_irq_enable, "IRQs while stepping")
1839 ARM11_BOOL_WRAPPER(hardware_step, "hardware single step")
1840
1841 COMMAND_HANDLER(arm11_handle_vcr)
1842 {
1843 switch (CMD_ARGC) {
1844 case 0:
1845 break;
1846 case 1:
1847 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], arm11_vcr);
1848 break;
1849 default:
1850 return ERROR_COMMAND_SYNTAX_ERROR;
1851 }
1852
1853 LOG_INFO("VCR 0x%08" PRIx32 "", arm11_vcr);
1854 return ERROR_OK;
1855 }
1856
1857 static const uint32_t arm11_coproc_instruction_limits[] =
1858 {
1859 15, /* coprocessor */
1860 7, /* opcode 1 */
1861 15, /* CRn */
1862 15, /* CRm */
1863 7, /* opcode 2 */
1864 0xFFFFFFFF, /* value */
1865 };
1866
1867 static int arm11_mrc_inner(struct target *target, int cpnum,
1868 uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm,
1869 uint32_t *value, bool read)
1870 {
1871 int retval;
1872 struct arm11_common *arm11 = target_to_arm11(target);
1873
1874 if (target->state != TARGET_HALTED)
1875 {
1876 LOG_ERROR("Target not halted");
1877 return ERROR_FAIL;
1878 }
1879
1880 uint32_t instr = 0xEE000010 |
1881 (cpnum << 8) |
1882 (op1 << 21) |
1883 (CRn << 16) |
1884 (CRm << 0) |
1885 (op2 << 5);
1886
1887 if (read)
1888 instr |= 0x00100000;
1889
1890 retval = arm11_run_instr_data_prepare(arm11);
1891 if (retval != ERROR_OK)
1892 return retval;
1893
1894 if (read)
1895 {
1896 retval = arm11_run_instr_data_from_core_via_r0(arm11, instr, value);
1897 if (retval != ERROR_OK)
1898 return retval;
1899 }
1900 else
1901 {
1902 retval = arm11_run_instr_data_to_core_via_r0(arm11, instr, *value);
1903 if (retval != ERROR_OK)
1904 return retval;
1905 }
1906
1907 return arm11_run_instr_data_finish(arm11);
1908 }
1909
1910 static int arm11_mrc(struct target *target, int cpnum,
1911 uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value)
1912 {
1913 return arm11_mrc_inner(target, cpnum, op1, op2, CRn, CRm, value, true);
1914 }
1915
1916 static int arm11_mcr(struct target *target, int cpnum,
1917 uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value)
1918 {
1919 return arm11_mrc_inner(target, cpnum, op1, op2, CRn, CRm, &value, false);
1920 }
1921
1922 static int arm11_register_commands(struct command_context *cmd_ctx)
1923 {
1924 struct command *top_cmd, *mw_cmd;
1925
1926 armv4_5_register_commands(cmd_ctx);
1927
1928 top_cmd = register_command(cmd_ctx, NULL, "arm11",
1929 NULL, COMMAND_ANY, NULL);
1930
1931 /* "hardware_step" is only here to check if the default
1932 * simulate + breakpoint implementation is broken.
1933 * TEMPORARY! NOT DOCUMENTED!
1934 */
1935 register_command(cmd_ctx, top_cmd, "hardware_step",
1936 arm11_handle_bool_hardware_step, COMMAND_ANY,
1937 "DEBUG ONLY - Hardware single stepping"
1938 " (default: disabled)");
1939
1940 mw_cmd = register_command(cmd_ctx, top_cmd, "memwrite",
1941 NULL, COMMAND_ANY, NULL);
1942 register_command(cmd_ctx, mw_cmd, "burst",
1943 arm11_handle_bool_memwrite_burst, COMMAND_ANY,
1944 "Enable/Disable non-standard but fast burst mode"
1945 " (default: enabled)");
1946 register_command(cmd_ctx, mw_cmd, "error_fatal",
1947 arm11_handle_bool_memwrite_error_fatal, COMMAND_ANY,
1948 "Terminate program if transfer error was found"
1949 " (default: enabled)");
1950
1951 register_command(cmd_ctx, top_cmd, "step_irq_enable",
1952 arm11_handle_bool_step_irq_enable, COMMAND_ANY,
1953 "Enable interrupts while stepping"
1954 " (default: disabled)");
1955 register_command(cmd_ctx, top_cmd, "vcr",
1956 arm11_handle_vcr, COMMAND_ANY,
1957 "Control (Interrupt) Vector Catch Register");
1958
1959 return etm_register_commands(cmd_ctx);
1960 }
1961
1962 /** Holds methods for ARM11xx targets. */
1963 struct target_type arm11_target = {
1964 .name = "arm11",
1965
1966 .poll = arm11_poll,
1967 .arch_state = arm11_arch_state,
1968
1969 .target_request_data = arm11_target_request_data,
1970
1971 .halt = arm11_halt,
1972 .resume = arm11_resume,
1973 .step = arm11_step,
1974
1975 .assert_reset = arm11_assert_reset,
1976 .deassert_reset = arm11_deassert_reset,
1977 .soft_reset_halt = arm11_soft_reset_halt,
1978
1979 .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
1980
1981 .read_memory = arm11_read_memory,
1982 .write_memory = arm11_write_memory,
1983
1984 .bulk_write_memory = arm11_bulk_write_memory,
1985
1986 .checksum_memory = arm_checksum_memory,
1987 .blank_check_memory = arm_blank_check_memory,
1988
1989 .add_breakpoint = arm11_add_breakpoint,
1990 .remove_breakpoint = arm11_remove_breakpoint,
1991 .add_watchpoint = arm11_add_watchpoint,
1992 .remove_watchpoint = arm11_remove_watchpoint,
1993
1994 .run_algorithm = arm11_run_algorithm,
1995
1996 .register_commands = arm11_register_commands,
1997 .target_create = arm11_target_create,
1998 .init_target = arm11_init_target,
1999 .examine = arm11_examine,
2000
2001 .mrc = arm11_mrc,
2002 .mcr = arm11_mcr,
2003 };
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