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[openocd.git] / src / target / arm11.c
1 /***************************************************************************
2 * Copyright (C) 2008 digenius technology GmbH. *
3 * *
4 * Copyright (C) 2008 Oyvind Harboe oyvind.harboe@zylin.com *
5 * *
6 * Copyright (C) 2008 Georg Acher <acher@in.tum.de> *
7 * *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
12 * *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
17 * *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
23
24 #ifdef HAVE_CONFIG_H
25 #include "config.h"
26 #endif
27
28 #include "arm11.h"
29 #include "jtag.h"
30 #include "log.h"
31
32 #include <stdlib.h>
33 #include <string.h>
34
35 #if 0
36 #define _DEBUG_INSTRUCTION_EXECUTION_
37 #endif
38
39 #if 0
40 #define FNC_INFO LOG_DEBUG("-")
41 #else
42 #define FNC_INFO
43 #endif
44
45 #if 1
46 #define FNC_INFO_NOTIMPLEMENTED do { LOG_DEBUG("NOT IMPLEMENTED"); /*exit(-1);*/ } while (0)
47 #else
48 #define FNC_INFO_NOTIMPLEMENTED
49 #endif
50
51 static int arm11_on_enter_debug_state(arm11_common_t * arm11);
52
53 bool arm11_config_memwrite_burst = true;
54 bool arm11_config_memwrite_error_fatal = true;
55 u32 arm11_vcr = 0;
56 bool arm11_config_memrw_no_increment = false;
57 bool arm11_config_step_irq_enable = false;
58
59 #define ARM11_HANDLER(x) \
60 .x = arm11_##x
61
62 target_type_t arm11_target =
63 {
64 .name = "arm11",
65
66 ARM11_HANDLER(poll),
67 ARM11_HANDLER(arch_state),
68
69 ARM11_HANDLER(target_request_data),
70
71 ARM11_HANDLER(halt),
72 ARM11_HANDLER(resume),
73 ARM11_HANDLER(step),
74
75 ARM11_HANDLER(assert_reset),
76 ARM11_HANDLER(deassert_reset),
77 ARM11_HANDLER(soft_reset_halt),
78
79 ARM11_HANDLER(get_gdb_reg_list),
80
81 ARM11_HANDLER(read_memory),
82 ARM11_HANDLER(write_memory),
83
84 ARM11_HANDLER(bulk_write_memory),
85
86 ARM11_HANDLER(checksum_memory),
87
88 ARM11_HANDLER(add_breakpoint),
89 ARM11_HANDLER(remove_breakpoint),
90 ARM11_HANDLER(add_watchpoint),
91 ARM11_HANDLER(remove_watchpoint),
92
93 ARM11_HANDLER(run_algorithm),
94
95 ARM11_HANDLER(register_commands),
96 ARM11_HANDLER(target_create),
97 ARM11_HANDLER(init_target),
98 ARM11_HANDLER(examine),
99 ARM11_HANDLER(quit),
100 };
101
102 int arm11_regs_arch_type = -1;
103
104
105 enum arm11_regtype
106 {
107 ARM11_REGISTER_CORE,
108 ARM11_REGISTER_CPSR,
109
110 ARM11_REGISTER_FX,
111 ARM11_REGISTER_FPS,
112
113 ARM11_REGISTER_FIQ,
114 ARM11_REGISTER_SVC,
115 ARM11_REGISTER_ABT,
116 ARM11_REGISTER_IRQ,
117 ARM11_REGISTER_UND,
118 ARM11_REGISTER_MON,
119
120 ARM11_REGISTER_SPSR_FIQ,
121 ARM11_REGISTER_SPSR_SVC,
122 ARM11_REGISTER_SPSR_ABT,
123 ARM11_REGISTER_SPSR_IRQ,
124 ARM11_REGISTER_SPSR_UND,
125 ARM11_REGISTER_SPSR_MON,
126
127 /* debug regs */
128 ARM11_REGISTER_DSCR,
129 ARM11_REGISTER_WDTR,
130 ARM11_REGISTER_RDTR,
131 };
132
133
134 typedef struct arm11_reg_defs_s
135 {
136 char * name;
137 u32 num;
138 int gdb_num;
139 enum arm11_regtype type;
140 } arm11_reg_defs_t;
141
142 /* update arm11_regcache_ids when changing this */
143 static const arm11_reg_defs_t arm11_reg_defs[] =
144 {
145 {"r0", 0, 0, ARM11_REGISTER_CORE},
146 {"r1", 1, 1, ARM11_REGISTER_CORE},
147 {"r2", 2, 2, ARM11_REGISTER_CORE},
148 {"r3", 3, 3, ARM11_REGISTER_CORE},
149 {"r4", 4, 4, ARM11_REGISTER_CORE},
150 {"r5", 5, 5, ARM11_REGISTER_CORE},
151 {"r6", 6, 6, ARM11_REGISTER_CORE},
152 {"r7", 7, 7, ARM11_REGISTER_CORE},
153 {"r8", 8, 8, ARM11_REGISTER_CORE},
154 {"r9", 9, 9, ARM11_REGISTER_CORE},
155 {"r10", 10, 10, ARM11_REGISTER_CORE},
156 {"r11", 11, 11, ARM11_REGISTER_CORE},
157 {"r12", 12, 12, ARM11_REGISTER_CORE},
158 {"sp", 13, 13, ARM11_REGISTER_CORE},
159 {"lr", 14, 14, ARM11_REGISTER_CORE},
160 {"pc", 15, 15, ARM11_REGISTER_CORE},
161
162 #if ARM11_REGCACHE_FREGS
163 {"f0", 0, 16, ARM11_REGISTER_FX},
164 {"f1", 1, 17, ARM11_REGISTER_FX},
165 {"f2", 2, 18, ARM11_REGISTER_FX},
166 {"f3", 3, 19, ARM11_REGISTER_FX},
167 {"f4", 4, 20, ARM11_REGISTER_FX},
168 {"f5", 5, 21, ARM11_REGISTER_FX},
169 {"f6", 6, 22, ARM11_REGISTER_FX},
170 {"f7", 7, 23, ARM11_REGISTER_FX},
171 {"fps", 0, 24, ARM11_REGISTER_FPS},
172 #endif
173
174 {"cpsr", 0, 25, ARM11_REGISTER_CPSR},
175
176 #if ARM11_REGCACHE_MODEREGS
177 {"r8_fiq", 8, -1, ARM11_REGISTER_FIQ},
178 {"r9_fiq", 9, -1, ARM11_REGISTER_FIQ},
179 {"r10_fiq", 10, -1, ARM11_REGISTER_FIQ},
180 {"r11_fiq", 11, -1, ARM11_REGISTER_FIQ},
181 {"r12_fiq", 12, -1, ARM11_REGISTER_FIQ},
182 {"r13_fiq", 13, -1, ARM11_REGISTER_FIQ},
183 {"r14_fiq", 14, -1, ARM11_REGISTER_FIQ},
184 {"spsr_fiq", 0, -1, ARM11_REGISTER_SPSR_FIQ},
185
186 {"r13_svc", 13, -1, ARM11_REGISTER_SVC},
187 {"r14_svc", 14, -1, ARM11_REGISTER_SVC},
188 {"spsr_svc", 0, -1, ARM11_REGISTER_SPSR_SVC},
189
190 {"r13_abt", 13, -1, ARM11_REGISTER_ABT},
191 {"r14_abt", 14, -1, ARM11_REGISTER_ABT},
192 {"spsr_abt", 0, -1, ARM11_REGISTER_SPSR_ABT},
193
194 {"r13_irq", 13, -1, ARM11_REGISTER_IRQ},
195 {"r14_irq", 14, -1, ARM11_REGISTER_IRQ},
196 {"spsr_irq", 0, -1, ARM11_REGISTER_SPSR_IRQ},
197
198 {"r13_und", 13, -1, ARM11_REGISTER_UND},
199 {"r14_und", 14, -1, ARM11_REGISTER_UND},
200 {"spsr_und", 0, -1, ARM11_REGISTER_SPSR_UND},
201
202 /* ARM1176 only */
203 {"r13_mon", 13, -1, ARM11_REGISTER_MON},
204 {"r14_mon", 14, -1, ARM11_REGISTER_MON},
205 {"spsr_mon", 0, -1, ARM11_REGISTER_SPSR_MON},
206 #endif
207
208 /* Debug Registers */
209 {"dscr", 0, -1, ARM11_REGISTER_DSCR},
210 {"wdtr", 0, -1, ARM11_REGISTER_WDTR},
211 {"rdtr", 0, -1, ARM11_REGISTER_RDTR},
212 };
213
214 enum arm11_regcache_ids
215 {
216 ARM11_RC_R0,
217 ARM11_RC_RX = ARM11_RC_R0,
218
219 ARM11_RC_R1,
220 ARM11_RC_R2,
221 ARM11_RC_R3,
222 ARM11_RC_R4,
223 ARM11_RC_R5,
224 ARM11_RC_R6,
225 ARM11_RC_R7,
226 ARM11_RC_R8,
227 ARM11_RC_R9,
228 ARM11_RC_R10,
229 ARM11_RC_R11,
230 ARM11_RC_R12,
231 ARM11_RC_R13,
232 ARM11_RC_SP = ARM11_RC_R13,
233 ARM11_RC_R14,
234 ARM11_RC_LR = ARM11_RC_R14,
235 ARM11_RC_R15,
236 ARM11_RC_PC = ARM11_RC_R15,
237
238 #if ARM11_REGCACHE_FREGS
239 ARM11_RC_F0,
240 ARM11_RC_FX = ARM11_RC_F0,
241 ARM11_RC_F1,
242 ARM11_RC_F2,
243 ARM11_RC_F3,
244 ARM11_RC_F4,
245 ARM11_RC_F5,
246 ARM11_RC_F6,
247 ARM11_RC_F7,
248 ARM11_RC_FPS,
249 #endif
250
251 ARM11_RC_CPSR,
252
253 #if ARM11_REGCACHE_MODEREGS
254 ARM11_RC_R8_FIQ,
255 ARM11_RC_R9_FIQ,
256 ARM11_RC_R10_FIQ,
257 ARM11_RC_R11_FIQ,
258 ARM11_RC_R12_FIQ,
259 ARM11_RC_R13_FIQ,
260 ARM11_RC_R14_FIQ,
261 ARM11_RC_SPSR_FIQ,
262
263 ARM11_RC_R13_SVC,
264 ARM11_RC_R14_SVC,
265 ARM11_RC_SPSR_SVC,
266
267 ARM11_RC_R13_ABT,
268 ARM11_RC_R14_ABT,
269 ARM11_RC_SPSR_ABT,
270
271 ARM11_RC_R13_IRQ,
272 ARM11_RC_R14_IRQ,
273 ARM11_RC_SPSR_IRQ,
274
275 ARM11_RC_R13_UND,
276 ARM11_RC_R14_UND,
277 ARM11_RC_SPSR_UND,
278
279 ARM11_RC_R13_MON,
280 ARM11_RC_R14_MON,
281 ARM11_RC_SPSR_MON,
282 #endif
283
284 ARM11_RC_DSCR,
285 ARM11_RC_WDTR,
286 ARM11_RC_RDTR,
287
288 ARM11_RC_MAX,
289 };
290
291 #define ARM11_GDB_REGISTER_COUNT 26
292
293 u8 arm11_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
294
295 reg_t arm11_gdb_dummy_fp_reg =
296 {
297 "GDB dummy floating-point register", arm11_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0
298 };
299
300 u8 arm11_gdb_dummy_fps_value[] = {0, 0, 0, 0};
301
302 reg_t arm11_gdb_dummy_fps_reg =
303 {
304 "GDB dummy floating-point status register", arm11_gdb_dummy_fps_value, 0, 1, 32, NULL, 0, NULL, 0
305 };
306
307
308
309 /** Check and if necessary take control of the system
310 *
311 * \param arm11 Target state variable.
312 * \param dscr If the current DSCR content is
313 * available a pointer to a word holding the
314 * DSCR can be passed. Otherwise use NULL.
315 */
316 int arm11_check_init(arm11_common_t * arm11, u32 * dscr)
317 {
318 FNC_INFO;
319
320 u32 dscr_local_tmp_copy;
321
322 if (!dscr)
323 {
324 dscr = &dscr_local_tmp_copy;
325
326 CHECK_RETVAL(arm11_read_DSCR(arm11, dscr));
327 }
328
329 if (!(*dscr & ARM11_DSCR_MODE_SELECT))
330 {
331 LOG_DEBUG("Bringing target into debug mode");
332
333 *dscr |= ARM11_DSCR_MODE_SELECT; /* Halt debug-mode */
334 arm11_write_DSCR(arm11, *dscr);
335
336 /* add further reset initialization here */
337
338 arm11->simulate_reset_on_next_halt = true;
339
340 if (*dscr & ARM11_DSCR_CORE_HALTED)
341 {
342 /** \todo TODO: this needs further scrutiny because
343 * arm11_on_enter_debug_state() never gets properly called
344 */
345
346 arm11->target->state = TARGET_HALTED;
347 arm11->target->debug_reason = arm11_get_DSCR_debug_reason(*dscr);
348 }
349 else
350 {
351 arm11->target->state = TARGET_RUNNING;
352 arm11->target->debug_reason = DBG_REASON_NOTHALTED;
353 }
354
355 arm11_sc7_clear_vbw(arm11);
356 }
357
358 return ERROR_OK;
359 }
360
361
362
363 #define R(x) \
364 (arm11->reg_values[ARM11_RC_##x])
365
366 /** Save processor state.
367 *
368 * This is called when the HALT instruction has succeeded
369 * or on other occasions that stop the processor.
370 *
371 */
372 static int arm11_on_enter_debug_state(arm11_common_t * arm11)
373 {
374 FNC_INFO;
375
376 {size_t i;
377 for(i = 0; i < asizeof(arm11->reg_values); i++)
378 {
379 arm11->reg_list[i].valid = 1;
380 arm11->reg_list[i].dirty = 0;
381 }}
382
383 /* Save DSCR */
384 CHECK_RETVAL(arm11_read_DSCR(arm11, &R(DSCR)));
385
386 /* Save wDTR */
387
388 if (R(DSCR) & ARM11_DSCR_WDTR_FULL)
389 {
390 arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
391
392 arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
393
394 scan_field_t chain5_fields[3];
395
396 arm11_setup_field(arm11, 32, NULL, &R(WDTR), chain5_fields + 0);
397 arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 1);
398 arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 2);
399
400 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
401 }
402 else
403 {
404 arm11->reg_list[ARM11_RC_WDTR].valid = 0;
405 }
406
407
408 /* DSCR: set ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE */
409 /* ARM1176 spec says this is needed only for wDTR/rDTR's "ITR mode", but not to issue ITRs
410 ARM1136 seems to require this to issue ITR's as well */
411
412 u32 new_dscr = R(DSCR) | ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE;
413
414 /* this executes JTAG queue: */
415
416 arm11_write_DSCR(arm11, new_dscr);
417
418
419 /* From the spec:
420 Before executing any instruction in debug state you have to drain the write buffer.
421 This ensures that no imprecise Data Aborts can return at a later point:*/
422
423 /** \todo TODO: Test drain write buffer. */
424
425 #if 0
426 while (1)
427 {
428 /* MRC p14,0,R0,c5,c10,0 */
429 // arm11_run_instr_no_data1(arm11, /*0xee150e1a*/0xe320f000);
430
431 /* mcr 15, 0, r0, cr7, cr10, {4} */
432 arm11_run_instr_no_data1(arm11, 0xee070f9a);
433
434 u32 dscr = arm11_read_DSCR(arm11);
435
436 LOG_DEBUG("DRAIN, DSCR %08x", dscr);
437
438 if (dscr & ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT)
439 {
440 arm11_run_instr_no_data1(arm11, 0xe320f000);
441
442 dscr = arm11_read_DSCR(arm11);
443
444 LOG_DEBUG("DRAIN, DSCR %08x (DONE)", dscr);
445
446 break;
447 }
448 }
449 #endif
450
451 arm11_run_instr_data_prepare(arm11);
452
453 /* save r0 - r14 */
454
455 /** \todo TODO: handle other mode registers */
456
457 {size_t i;
458 for (i = 0; i < 15; i++)
459 {
460 /* MCR p14,0,R?,c0,c5,0 */
461 arm11_run_instr_data_from_core(arm11, 0xEE000E15 | (i << 12), &R(RX + i), 1);
462 }}
463
464 /* save rDTR */
465
466 /* check rDTRfull in DSCR */
467
468 if (R(DSCR) & ARM11_DSCR_RDTR_FULL)
469 {
470 /* MRC p14,0,R0,c0,c5,0 (move rDTR -> r0 (-> wDTR -> local var)) */
471 arm11_run_instr_data_from_core_via_r0(arm11, 0xEE100E15, &R(RDTR));
472 }
473 else
474 {
475 arm11->reg_list[ARM11_RC_RDTR].valid = 0;
476 }
477
478 /* save CPSR */
479
480 /* MRS r0,CPSR (move CPSR -> r0 (-> wDTR -> local var)) */
481 arm11_run_instr_data_from_core_via_r0(arm11, 0xE10F0000, &R(CPSR));
482
483 /* save PC */
484
485 /* MOV R0,PC (move PC -> r0 (-> wDTR -> local var)) */
486 arm11_run_instr_data_from_core_via_r0(arm11, 0xE1A0000F, &R(PC));
487
488 /* adjust PC depending on ARM state */
489
490 if (R(CPSR) & ARM11_CPSR_J) /* Java state */
491 {
492 arm11->reg_values[ARM11_RC_PC] -= 0;
493 }
494 else if (R(CPSR) & ARM11_CPSR_T) /* Thumb state */
495 {
496 arm11->reg_values[ARM11_RC_PC] -= 4;
497 }
498 else /* ARM state */
499 {
500 arm11->reg_values[ARM11_RC_PC] -= 8;
501 }
502
503 if (arm11->simulate_reset_on_next_halt)
504 {
505 arm11->simulate_reset_on_next_halt = false;
506
507 LOG_DEBUG("Reset c1 Control Register");
508
509 /* Write 0 (reset value) to Control register 0 to disable MMU/Cache etc. */
510
511 /* MCR p15,0,R0,c1,c0,0 */
512 arm11_run_instr_data_to_core_via_r0(arm11, 0xee010f10, 0);
513
514 }
515
516 arm11_run_instr_data_finish(arm11);
517
518 arm11_dump_reg_changes(arm11);
519
520 return ERROR_OK;
521 }
522
523 void arm11_dump_reg_changes(arm11_common_t * arm11)
524 {
525
526 if (!(debug_level >= LOG_LVL_DEBUG))
527 {
528 return;
529 }
530
531 {size_t i;
532 for(i = 0; i < ARM11_REGCACHE_COUNT; i++)
533 {
534 if (!arm11->reg_list[i].valid)
535 {
536 if (arm11->reg_history[i].valid)
537 LOG_DEBUG("%8s INVALID (%08x)", arm11_reg_defs[i].name, arm11->reg_history[i].value);
538 }
539 else
540 {
541 if (arm11->reg_history[i].valid)
542 {
543 if (arm11->reg_history[i].value != arm11->reg_values[i])
544 LOG_DEBUG("%8s %08x (%08x)", arm11_reg_defs[i].name, arm11->reg_values[i], arm11->reg_history[i].value);
545 }
546 else
547 {
548 LOG_DEBUG("%8s %08x (INVALID)", arm11_reg_defs[i].name, arm11->reg_values[i]);
549 }
550 }
551 }}
552 }
553
554 /** Restore processor state
555 *
556 * This is called in preparation for the RESTART function.
557 *
558 */
559 int arm11_leave_debug_state(arm11_common_t * arm11)
560 {
561 FNC_INFO;
562
563 arm11_run_instr_data_prepare(arm11);
564
565 /** \todo TODO: handle other mode registers */
566
567 /* restore R1 - R14 */
568 {size_t i;
569 for (i = 1; i < 15; i++)
570 {
571 if (!arm11->reg_list[ARM11_RC_RX + i].dirty)
572 continue;
573
574 /* MRC p14,0,r?,c0,c5,0 */
575 arm11_run_instr_data_to_core1(arm11, 0xee100e15 | (i << 12), R(RX + i));
576
577 // LOG_DEBUG("RESTORE R" ZU " %08x", i, R(RX + i));
578 }}
579
580 arm11_run_instr_data_finish(arm11);
581
582 /* spec says clear wDTR and rDTR; we assume they are clear as
583 otherwise our programming would be sloppy */
584 {
585 u32 DSCR;
586
587 CHECK_RETVAL(arm11_read_DSCR(arm11, &DSCR));
588
589 if (DSCR & (ARM11_DSCR_RDTR_FULL | ARM11_DSCR_WDTR_FULL))
590 {
591 LOG_ERROR("wDTR/rDTR inconsistent (DSCR %08x)", DSCR);
592 }
593 }
594
595 arm11_run_instr_data_prepare(arm11);
596
597 /* restore original wDTR */
598
599 if ((R(DSCR) & ARM11_DSCR_WDTR_FULL) || arm11->reg_list[ARM11_RC_WDTR].dirty)
600 {
601 /* MCR p14,0,R0,c0,c5,0 */
602 arm11_run_instr_data_to_core_via_r0(arm11, 0xee000e15, R(WDTR));
603 }
604
605 /* restore CPSR */
606
607 /* MSR CPSR,R0*/
608 arm11_run_instr_data_to_core_via_r0(arm11, 0xe129f000, R(CPSR));
609
610 /* restore PC */
611
612 /* MOV PC,R0 */
613 arm11_run_instr_data_to_core_via_r0(arm11, 0xe1a0f000, R(PC));
614
615 /* restore R0 */
616
617 /* MRC p14,0,r0,c0,c5,0 */
618 arm11_run_instr_data_to_core1(arm11, 0xee100e15, R(R0));
619
620 arm11_run_instr_data_finish(arm11);
621
622 /* restore DSCR */
623
624 arm11_write_DSCR(arm11, R(DSCR));
625
626 /* restore rDTR */
627
628 if (R(DSCR) & ARM11_DSCR_RDTR_FULL || arm11->reg_list[ARM11_RC_RDTR].dirty)
629 {
630 arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
631
632 arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT);
633
634 scan_field_t chain5_fields[3];
635
636 u8 Ready = 0; /* ignored */
637 u8 Valid = 0; /* ignored */
638
639 arm11_setup_field(arm11, 32, &R(RDTR), NULL, chain5_fields + 0);
640 arm11_setup_field(arm11, 1, &Ready, NULL, chain5_fields + 1);
641 arm11_setup_field(arm11, 1, &Valid, NULL, chain5_fields + 2);
642
643 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
644 }
645
646 arm11_record_register_history(arm11);
647
648 return ERROR_OK;
649 }
650
651 void arm11_record_register_history(arm11_common_t * arm11)
652 {
653 {size_t i;
654 for(i = 0; i < ARM11_REGCACHE_COUNT; i++)
655 {
656 arm11->reg_history[i].value = arm11->reg_values[i];
657 arm11->reg_history[i].valid = arm11->reg_list[i].valid;
658
659 arm11->reg_list[i].valid = 0;
660 arm11->reg_list[i].dirty = 0;
661 }}
662 }
663
664
665 /* poll current target status */
666 int arm11_poll(struct target_s *target)
667 {
668 FNC_INFO;
669
670 arm11_common_t * arm11 = target->arch_info;
671
672 if (arm11->trst_active)
673 return ERROR_OK;
674
675 u32 dscr;
676
677 CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
678
679 LOG_DEBUG("DSCR %08x", dscr);
680
681 CHECK_RETVAL(arm11_check_init(arm11, &dscr));
682
683 if (dscr & ARM11_DSCR_CORE_HALTED)
684 {
685 if (target->state != TARGET_HALTED)
686 {
687 enum target_state old_state = target->state;
688
689 LOG_DEBUG("enter TARGET_HALTED");
690 target->state = TARGET_HALTED;
691 target->debug_reason = arm11_get_DSCR_debug_reason(dscr);
692 arm11_on_enter_debug_state(arm11);
693
694 target_call_event_callbacks(target,
695 old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED);
696 }
697 }
698 else
699 {
700 if (target->state != TARGET_RUNNING && target->state != TARGET_DEBUG_RUNNING)
701 {
702 LOG_DEBUG("enter TARGET_RUNNING");
703 target->state = TARGET_RUNNING;
704 target->debug_reason = DBG_REASON_NOTHALTED;
705 }
706 }
707
708 return ERROR_OK;
709 }
710 /* architecture specific status reply */
711 int arm11_arch_state(struct target_s *target)
712 {
713 arm11_common_t * arm11 = target->arch_info;
714
715 LOG_USER("target halted due to %s\ncpsr: 0x%8.8x pc: 0x%8.8x",
716 Jim_Nvp_value2name_simple( nvp_target_debug_reason, target->debug_reason )->name,
717 R(CPSR),
718 R(PC));
719
720 return ERROR_OK;
721 }
722
723 /* target request support */
724 int arm11_target_request_data(struct target_s *target, u32 size, u8 *buffer)
725 {
726 FNC_INFO_NOTIMPLEMENTED;
727
728 return ERROR_OK;
729 }
730
731 /* target execution control */
732 int arm11_halt(struct target_s *target)
733 {
734 FNC_INFO;
735
736 arm11_common_t * arm11 = target->arch_info;
737
738 LOG_DEBUG("target->state: %s",
739 Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name );
740
741 if (target->state == TARGET_UNKNOWN)
742 {
743 arm11->simulate_reset_on_next_halt = true;
744 }
745
746 if (target->state == TARGET_HALTED)
747 {
748 LOG_DEBUG("target was already halted");
749 return ERROR_OK;
750 }
751
752 if (arm11->trst_active)
753 {
754 arm11->halt_requested = true;
755 return ERROR_OK;
756 }
757
758 arm11_add_IR(arm11, ARM11_HALT, TAP_IDLE);
759
760 CHECK_RETVAL(jtag_execute_queue());
761
762 u32 dscr;
763
764 while (1)
765 {
766 CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
767
768 if (dscr & ARM11_DSCR_CORE_HALTED)
769 break;
770 }
771
772 arm11_on_enter_debug_state(arm11);
773
774 enum target_state old_state = target->state;
775
776 target->state = TARGET_HALTED;
777 target->debug_reason = arm11_get_DSCR_debug_reason(dscr);
778
779 CHECK_RETVAL(
780 target_call_event_callbacks(target,
781 old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED));
782
783 return ERROR_OK;
784 }
785
786 int arm11_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution)
787 {
788 FNC_INFO;
789
790 // LOG_DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d",
791 // current, address, handle_breakpoints, debug_execution);
792
793 arm11_common_t * arm11 = target->arch_info;
794
795 LOG_DEBUG("target->state: %s",
796 Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name );
797
798
799 if (target->state != TARGET_HALTED)
800 {
801 LOG_ERROR("Target not halted");
802 return ERROR_TARGET_NOT_HALTED;
803 }
804
805 if (!current)
806 R(PC) = address;
807
808 LOG_DEBUG("RESUME PC %08x%s", R(PC), !current ? "!" : "");
809
810 /* clear breakpoints/watchpoints and VCR*/
811 arm11_sc7_clear_vbw(arm11);
812
813 /* Set up breakpoints */
814 if (!debug_execution)
815 {
816 /* check if one matches PC and step over it if necessary */
817
818 breakpoint_t * bp;
819
820 for (bp = target->breakpoints; bp; bp = bp->next)
821 {
822 if (bp->address == R(PC))
823 {
824 LOG_DEBUG("must step over %08x", bp->address);
825 arm11_step(target, 1, 0, 0);
826 break;
827 }
828 }
829
830 /* set all breakpoints */
831
832 size_t brp_num = 0;
833
834 for (bp = target->breakpoints; bp; bp = bp->next)
835 {
836 arm11_sc7_action_t brp[2];
837
838 brp[0].write = 1;
839 brp[0].address = ARM11_SC7_BVR0 + brp_num;
840 brp[0].value = bp->address;
841 brp[1].write = 1;
842 brp[1].address = ARM11_SC7_BCR0 + brp_num;
843 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
844
845 arm11_sc7_run(arm11, brp, asizeof(brp));
846
847 LOG_DEBUG("Add BP " ZU " at %08x", brp_num, bp->address);
848
849 brp_num++;
850 }
851
852 arm11_sc7_set_vcr(arm11, arm11_vcr);
853 }
854
855 arm11_leave_debug_state(arm11);
856
857 arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
858
859 CHECK_RETVAL(jtag_execute_queue());
860
861 while (1)
862 {
863 u32 dscr;
864
865 CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
866
867 LOG_DEBUG("DSCR %08x", dscr);
868
869 if (dscr & ARM11_DSCR_CORE_RESTARTED)
870 break;
871 }
872
873 if (!debug_execution)
874 {
875 target->state = TARGET_RUNNING;
876 target->debug_reason = DBG_REASON_NOTHALTED;
877
878 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
879 }
880 else
881 {
882 target->state = TARGET_DEBUG_RUNNING;
883 target->debug_reason = DBG_REASON_NOTHALTED;
884
885 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
886 }
887
888 return ERROR_OK;
889 }
890
891 int arm11_step(struct target_s *target, int current, u32 address, int handle_breakpoints)
892 {
893 FNC_INFO;
894
895 LOG_DEBUG("target->state: %s",
896 Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name );
897
898 if (target->state != TARGET_HALTED)
899 {
900 LOG_WARNING("target was not halted");
901 return ERROR_TARGET_NOT_HALTED;
902 }
903
904 arm11_common_t * arm11 = target->arch_info;
905
906 if (!current)
907 R(PC) = address;
908
909 LOG_DEBUG("STEP PC %08x%s", R(PC), !current ? "!" : "");
910
911 /** \todo TODO: Thumb not supported here */
912
913 u32 next_instruction;
914
915 CHECK_RETVAL(arm11_read_memory_word(arm11, R(PC), &next_instruction));
916
917 /* skip over BKPT */
918 if ((next_instruction & 0xFFF00070) == 0xe1200070)
919 {
920 R(PC) += 4;
921 arm11->reg_list[ARM11_RC_PC].valid = 1;
922 arm11->reg_list[ARM11_RC_PC].dirty = 0;
923 LOG_DEBUG("Skipping BKPT");
924 }
925 /* skip over Wait for interrupt / Standby */
926 /* mcr 15, 0, r?, cr7, cr0, {4} */
927 else if ((next_instruction & 0xFFFF0FFF) == 0xee070f90)
928 {
929 R(PC) += 4;
930 arm11->reg_list[ARM11_RC_PC].valid = 1;
931 arm11->reg_list[ARM11_RC_PC].dirty = 0;
932 LOG_DEBUG("Skipping WFI");
933 }
934 /* ignore B to self */
935 else if ((next_instruction & 0xFEFFFFFF) == 0xeafffffe)
936 {
937 LOG_DEBUG("Not stepping jump to self");
938 }
939 else
940 {
941 /** \todo TODO: check if break-/watchpoints make any sense at all in combination
942 * with this. */
943
944 /** \todo TODO: check if disabling IRQs might be a good idea here. Alternatively
945 * the VCR might be something worth looking into. */
946
947
948 /* Set up breakpoint for stepping */
949
950 arm11_sc7_action_t brp[2];
951
952 brp[0].write = 1;
953 brp[0].address = ARM11_SC7_BVR0;
954 brp[0].value = R(PC);
955 brp[1].write = 1;
956 brp[1].address = ARM11_SC7_BCR0;
957 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (2 << 21);
958
959 CHECK_RETVAL(arm11_sc7_run(arm11, brp, asizeof(brp)));
960
961 /* resume */
962
963
964 if (arm11_config_step_irq_enable)
965 R(DSCR) &= ~ARM11_DSCR_INTERRUPTS_DISABLE; /* should be redundant */
966 else
967 R(DSCR) |= ARM11_DSCR_INTERRUPTS_DISABLE;
968
969
970 CHECK_RETVAL(arm11_leave_debug_state(arm11));
971
972 arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
973
974 CHECK_RETVAL(jtag_execute_queue());
975
976 /** \todo TODO: add a timeout */
977
978 /* wait for halt */
979
980 while (1)
981 {
982 u32 dscr;
983
984 CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
985
986 LOG_DEBUG("DSCR %08x", dscr);
987
988 if ((dscr & (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED)) ==
989 (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED))
990 break;
991 }
992
993 /* clear breakpoint */
994 arm11_sc7_clear_vbw(arm11);
995
996 /* save state */
997 CHECK_RETVAL(arm11_on_enter_debug_state(arm11));
998
999 /* restore default state */
1000 R(DSCR) &= ~ARM11_DSCR_INTERRUPTS_DISABLE;
1001
1002 }
1003
1004 // target->state = TARGET_HALTED;
1005 target->debug_reason = DBG_REASON_SINGLESTEP;
1006
1007 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_HALTED));
1008
1009 return ERROR_OK;
1010 }
1011
1012 /* target reset control */
1013 int arm11_assert_reset(struct target_s *target)
1014 {
1015 FNC_INFO;
1016
1017 #if 0
1018 /* assert reset lines */
1019 /* resets only the DBGTAP, not the ARM */
1020
1021 jtag_add_reset(1, 0);
1022 jtag_add_sleep(5000);
1023
1024 arm11_common_t * arm11 = target->arch_info;
1025 arm11->trst_active = true;
1026 #endif
1027
1028 if (target->reset_halt)
1029 {
1030 CHECK_RETVAL(target_halt(target));
1031 }
1032
1033 return ERROR_OK;
1034 }
1035
1036 int arm11_deassert_reset(struct target_s *target)
1037 {
1038 FNC_INFO;
1039
1040 #if 0
1041 LOG_DEBUG("target->state: %s",
1042 Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name );
1043
1044
1045 /* deassert reset lines */
1046 jtag_add_reset(0, 0);
1047
1048 arm11_common_t * arm11 = target->arch_info;
1049 arm11->trst_active = false;
1050
1051 if (arm11->halt_requested)
1052 return arm11_halt(target);
1053 #endif
1054
1055 return ERROR_OK;
1056 }
1057
1058 int arm11_soft_reset_halt(struct target_s *target)
1059 {
1060 FNC_INFO_NOTIMPLEMENTED;
1061
1062 return ERROR_OK;
1063 }
1064
1065 /* target register access for gdb */
1066 int arm11_get_gdb_reg_list(struct target_s *target, struct reg_s **reg_list[], int *reg_list_size)
1067 {
1068 FNC_INFO;
1069
1070 arm11_common_t * arm11 = target->arch_info;
1071
1072 *reg_list_size = ARM11_GDB_REGISTER_COUNT;
1073 *reg_list = malloc(sizeof(reg_t*) * ARM11_GDB_REGISTER_COUNT);
1074
1075 {size_t i;
1076 for (i = 16; i < 24; i++)
1077 {
1078 (*reg_list)[i] = &arm11_gdb_dummy_fp_reg;
1079 }}
1080
1081 (*reg_list)[24] = &arm11_gdb_dummy_fps_reg;
1082
1083 {size_t i;
1084 for (i = 0; i < ARM11_REGCACHE_COUNT; i++)
1085 {
1086 if (arm11_reg_defs[i].gdb_num == -1)
1087 continue;
1088
1089 (*reg_list)[arm11_reg_defs[i].gdb_num] = arm11->reg_list + i;
1090 }}
1091
1092 return ERROR_OK;
1093 }
1094
1095 /* target memory access
1096 * size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
1097 * count: number of items of <size>
1098 */
1099 int arm11_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1100 {
1101 /** \todo TODO: check if buffer cast to u32* and u16* might cause alignment problems */
1102
1103 FNC_INFO;
1104
1105 if (target->state != TARGET_HALTED)
1106 {
1107 LOG_WARNING("target was not halted");
1108 return ERROR_TARGET_NOT_HALTED;
1109 }
1110
1111 LOG_DEBUG("ADDR %08x SIZE %08x COUNT %08x", address, size, count);
1112
1113 arm11_common_t * arm11 = target->arch_info;
1114
1115 arm11_run_instr_data_prepare(arm11);
1116
1117 /* MRC p14,0,r0,c0,c5,0 */
1118 arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
1119
1120 switch (size)
1121 {
1122 case 1:
1123 /** \todo TODO: check if dirty is the right choice to force a rewrite on arm11_resume() */
1124 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1125
1126 {size_t i;
1127 for (i = 0; i < count; i++)
1128 {
1129 /* ldrb r1, [r0], #1 */
1130 /* ldrb r1, [r0] */
1131 arm11_run_instr_no_data1(arm11,
1132 !arm11_config_memrw_no_increment ? 0xe4d01001 : 0xe5d01000);
1133
1134 u32 res;
1135 /* MCR p14,0,R1,c0,c5,0 */
1136 arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
1137
1138 *buffer++ = res;
1139 }}
1140
1141 break;
1142
1143 case 2:
1144 {
1145 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1146
1147 u16 * buf16 = (u16*)buffer;
1148
1149 {size_t i;
1150 for (i = 0; i < count; i++)
1151 {
1152 /* ldrh r1, [r0], #2 */
1153 arm11_run_instr_no_data1(arm11,
1154 !arm11_config_memrw_no_increment ? 0xe0d010b2 : 0xe1d010b0);
1155
1156 u32 res;
1157
1158 /* MCR p14,0,R1,c0,c5,0 */
1159 arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
1160
1161 *buf16++ = res;
1162 }}
1163
1164 break;
1165 }
1166
1167 case 4:
1168
1169 /* LDC p14,c5,[R0],#4 */
1170 /* LDC p14,c5,[R0] */
1171 arm11_run_instr_data_from_core(arm11,
1172 (!arm11_config_memrw_no_increment ? 0xecb05e01 : 0xed905e00),
1173 (u32 *)buffer, count);
1174 break;
1175 }
1176
1177 arm11_run_instr_data_finish(arm11);
1178
1179 return ERROR_OK;
1180 }
1181
1182 int arm11_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1183 {
1184 FNC_INFO;
1185
1186 if (target->state != TARGET_HALTED)
1187 {
1188 LOG_WARNING("target was not halted");
1189 return ERROR_TARGET_NOT_HALTED;
1190 }
1191
1192 LOG_DEBUG("ADDR %08x SIZE %08x COUNT %08x", address, size, count);
1193
1194 arm11_common_t * arm11 = target->arch_info;
1195
1196 arm11_run_instr_data_prepare(arm11);
1197
1198 /* MRC p14,0,r0,c0,c5,0 */
1199 arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
1200
1201 switch (size)
1202 {
1203 case 1:
1204 {
1205 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1206
1207 {size_t i;
1208 for (i = 0; i < count; i++)
1209 {
1210 /* MRC p14,0,r1,c0,c5,0 */
1211 arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buffer++);
1212
1213 /* strb r1, [r0], #1 */
1214 /* strb r1, [r0] */
1215 arm11_run_instr_no_data1(arm11,
1216 !arm11_config_memrw_no_increment ? 0xe4c01001 : 0xe5c01000);
1217 }}
1218
1219 break;
1220 }
1221
1222 case 2:
1223 {
1224 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1225
1226 u16 * buf16 = (u16*)buffer;
1227
1228 {size_t i;
1229 for (i = 0; i < count; i++)
1230 {
1231 /* MRC p14,0,r1,c0,c5,0 */
1232 arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buf16++);
1233
1234 /* strh r1, [r0], #2 */
1235 /* strh r1, [r0] */
1236 arm11_run_instr_no_data1(arm11,
1237 !arm11_config_memrw_no_increment ? 0xe0c010b2 : 0xe1c010b0);
1238 }}
1239
1240 break;
1241 }
1242
1243 case 4:
1244 /** \todo TODO: check if buffer cast to u32* might cause alignment problems */
1245
1246 if (!arm11_config_memwrite_burst)
1247 {
1248 /* STC p14,c5,[R0],#4 */
1249 /* STC p14,c5,[R0]*/
1250 arm11_run_instr_data_to_core(arm11,
1251 (!arm11_config_memrw_no_increment ? 0xeca05e01 : 0xed805e00),
1252 (u32 *)buffer, count);
1253 }
1254 else
1255 {
1256 /* STC p14,c5,[R0],#4 */
1257 /* STC p14,c5,[R0]*/
1258 arm11_run_instr_data_to_core_noack(arm11,
1259 (!arm11_config_memrw_no_increment ? 0xeca05e01 : 0xed805e00),
1260 (u32 *)buffer, count);
1261 }
1262
1263 break;
1264 }
1265
1266 #if 1
1267 /* r0 verification */
1268 if (!arm11_config_memrw_no_increment)
1269 {
1270 u32 r0;
1271
1272 /* MCR p14,0,R0,c0,c5,0 */
1273 arm11_run_instr_data_from_core(arm11, 0xEE000E15, &r0, 1);
1274
1275 if (address + size * count != r0)
1276 {
1277 LOG_ERROR("Data transfer failed. (%d)", (r0 - address) - size * count);
1278
1279 if (arm11_config_memwrite_burst)
1280 LOG_ERROR("use 'arm11 memwrite burst disable' to disable fast burst mode");
1281
1282 if (arm11_config_memwrite_error_fatal)
1283 return ERROR_FAIL;
1284 }
1285 }
1286 #endif
1287
1288 arm11_run_instr_data_finish(arm11);
1289
1290 return ERROR_OK;
1291 }
1292
1293
1294 /* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
1295 int arm11_bulk_write_memory(struct target_s *target, u32 address, u32 count, u8 *buffer)
1296 {
1297 FNC_INFO;
1298
1299 if (target->state != TARGET_HALTED)
1300 {
1301 LOG_WARNING("target was not halted");
1302 return ERROR_TARGET_NOT_HALTED;
1303 }
1304
1305 return arm11_write_memory(target, address, 4, count, buffer);
1306 }
1307
1308 /* here we have nothing target specific to contribute, so we fail and then the
1309 * fallback code will read data from the target and calculate the CRC on the
1310 * host.
1311 */
1312 int arm11_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum)
1313 {
1314 return ERROR_FAIL;
1315 }
1316
1317 /* target break-/watchpoint control
1318 * rw: 0 = write, 1 = read, 2 = access
1319 */
1320 int arm11_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
1321 {
1322 FNC_INFO;
1323
1324 arm11_common_t * arm11 = target->arch_info;
1325
1326 #if 0
1327 if (breakpoint->type == BKPT_SOFT)
1328 {
1329 LOG_INFO("sw breakpoint requested, but software breakpoints not enabled");
1330 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1331 }
1332 #endif
1333
1334 if (!arm11->free_brps)
1335 {
1336 LOG_DEBUG("no breakpoint unit available for hardware breakpoint");
1337 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1338 }
1339
1340 if (breakpoint->length != 4)
1341 {
1342 LOG_DEBUG("only breakpoints of four bytes length supported");
1343 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1344 }
1345
1346 arm11->free_brps--;
1347
1348 return ERROR_OK;
1349 }
1350
1351 int arm11_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
1352 {
1353 FNC_INFO;
1354
1355 arm11_common_t * arm11 = target->arch_info;
1356
1357 arm11->free_brps++;
1358
1359 return ERROR_OK;
1360 }
1361
1362 int arm11_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
1363 {
1364 FNC_INFO_NOTIMPLEMENTED;
1365
1366 return ERROR_OK;
1367 }
1368
1369 int arm11_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
1370 {
1371 FNC_INFO_NOTIMPLEMENTED;
1372
1373 return ERROR_OK;
1374 }
1375
1376 // HACKHACKHACK - FIXME mode/state
1377 /* target algorithm support */
1378 int arm11_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params,
1379 int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point,
1380 int timeout_ms, void *arch_info)
1381 {
1382 arm11_common_t *arm11 = target->arch_info;
1383 armv4_5_algorithm_t *arm11_algorithm_info = arch_info;
1384 // enum armv4_5_state core_state = arm11->core_state;
1385 // enum armv4_5_mode core_mode = arm11->core_mode;
1386 u32 context[16];
1387 u32 cpsr;
1388 int exit_breakpoint_size = 0;
1389 int i;
1390 int retval = ERROR_OK;
1391 LOG_DEBUG("Running algorithm");
1392
1393 if (arm11_algorithm_info->common_magic != ARMV4_5_COMMON_MAGIC)
1394 {
1395 LOG_ERROR("current target isn't an ARMV4/5 target");
1396 return ERROR_TARGET_INVALID;
1397 }
1398
1399 if (target->state != TARGET_HALTED)
1400 {
1401 LOG_WARNING("target not halted");
1402 return ERROR_TARGET_NOT_HALTED;
1403 }
1404
1405 // FIXME
1406 // if (armv4_5_mode_to_number(arm11->core_mode)==-1)
1407 // return ERROR_FAIL;
1408
1409 // Save regs
1410 for (i = 0; i < 16; i++)
1411 {
1412 context[i] = buf_get_u32((u8*)(&arm11->reg_values[i]),0,32);
1413 LOG_DEBUG("Save %i: 0x%x",i,context[i]);
1414 }
1415
1416 cpsr = buf_get_u32((u8*)(arm11->reg_values+ARM11_RC_CPSR),0,32);
1417 LOG_DEBUG("Save CPSR: 0x%x", cpsr);
1418
1419 for (i = 0; i < num_mem_params; i++)
1420 {
1421 target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
1422 }
1423
1424 // Set register parameters
1425 for (i = 0; i < num_reg_params; i++)
1426 {
1427 reg_t *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0);
1428 if (!reg)
1429 {
1430 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
1431 exit(-1);
1432 }
1433
1434 if (reg->size != reg_params[i].size)
1435 {
1436 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
1437 exit(-1);
1438 }
1439 arm11_set_reg(reg,reg_params[i].value);
1440 // printf("%i: Set %s =%08x\n", i, reg_params[i].reg_name,val);
1441 }
1442
1443 exit_breakpoint_size = 4;
1444
1445 /* arm11->core_state = arm11_algorithm_info->core_state;
1446 if (arm11->core_state == ARMV4_5_STATE_ARM)
1447 exit_breakpoint_size = 4;
1448 else if (arm11->core_state == ARMV4_5_STATE_THUMB)
1449 exit_breakpoint_size = 2;
1450 else
1451 {
1452 LOG_ERROR("BUG: can't execute algorithms when not in ARM or Thumb state");
1453 exit(-1);
1454 }
1455 */
1456 if (arm11_algorithm_info->core_mode != ARMV4_5_MODE_ANY)
1457 {
1458 LOG_DEBUG("setting core_mode: 0x%2.2x", arm11_algorithm_info->core_mode);
1459 buf_set_u32(arm11->reg_list[ARM11_RC_CPSR].value, 0, 5, arm11_algorithm_info->core_mode);
1460 arm11->reg_list[ARM11_RC_CPSR].dirty = 1;
1461 arm11->reg_list[ARM11_RC_CPSR].valid = 1;
1462 }
1463
1464 if ((retval = breakpoint_add(target, exit_point, exit_breakpoint_size, BKPT_HARD)) != ERROR_OK)
1465 {
1466 LOG_ERROR("can't add breakpoint to finish algorithm execution");
1467 retval = ERROR_TARGET_FAILURE;
1468 goto restore;
1469 }
1470
1471 // no debug, otherwise breakpoint is not set
1472 CHECK_RETVAL(target_resume(target, 0, entry_point, 1, 0));
1473
1474 CHECK_RETVAL(target_wait_state(target, TARGET_HALTED, timeout_ms));
1475
1476 if (target->state != TARGET_HALTED)
1477 {
1478 CHECK_RETVAL(target_halt(target));
1479
1480 CHECK_RETVAL(target_wait_state(target, TARGET_HALTED, 500));
1481
1482 retval = ERROR_TARGET_TIMEOUT;
1483
1484 goto del_breakpoint;
1485 }
1486
1487 if (buf_get_u32(arm11->reg_list[15].value, 0, 32) != exit_point)
1488 {
1489 LOG_WARNING("target reentered debug state, but not at the desired exit point: 0x%4.4x",
1490 buf_get_u32(arm11->reg_list[15].value, 0, 32));
1491 retval = ERROR_TARGET_TIMEOUT;
1492 goto del_breakpoint;
1493 }
1494
1495 for (i = 0; i < num_mem_params; i++)
1496 {
1497 if (mem_params[i].direction != PARAM_OUT)
1498 target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
1499 }
1500
1501 for (i = 0; i < num_reg_params; i++)
1502 {
1503 if (reg_params[i].direction != PARAM_OUT)
1504 {
1505 reg_t *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0);
1506 if (!reg)
1507 {
1508 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
1509 exit(-1);
1510 }
1511
1512 if (reg->size != reg_params[i].size)
1513 {
1514 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
1515 exit(-1);
1516 }
1517
1518 buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
1519 }
1520 }
1521
1522 del_breakpoint:
1523 breakpoint_remove(target, exit_point);
1524
1525 restore:
1526 // Restore context
1527 for (i = 0; i < 16; i++)
1528 {
1529 LOG_DEBUG("restoring register %s with value 0x%8.8x",
1530 arm11->reg_list[i].name, context[i]);
1531 arm11_set_reg(&arm11->reg_list[i], (u8*)&context[i]);
1532 }
1533 LOG_DEBUG("restoring CPSR with value 0x%8.8x", cpsr);
1534 arm11_set_reg(&arm11->reg_list[ARM11_RC_CPSR], (u8*)&cpsr);
1535
1536 // arm11->core_state = core_state;
1537 // arm11->core_mode = core_mode;
1538
1539 return retval;
1540 }
1541
1542 int arm11_target_create(struct target_s *target, Jim_Interp *interp)
1543 {
1544 FNC_INFO;
1545
1546 NEW(arm11_common_t, arm11, 1);
1547
1548 arm11->target = target;
1549
1550 /* prepare JTAG information for the new target */
1551 arm11->jtag_info.tap = target->tap;
1552 arm11->jtag_info.scann_size = 5;
1553
1554 CHECK_RETVAL(arm_jtag_setup_connection(&arm11->jtag_info));
1555
1556 if (target->tap==NULL)
1557 return ERROR_FAIL;
1558
1559 if (target->tap->ir_length != 5)
1560 {
1561 LOG_ERROR("'target arm11' expects IR LENGTH = 5");
1562 return ERROR_COMMAND_SYNTAX_ERROR;
1563 }
1564
1565 target->arch_info = arm11;
1566
1567 return ERROR_OK;
1568 }
1569
1570 int arm11_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
1571 {
1572 /* Initialize anything we can set up without talking to the target */
1573 return arm11_build_reg_cache(target);
1574 }
1575
1576 /* talk to the target and set things up */
1577 int arm11_examine(struct target_s *target)
1578 {
1579 FNC_INFO;
1580
1581 arm11_common_t * arm11 = target->arch_info;
1582
1583 /* check IDCODE */
1584
1585 arm11_add_IR(arm11, ARM11_IDCODE, ARM11_TAP_DEFAULT);
1586
1587 scan_field_t idcode_field;
1588
1589 arm11_setup_field(arm11, 32, NULL, &arm11->device_id, &idcode_field);
1590
1591 arm11_add_dr_scan_vc(1, &idcode_field, TAP_DRPAUSE);
1592
1593 /* check DIDR */
1594
1595 arm11_add_debug_SCAN_N(arm11, 0x00, ARM11_TAP_DEFAULT);
1596
1597 arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
1598
1599 scan_field_t chain0_fields[2];
1600
1601 arm11_setup_field(arm11, 32, NULL, &arm11->didr, chain0_fields + 0);
1602 arm11_setup_field(arm11, 8, NULL, &arm11->implementor, chain0_fields + 1);
1603
1604 arm11_add_dr_scan_vc(asizeof(chain0_fields), chain0_fields, TAP_IDLE);
1605
1606 CHECK_RETVAL(jtag_execute_queue());
1607
1608 switch (arm11->device_id & 0x0FFFF000)
1609 {
1610 case 0x07B36000: LOG_INFO("found ARM1136"); break;
1611 case 0x07B56000: LOG_INFO("found ARM1156"); break;
1612 case 0x07B76000: LOG_INFO("found ARM1176"); break;
1613 default:
1614 {
1615 LOG_ERROR("'target arm11' expects IDCODE 0x*7B*7****");
1616 return ERROR_FAIL;
1617 }
1618 }
1619
1620 arm11->debug_version = (arm11->didr >> 16) & 0x0F;
1621
1622 if (arm11->debug_version != ARM11_DEBUG_V6 &&
1623 arm11->debug_version != ARM11_DEBUG_V61)
1624 {
1625 LOG_ERROR("Only ARMv6 v6 and v6.1 architectures supported.");
1626 return ERROR_FAIL;
1627 }
1628
1629 arm11->brp = ((arm11->didr >> 24) & 0x0F) + 1;
1630 arm11->wrp = ((arm11->didr >> 28) & 0x0F) + 1;
1631
1632 /** \todo TODO: reserve one brp slot if we allow breakpoints during step */
1633 arm11->free_brps = arm11->brp;
1634 arm11->free_wrps = arm11->wrp;
1635
1636 LOG_DEBUG("IDCODE %08x IMPLEMENTOR %02x DIDR %08x",
1637 arm11->device_id,
1638 arm11->implementor,
1639 arm11->didr);
1640
1641 /* as a side-effect this reads DSCR and thus
1642 * clears the ARM11_DSCR_STICKY_PRECISE_DATA_ABORT / Sticky Precise Data Abort Flag
1643 * as suggested by the spec.
1644 */
1645
1646 arm11_check_init(arm11, NULL);
1647
1648 target->type->examined = 1;
1649
1650 return ERROR_OK;
1651 }
1652
1653 int arm11_quit(void)
1654 {
1655 FNC_INFO_NOTIMPLEMENTED;
1656
1657 return ERROR_OK;
1658 }
1659
1660 /** Load a register that is marked !valid in the register cache */
1661 int arm11_get_reg(reg_t *reg)
1662 {
1663 FNC_INFO;
1664
1665 target_t * target = ((arm11_reg_state_t *)reg->arch_info)->target;
1666
1667 if (target->state != TARGET_HALTED)
1668 {
1669 LOG_WARNING("target was not halted");
1670 return ERROR_TARGET_NOT_HALTED;
1671 }
1672
1673 /** \todo TODO: Check this. We assume that all registers are fetched at debug entry. */
1674
1675 #if 0
1676 arm11_common_t *arm11 = target->arch_info;
1677 const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index;
1678 #endif
1679
1680 return ERROR_OK;
1681 }
1682
1683 /** Change a value in the register cache */
1684 int arm11_set_reg(reg_t *reg, u8 *buf)
1685 {
1686 FNC_INFO;
1687
1688 target_t * target = ((arm11_reg_state_t *)reg->arch_info)->target;
1689 arm11_common_t *arm11 = target->arch_info;
1690 // const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index;
1691
1692 arm11->reg_values[((arm11_reg_state_t *)reg->arch_info)->def_index] = buf_get_u32(buf, 0, 32);
1693 reg->valid = 1;
1694 reg->dirty = 1;
1695
1696 return ERROR_OK;
1697 }
1698
1699 int arm11_build_reg_cache(target_t *target)
1700 {
1701 arm11_common_t *arm11 = target->arch_info;
1702
1703 NEW(reg_cache_t, cache, 1);
1704 NEW(reg_t, reg_list, ARM11_REGCACHE_COUNT);
1705 NEW(arm11_reg_state_t, arm11_reg_states, ARM11_REGCACHE_COUNT);
1706
1707 if (arm11_regs_arch_type == -1)
1708 arm11_regs_arch_type = register_reg_arch_type(arm11_get_reg, arm11_set_reg);
1709
1710 register_init_dummy(&arm11_gdb_dummy_fp_reg);
1711 register_init_dummy(&arm11_gdb_dummy_fps_reg);
1712
1713 arm11->reg_list = reg_list;
1714
1715 /* Build the process context cache */
1716 cache->name = "arm11 registers";
1717 cache->next = NULL;
1718 cache->reg_list = reg_list;
1719 cache->num_regs = ARM11_REGCACHE_COUNT;
1720
1721 reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
1722 (*cache_p) = cache;
1723
1724 arm11->core_cache = cache;
1725 // armv7m->process_context = cache;
1726
1727 size_t i;
1728
1729 /* Not very elegant assertion */
1730 if (ARM11_REGCACHE_COUNT != asizeof(arm11->reg_values) ||
1731 ARM11_REGCACHE_COUNT != asizeof(arm11_reg_defs) ||
1732 ARM11_REGCACHE_COUNT != ARM11_RC_MAX)
1733 {
1734 LOG_ERROR("BUG: arm11->reg_values inconsistent (%d " ZU " " ZU " %d)", ARM11_REGCACHE_COUNT, asizeof(arm11->reg_values), asizeof(arm11_reg_defs), ARM11_RC_MAX);
1735 exit(-1);
1736 }
1737
1738 for (i = 0; i < ARM11_REGCACHE_COUNT; i++)
1739 {
1740 reg_t * r = reg_list + i;
1741 const arm11_reg_defs_t * rd = arm11_reg_defs + i;
1742 arm11_reg_state_t * rs = arm11_reg_states + i;
1743
1744 r->name = rd->name;
1745 r->size = 32;
1746 r->value = (u8 *)(arm11->reg_values + i);
1747 r->dirty = 0;
1748 r->valid = 0;
1749 r->bitfield_desc = NULL;
1750 r->num_bitfields = 0;
1751 r->arch_type = arm11_regs_arch_type;
1752 r->arch_info = rs;
1753
1754 rs->def_index = i;
1755 rs->target = target;
1756 }
1757
1758 return ERROR_OK;
1759 }
1760
1761 int arm11_handle_bool(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, bool * var, char * name)
1762 {
1763 if (argc == 0)
1764 {
1765 LOG_INFO("%s is %s.", name, *var ? "enabled" : "disabled");
1766 return ERROR_OK;
1767 }
1768
1769 if (argc != 1)
1770 return ERROR_COMMAND_SYNTAX_ERROR;
1771
1772 switch (args[0][0])
1773 {
1774 case '0': /* 0 */
1775 case 'f': /* false */
1776 case 'F':
1777 case 'd': /* disable */
1778 case 'D':
1779 *var = false;
1780 break;
1781
1782 case '1': /* 1 */
1783 case 't': /* true */
1784 case 'T':
1785 case 'e': /* enable */
1786 case 'E':
1787 *var = true;
1788 break;
1789 }
1790
1791 LOG_INFO("%s %s.", *var ? "Enabled" : "Disabled", name);
1792
1793 return ERROR_OK;
1794 }
1795
1796 #define BOOL_WRAPPER(name, print_name) \
1797 int arm11_handle_bool_##name(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) \
1798 { \
1799 return arm11_handle_bool(cmd_ctx, cmd, args, argc, &arm11_config_##name, print_name); \
1800 }
1801
1802 #define RC_TOP(name, descr, more) \
1803 { \
1804 command_t * new_cmd = register_command(cmd_ctx, top_cmd, name, NULL, COMMAND_ANY, descr); \
1805 command_t * top_cmd = new_cmd; \
1806 more \
1807 }
1808
1809 #define RC_FINAL(name, descr, handler) \
1810 register_command(cmd_ctx, top_cmd, name, handler, COMMAND_ANY, descr);
1811
1812 #define RC_FINAL_BOOL(name, descr, var) \
1813 register_command(cmd_ctx, top_cmd, name, arm11_handle_bool_##var, COMMAND_ANY, descr);
1814
1815 BOOL_WRAPPER(memwrite_burst, "memory write burst mode")
1816 BOOL_WRAPPER(memwrite_error_fatal, "fatal error mode for memory writes")
1817 BOOL_WRAPPER(memrw_no_increment, "\"no increment\" mode for memory transfers")
1818 BOOL_WRAPPER(step_irq_enable, "IRQs while stepping")
1819
1820 int arm11_handle_vcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1821 {
1822 if (argc == 1)
1823 {
1824 arm11_vcr = strtoul(args[0], NULL, 0);
1825 }
1826 else if (argc != 0)
1827 {
1828 return ERROR_COMMAND_SYNTAX_ERROR;
1829 }
1830
1831 LOG_INFO("VCR 0x%08X", arm11_vcr);
1832 return ERROR_OK;
1833 }
1834
1835 const u32 arm11_coproc_instruction_limits[] =
1836 {
1837 15, /* coprocessor */
1838 7, /* opcode 1 */
1839 15, /* CRn */
1840 15, /* CRm */
1841 7, /* opcode 2 */
1842 0xFFFFFFFF, /* value */
1843 };
1844
1845 const char arm11_mrc_syntax[] = "Syntax: mrc <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2>. All parameters are numbers only.";
1846 const char arm11_mcr_syntax[] = "Syntax: mcr <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2> <32bit value to write>. All parameters are numbers only.";
1847
1848 arm11_common_t * arm11_find_target(const char * arg)
1849 {
1850 jtag_tap_t * tap;
1851 target_t * t;
1852
1853 tap = jtag_TapByString(arg);
1854
1855 if (!tap)
1856 return 0;
1857
1858 for (t = all_targets; t; t = t->next)
1859 {
1860 if (t->tap != tap)
1861 continue;
1862
1863 /* if (t->type == arm11_target) */
1864 if (0 == strcmp(t->type->name, "arm11"))
1865 return t->arch_info;
1866 }
1867
1868 return 0;
1869 }
1870
1871 int arm11_handle_mrc_mcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, bool read)
1872 {
1873 if (argc != (read ? 6 : 7))
1874 {
1875 LOG_ERROR("Invalid number of arguments. %s", read ? arm11_mrc_syntax : arm11_mcr_syntax);
1876 return -1;
1877 }
1878
1879 arm11_common_t * arm11 = arm11_find_target(args[0]);
1880
1881 if (!arm11)
1882 {
1883 LOG_ERROR("Parameter 1 is not a the JTAG chain position of an ARM11 device. %s",
1884 read ? arm11_mrc_syntax : arm11_mcr_syntax);
1885
1886 return -1;
1887 }
1888
1889 if (arm11->target->state != TARGET_HALTED)
1890 {
1891 LOG_WARNING("target was not halted");
1892 return ERROR_TARGET_NOT_HALTED;
1893 }
1894
1895 u32 values[6];
1896
1897 {size_t i;
1898 for (i = 0; i < (read ? 5 : 6); i++)
1899 {
1900 values[i] = strtoul(args[i + 1], NULL, 0);
1901
1902 if (values[i] > arm11_coproc_instruction_limits[i])
1903 {
1904 LOG_ERROR("Parameter %ld out of bounds (%d max). %s",
1905 (long)(i + 2), arm11_coproc_instruction_limits[i],
1906 read ? arm11_mrc_syntax : arm11_mcr_syntax);
1907 return -1;
1908 }
1909 }}
1910
1911 u32 instr = 0xEE000010 |
1912 (values[0] << 8) |
1913 (values[1] << 21) |
1914 (values[2] << 16) |
1915 (values[3] << 0) |
1916 (values[4] << 5);
1917
1918 if (read)
1919 instr |= 0x00100000;
1920
1921 arm11_run_instr_data_prepare(arm11);
1922
1923 if (read)
1924 {
1925 u32 result;
1926 arm11_run_instr_data_from_core_via_r0(arm11, instr, &result);
1927
1928 LOG_INFO("MRC p%d, %d, R0, c%d, c%d, %d = 0x%08x (%d)",
1929 values[0], values[1], values[2], values[3], values[4], result, result);
1930 }
1931 else
1932 {
1933 arm11_run_instr_data_to_core_via_r0(arm11, instr, values[5]);
1934
1935 LOG_INFO("MRC p%d, %d, R0 (#0x%08x), c%d, c%d, %d",
1936 values[0], values[1],
1937 values[5],
1938 values[2], values[3], values[4]);
1939 }
1940
1941 arm11_run_instr_data_finish(arm11);
1942
1943
1944 return ERROR_OK;
1945 }
1946
1947 int arm11_handle_mrc(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1948 {
1949 return arm11_handle_mrc_mcr(cmd_ctx, cmd, args, argc, true);
1950 }
1951
1952 int arm11_handle_mcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1953 {
1954 return arm11_handle_mrc_mcr(cmd_ctx, cmd, args, argc, false);
1955 }
1956
1957 int arm11_register_commands(struct command_context_s *cmd_ctx)
1958 {
1959 FNC_INFO;
1960
1961 command_t * top_cmd = NULL;
1962
1963 RC_TOP( "arm11", "arm11 specific commands",
1964
1965 RC_TOP( "memwrite", "Control memory write transfer mode",
1966
1967 RC_FINAL_BOOL( "burst", "Enable/Disable non-standard but fast burst mode (default: enabled)",
1968 memwrite_burst)
1969
1970 RC_FINAL_BOOL( "error_fatal", "Terminate program if transfer error was found (default: enabled)",
1971 memwrite_error_fatal)
1972 )
1973
1974 RC_FINAL_BOOL( "no_increment", "Don't increment address on multi-read/-write (default: disabled)",
1975 memrw_no_increment)
1976
1977 RC_FINAL_BOOL( "step_irq_enable", "Enable interrupts while stepping (default: disabled)",
1978 step_irq_enable)
1979
1980 RC_FINAL( "vcr", "Control (Interrupt) Vector Catch Register",
1981 arm11_handle_vcr)
1982
1983 RC_FINAL( "mrc", "Read Coprocessor register",
1984 arm11_handle_mrc)
1985
1986 RC_FINAL( "mcr", "Write Coprocessor register",
1987 arm11_handle_mcr)
1988 )
1989
1990 return ERROR_OK;
1991 }
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