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If halt times out, stop GDB. Allows e.g. manual reset via monitor commands.
[openocd.git] / src / target / arm11.c
1 /***************************************************************************
2 * Copyright (C) 2008 digenius technology GmbH. *
3 * Michael Bruck *
4 * *
5 * Copyright (C) 2008,2009 Oyvind Harboe oyvind.harboe@zylin.com *
6 * *
7 * Copyright (C) 2008 Georg Acher <acher@in.tum.de> *
8 * *
9 * This program is free software; you can redistribute it and/or modify *
10 * it under the terms of the GNU General Public License as published by *
11 * the Free Software Foundation; either version 2 of the License, or *
12 * (at your option) any later version. *
13 * *
14 * This program is distributed in the hope that it will be useful, *
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
17 * GNU General Public License for more details. *
18 * *
19 * You should have received a copy of the GNU General Public License *
20 * along with this program; if not, write to the *
21 * Free Software Foundation, Inc., *
22 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
23 ***************************************************************************/
24
25 #ifdef HAVE_CONFIG_H
26 #include "config.h"
27 #endif
28
29 #include "arm11.h"
30 #include "armv4_5.h"
31 #include "arm_simulator.h"
32 #include "time_support.h"
33 #include "target_type.h"
34
35
36 #if 0
37 #define _DEBUG_INSTRUCTION_EXECUTION_
38 #endif
39
40 #if 0
41 #define FNC_INFO LOG_DEBUG("-")
42 #else
43 #define FNC_INFO
44 #endif
45
46 #if 1
47 #define FNC_INFO_NOTIMPLEMENTED do { LOG_DEBUG("NOT IMPLEMENTED"); /*exit(-1);*/ } while (0)
48 #else
49 #define FNC_INFO_NOTIMPLEMENTED
50 #endif
51
52 static int arm11_on_enter_debug_state(arm11_common_t * arm11);
53
54 bool arm11_config_memwrite_burst = true;
55 bool arm11_config_memwrite_error_fatal = true;
56 uint32_t arm11_vcr = 0;
57 bool arm11_config_memrw_no_increment = false;
58 bool arm11_config_step_irq_enable = false;
59 bool arm11_config_hardware_step = false;
60
61 #define ARM11_HANDLER(x) \
62 .x = arm11_##x
63
64 target_type_t arm11_target =
65 {
66 .name = "arm11",
67
68 ARM11_HANDLER(poll),
69 ARM11_HANDLER(arch_state),
70
71 ARM11_HANDLER(target_request_data),
72
73 ARM11_HANDLER(halt),
74 ARM11_HANDLER(resume),
75 ARM11_HANDLER(step),
76
77 ARM11_HANDLER(assert_reset),
78 ARM11_HANDLER(deassert_reset),
79 ARM11_HANDLER(soft_reset_halt),
80
81 ARM11_HANDLER(get_gdb_reg_list),
82
83 ARM11_HANDLER(read_memory),
84 ARM11_HANDLER(write_memory),
85
86 ARM11_HANDLER(bulk_write_memory),
87
88 ARM11_HANDLER(checksum_memory),
89
90 ARM11_HANDLER(add_breakpoint),
91 ARM11_HANDLER(remove_breakpoint),
92 ARM11_HANDLER(add_watchpoint),
93 ARM11_HANDLER(remove_watchpoint),
94
95 ARM11_HANDLER(run_algorithm),
96
97 ARM11_HANDLER(register_commands),
98 ARM11_HANDLER(target_create),
99 ARM11_HANDLER(init_target),
100 ARM11_HANDLER(examine),
101 ARM11_HANDLER(quit),
102 };
103
104 int arm11_regs_arch_type = -1;
105
106
107 enum arm11_regtype
108 {
109 ARM11_REGISTER_CORE,
110 ARM11_REGISTER_CPSR,
111
112 ARM11_REGISTER_FX,
113 ARM11_REGISTER_FPS,
114
115 ARM11_REGISTER_FIQ,
116 ARM11_REGISTER_SVC,
117 ARM11_REGISTER_ABT,
118 ARM11_REGISTER_IRQ,
119 ARM11_REGISTER_UND,
120 ARM11_REGISTER_MON,
121
122 ARM11_REGISTER_SPSR_FIQ,
123 ARM11_REGISTER_SPSR_SVC,
124 ARM11_REGISTER_SPSR_ABT,
125 ARM11_REGISTER_SPSR_IRQ,
126 ARM11_REGISTER_SPSR_UND,
127 ARM11_REGISTER_SPSR_MON,
128
129 /* debug regs */
130 ARM11_REGISTER_DSCR,
131 ARM11_REGISTER_WDTR,
132 ARM11_REGISTER_RDTR,
133 };
134
135
136 typedef struct arm11_reg_defs_s
137 {
138 char * name;
139 uint32_t num;
140 int gdb_num;
141 enum arm11_regtype type;
142 } arm11_reg_defs_t;
143
144 /* update arm11_regcache_ids when changing this */
145 static const arm11_reg_defs_t arm11_reg_defs[] =
146 {
147 {"r0", 0, 0, ARM11_REGISTER_CORE},
148 {"r1", 1, 1, ARM11_REGISTER_CORE},
149 {"r2", 2, 2, ARM11_REGISTER_CORE},
150 {"r3", 3, 3, ARM11_REGISTER_CORE},
151 {"r4", 4, 4, ARM11_REGISTER_CORE},
152 {"r5", 5, 5, ARM11_REGISTER_CORE},
153 {"r6", 6, 6, ARM11_REGISTER_CORE},
154 {"r7", 7, 7, ARM11_REGISTER_CORE},
155 {"r8", 8, 8, ARM11_REGISTER_CORE},
156 {"r9", 9, 9, ARM11_REGISTER_CORE},
157 {"r10", 10, 10, ARM11_REGISTER_CORE},
158 {"r11", 11, 11, ARM11_REGISTER_CORE},
159 {"r12", 12, 12, ARM11_REGISTER_CORE},
160 {"sp", 13, 13, ARM11_REGISTER_CORE},
161 {"lr", 14, 14, ARM11_REGISTER_CORE},
162 {"pc", 15, 15, ARM11_REGISTER_CORE},
163
164 #if ARM11_REGCACHE_FREGS
165 {"f0", 0, 16, ARM11_REGISTER_FX},
166 {"f1", 1, 17, ARM11_REGISTER_FX},
167 {"f2", 2, 18, ARM11_REGISTER_FX},
168 {"f3", 3, 19, ARM11_REGISTER_FX},
169 {"f4", 4, 20, ARM11_REGISTER_FX},
170 {"f5", 5, 21, ARM11_REGISTER_FX},
171 {"f6", 6, 22, ARM11_REGISTER_FX},
172 {"f7", 7, 23, ARM11_REGISTER_FX},
173 {"fps", 0, 24, ARM11_REGISTER_FPS},
174 #endif
175
176 {"cpsr", 0, 25, ARM11_REGISTER_CPSR},
177
178 #if ARM11_REGCACHE_MODEREGS
179 {"r8_fiq", 8, -1, ARM11_REGISTER_FIQ},
180 {"r9_fiq", 9, -1, ARM11_REGISTER_FIQ},
181 {"r10_fiq", 10, -1, ARM11_REGISTER_FIQ},
182 {"r11_fiq", 11, -1, ARM11_REGISTER_FIQ},
183 {"r12_fiq", 12, -1, ARM11_REGISTER_FIQ},
184 {"r13_fiq", 13, -1, ARM11_REGISTER_FIQ},
185 {"r14_fiq", 14, -1, ARM11_REGISTER_FIQ},
186 {"spsr_fiq", 0, -1, ARM11_REGISTER_SPSR_FIQ},
187
188 {"r13_svc", 13, -1, ARM11_REGISTER_SVC},
189 {"r14_svc", 14, -1, ARM11_REGISTER_SVC},
190 {"spsr_svc", 0, -1, ARM11_REGISTER_SPSR_SVC},
191
192 {"r13_abt", 13, -1, ARM11_REGISTER_ABT},
193 {"r14_abt", 14, -1, ARM11_REGISTER_ABT},
194 {"spsr_abt", 0, -1, ARM11_REGISTER_SPSR_ABT},
195
196 {"r13_irq", 13, -1, ARM11_REGISTER_IRQ},
197 {"r14_irq", 14, -1, ARM11_REGISTER_IRQ},
198 {"spsr_irq", 0, -1, ARM11_REGISTER_SPSR_IRQ},
199
200 {"r13_und", 13, -1, ARM11_REGISTER_UND},
201 {"r14_und", 14, -1, ARM11_REGISTER_UND},
202 {"spsr_und", 0, -1, ARM11_REGISTER_SPSR_UND},
203
204 /* ARM1176 only */
205 {"r13_mon", 13, -1, ARM11_REGISTER_MON},
206 {"r14_mon", 14, -1, ARM11_REGISTER_MON},
207 {"spsr_mon", 0, -1, ARM11_REGISTER_SPSR_MON},
208 #endif
209
210 /* Debug Registers */
211 {"dscr", 0, -1, ARM11_REGISTER_DSCR},
212 {"wdtr", 0, -1, ARM11_REGISTER_WDTR},
213 {"rdtr", 0, -1, ARM11_REGISTER_RDTR},
214 };
215
216 enum arm11_regcache_ids
217 {
218 ARM11_RC_R0,
219 ARM11_RC_RX = ARM11_RC_R0,
220
221 ARM11_RC_R1,
222 ARM11_RC_R2,
223 ARM11_RC_R3,
224 ARM11_RC_R4,
225 ARM11_RC_R5,
226 ARM11_RC_R6,
227 ARM11_RC_R7,
228 ARM11_RC_R8,
229 ARM11_RC_R9,
230 ARM11_RC_R10,
231 ARM11_RC_R11,
232 ARM11_RC_R12,
233 ARM11_RC_R13,
234 ARM11_RC_SP = ARM11_RC_R13,
235 ARM11_RC_R14,
236 ARM11_RC_LR = ARM11_RC_R14,
237 ARM11_RC_R15,
238 ARM11_RC_PC = ARM11_RC_R15,
239
240 #if ARM11_REGCACHE_FREGS
241 ARM11_RC_F0,
242 ARM11_RC_FX = ARM11_RC_F0,
243 ARM11_RC_F1,
244 ARM11_RC_F2,
245 ARM11_RC_F3,
246 ARM11_RC_F4,
247 ARM11_RC_F5,
248 ARM11_RC_F6,
249 ARM11_RC_F7,
250 ARM11_RC_FPS,
251 #endif
252
253 ARM11_RC_CPSR,
254
255 #if ARM11_REGCACHE_MODEREGS
256 ARM11_RC_R8_FIQ,
257 ARM11_RC_R9_FIQ,
258 ARM11_RC_R10_FIQ,
259 ARM11_RC_R11_FIQ,
260 ARM11_RC_R12_FIQ,
261 ARM11_RC_R13_FIQ,
262 ARM11_RC_R14_FIQ,
263 ARM11_RC_SPSR_FIQ,
264
265 ARM11_RC_R13_SVC,
266 ARM11_RC_R14_SVC,
267 ARM11_RC_SPSR_SVC,
268
269 ARM11_RC_R13_ABT,
270 ARM11_RC_R14_ABT,
271 ARM11_RC_SPSR_ABT,
272
273 ARM11_RC_R13_IRQ,
274 ARM11_RC_R14_IRQ,
275 ARM11_RC_SPSR_IRQ,
276
277 ARM11_RC_R13_UND,
278 ARM11_RC_R14_UND,
279 ARM11_RC_SPSR_UND,
280
281 ARM11_RC_R13_MON,
282 ARM11_RC_R14_MON,
283 ARM11_RC_SPSR_MON,
284 #endif
285
286 ARM11_RC_DSCR,
287 ARM11_RC_WDTR,
288 ARM11_RC_RDTR,
289
290 ARM11_RC_MAX,
291 };
292
293 #define ARM11_GDB_REGISTER_COUNT 26
294
295 uint8_t arm11_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
296
297 reg_t arm11_gdb_dummy_fp_reg =
298 {
299 "GDB dummy floating-point register", arm11_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0
300 };
301
302 uint8_t arm11_gdb_dummy_fps_value[] = {0, 0, 0, 0};
303
304 reg_t arm11_gdb_dummy_fps_reg =
305 {
306 "GDB dummy floating-point status register", arm11_gdb_dummy_fps_value, 0, 1, 32, NULL, 0, NULL, 0
307 };
308
309
310
311 /** Check and if necessary take control of the system
312 *
313 * \param arm11 Target state variable.
314 * \param dscr If the current DSCR content is
315 * available a pointer to a word holding the
316 * DSCR can be passed. Otherwise use NULL.
317 */
318 int arm11_check_init(arm11_common_t * arm11, uint32_t * dscr)
319 {
320 FNC_INFO;
321
322 uint32_t dscr_local_tmp_copy;
323
324 if (!dscr)
325 {
326 dscr = &dscr_local_tmp_copy;
327
328 CHECK_RETVAL(arm11_read_DSCR(arm11, dscr));
329 }
330
331 if (!(*dscr & ARM11_DSCR_MODE_SELECT))
332 {
333 LOG_DEBUG("Bringing target into debug mode");
334
335 *dscr |= ARM11_DSCR_MODE_SELECT; /* Halt debug-mode */
336 arm11_write_DSCR(arm11, *dscr);
337
338 /* add further reset initialization here */
339
340 arm11->simulate_reset_on_next_halt = true;
341
342 if (*dscr & ARM11_DSCR_CORE_HALTED)
343 {
344 /** \todo TODO: this needs further scrutiny because
345 * arm11_on_enter_debug_state() never gets properly called.
346 * As a result we don't read the actual register states from
347 * the target.
348 */
349
350 arm11->target->state = TARGET_HALTED;
351 arm11->target->debug_reason = arm11_get_DSCR_debug_reason(*dscr);
352 }
353 else
354 {
355 arm11->target->state = TARGET_RUNNING;
356 arm11->target->debug_reason = DBG_REASON_NOTHALTED;
357 }
358
359 arm11_sc7_clear_vbw(arm11);
360 }
361
362 return ERROR_OK;
363 }
364
365
366
367 #define R(x) \
368 (arm11->reg_values[ARM11_RC_##x])
369
370 /** Save processor state.
371 *
372 * This is called when the HALT instruction has succeeded
373 * or on other occasions that stop the processor.
374 *
375 */
376 static int arm11_on_enter_debug_state(arm11_common_t * arm11)
377 {
378 int retval;
379 FNC_INFO;
380
381 for (size_t i = 0; i < asizeof(arm11->reg_values); i++)
382 {
383 arm11->reg_list[i].valid = 1;
384 arm11->reg_list[i].dirty = 0;
385 }
386
387 /* Save DSCR */
388 CHECK_RETVAL(arm11_read_DSCR(arm11, &R(DSCR)));
389
390 /* Save wDTR */
391
392 if (R(DSCR) & ARM11_DSCR_WDTR_FULL)
393 {
394 arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
395
396 arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
397
398 scan_field_t chain5_fields[3];
399
400 arm11_setup_field(arm11, 32, NULL, &R(WDTR), chain5_fields + 0);
401 arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 1);
402 arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 2);
403
404 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
405 }
406 else
407 {
408 arm11->reg_list[ARM11_RC_WDTR].valid = 0;
409 }
410
411
412 /* DSCR: set ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE */
413 /* ARM1176 spec says this is needed only for wDTR/rDTR's "ITR mode", but not to issue ITRs
414 ARM1136 seems to require this to issue ITR's as well */
415
416 uint32_t new_dscr = R(DSCR) | ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE;
417
418 /* this executes JTAG queue: */
419
420 arm11_write_DSCR(arm11, new_dscr);
421
422
423 /* From the spec:
424 Before executing any instruction in debug state you have to drain the write buffer.
425 This ensures that no imprecise Data Aborts can return at a later point:*/
426
427 /** \todo TODO: Test drain write buffer. */
428
429 #if 0
430 while (1)
431 {
432 /* MRC p14,0,R0,c5,c10,0 */
433 // arm11_run_instr_no_data1(arm11, /*0xee150e1a*/0xe320f000);
434
435 /* mcr 15, 0, r0, cr7, cr10, {4} */
436 arm11_run_instr_no_data1(arm11, 0xee070f9a);
437
438 uint32_t dscr = arm11_read_DSCR(arm11);
439
440 LOG_DEBUG("DRAIN, DSCR %08x", dscr);
441
442 if (dscr & ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT)
443 {
444 arm11_run_instr_no_data1(arm11, 0xe320f000);
445
446 dscr = arm11_read_DSCR(arm11);
447
448 LOG_DEBUG("DRAIN, DSCR %08x (DONE)", dscr);
449
450 break;
451 }
452 }
453 #endif
454
455 retval = arm11_run_instr_data_prepare(arm11);
456 if (retval != ERROR_OK)
457 return retval;
458
459 /* save r0 - r14 */
460
461 /** \todo TODO: handle other mode registers */
462
463 for (size_t i = 0; i < 15; i++)
464 {
465 /* MCR p14,0,R?,c0,c5,0 */
466 retval = arm11_run_instr_data_from_core(arm11, 0xEE000E15 | (i << 12), &R(RX + i), 1);
467 if (retval != ERROR_OK)
468 return retval;
469 }
470
471 /* save rDTR */
472
473 /* check rDTRfull in DSCR */
474
475 if (R(DSCR) & ARM11_DSCR_RDTR_FULL)
476 {
477 /* MRC p14,0,R0,c0,c5,0 (move rDTR -> r0 (-> wDTR -> local var)) */
478 retval = arm11_run_instr_data_from_core_via_r0(arm11, 0xEE100E15, &R(RDTR));
479 if (retval != ERROR_OK)
480 return retval;
481 }
482 else
483 {
484 arm11->reg_list[ARM11_RC_RDTR].valid = 0;
485 }
486
487 /* save CPSR */
488
489 /* MRS r0,CPSR (move CPSR -> r0 (-> wDTR -> local var)) */
490 retval = arm11_run_instr_data_from_core_via_r0(arm11, 0xE10F0000, &R(CPSR));
491 if (retval != ERROR_OK)
492 return retval;
493
494 /* save PC */
495
496 /* MOV R0,PC (move PC -> r0 (-> wDTR -> local var)) */
497 retval = arm11_run_instr_data_from_core_via_r0(arm11, 0xE1A0000F, &R(PC));
498 if (retval != ERROR_OK)
499 return retval;
500
501 /* adjust PC depending on ARM state */
502
503 if (R(CPSR) & ARM11_CPSR_J) /* Java state */
504 {
505 arm11->reg_values[ARM11_RC_PC] -= 0;
506 }
507 else if (R(CPSR) & ARM11_CPSR_T) /* Thumb state */
508 {
509 arm11->reg_values[ARM11_RC_PC] -= 4;
510 }
511 else /* ARM state */
512 {
513 arm11->reg_values[ARM11_RC_PC] -= 8;
514 }
515
516 if (arm11->simulate_reset_on_next_halt)
517 {
518 arm11->simulate_reset_on_next_halt = false;
519
520 LOG_DEBUG("Reset c1 Control Register");
521
522 /* Write 0 (reset value) to Control register 0 to disable MMU/Cache etc. */
523
524 /* MCR p15,0,R0,c1,c0,0 */
525 retval = arm11_run_instr_data_to_core_via_r0(arm11, 0xee010f10, 0);
526 if (retval != ERROR_OK)
527 return retval;
528
529 }
530
531 retval = arm11_run_instr_data_finish(arm11);
532 if (retval != ERROR_OK)
533 return retval;
534
535 arm11_dump_reg_changes(arm11);
536
537 return ERROR_OK;
538 }
539
540 void arm11_dump_reg_changes(arm11_common_t * arm11)
541 {
542
543 if (!(debug_level >= LOG_LVL_DEBUG))
544 {
545 return;
546 }
547
548 for (size_t i = 0; i < ARM11_REGCACHE_COUNT; i++)
549 {
550 if (!arm11->reg_list[i].valid)
551 {
552 if (arm11->reg_history[i].valid)
553 LOG_DEBUG("%8s INVALID (%08" PRIx32 ")", arm11_reg_defs[i].name, arm11->reg_history[i].value);
554 }
555 else
556 {
557 if (arm11->reg_history[i].valid)
558 {
559 if (arm11->reg_history[i].value != arm11->reg_values[i])
560 LOG_DEBUG("%8s %08" PRIx32 " (%08" PRIx32 ")", arm11_reg_defs[i].name, arm11->reg_values[i], arm11->reg_history[i].value);
561 }
562 else
563 {
564 LOG_DEBUG("%8s %08" PRIx32 " (INVALID)", arm11_reg_defs[i].name, arm11->reg_values[i]);
565 }
566 }
567 }
568 }
569
570 /** Restore processor state
571 *
572 * This is called in preparation for the RESTART function.
573 *
574 */
575 int arm11_leave_debug_state(arm11_common_t * arm11)
576 {
577 FNC_INFO;
578 int retval;
579
580 retval = arm11_run_instr_data_prepare(arm11);
581 if (retval != ERROR_OK)
582 return retval;
583
584 /** \todo TODO: handle other mode registers */
585
586 /* restore R1 - R14 */
587
588 for (size_t i = 1; i < 15; i++)
589 {
590 if (!arm11->reg_list[ARM11_RC_RX + i].dirty)
591 continue;
592
593 /* MRC p14,0,r?,c0,c5,0 */
594 arm11_run_instr_data_to_core1(arm11, 0xee100e15 | (i << 12), R(RX + i));
595
596 // LOG_DEBUG("RESTORE R" ZU " %08x", i, R(RX + i));
597 }
598
599 retval = arm11_run_instr_data_finish(arm11);
600 if (retval != ERROR_OK)
601 return retval;
602
603 /* spec says clear wDTR and rDTR; we assume they are clear as
604 otherwise our programming would be sloppy */
605 {
606 uint32_t DSCR;
607
608 CHECK_RETVAL(arm11_read_DSCR(arm11, &DSCR));
609
610 if (DSCR & (ARM11_DSCR_RDTR_FULL | ARM11_DSCR_WDTR_FULL))
611 {
612 LOG_ERROR("wDTR/rDTR inconsistent (DSCR %08" PRIx32 ")", DSCR);
613 }
614 }
615
616 retval = arm11_run_instr_data_prepare(arm11);
617 if (retval != ERROR_OK)
618 return retval;
619
620 /* restore original wDTR */
621
622 if ((R(DSCR) & ARM11_DSCR_WDTR_FULL) || arm11->reg_list[ARM11_RC_WDTR].dirty)
623 {
624 /* MCR p14,0,R0,c0,c5,0 */
625 retval = arm11_run_instr_data_to_core_via_r0(arm11, 0xee000e15, R(WDTR));
626 if (retval != ERROR_OK)
627 return retval;
628 }
629
630 /* restore CPSR */
631
632 /* MSR CPSR,R0*/
633 retval = arm11_run_instr_data_to_core_via_r0(arm11, 0xe129f000, R(CPSR));
634 if (retval != ERROR_OK)
635 return retval;
636
637
638 /* restore PC */
639
640 /* MOV PC,R0 */
641 retval = arm11_run_instr_data_to_core_via_r0(arm11, 0xe1a0f000, R(PC));
642 if (retval != ERROR_OK)
643 return retval;
644
645
646 /* restore R0 */
647
648 /* MRC p14,0,r0,c0,c5,0 */
649 arm11_run_instr_data_to_core1(arm11, 0xee100e15, R(R0));
650
651 retval = arm11_run_instr_data_finish(arm11);
652 if (retval != ERROR_OK)
653 return retval;
654
655 /* restore DSCR */
656
657 arm11_write_DSCR(arm11, R(DSCR));
658
659 /* restore rDTR */
660
661 if (R(DSCR) & ARM11_DSCR_RDTR_FULL || arm11->reg_list[ARM11_RC_RDTR].dirty)
662 {
663 arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
664
665 arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT);
666
667 scan_field_t chain5_fields[3];
668
669 uint8_t Ready = 0; /* ignored */
670 uint8_t Valid = 0; /* ignored */
671
672 arm11_setup_field(arm11, 32, &R(RDTR), NULL, chain5_fields + 0);
673 arm11_setup_field(arm11, 1, &Ready, NULL, chain5_fields + 1);
674 arm11_setup_field(arm11, 1, &Valid, NULL, chain5_fields + 2);
675
676 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
677 }
678
679 arm11_record_register_history(arm11);
680
681 return ERROR_OK;
682 }
683
684 void arm11_record_register_history(arm11_common_t * arm11)
685 {
686 for (size_t i = 0; i < ARM11_REGCACHE_COUNT; i++)
687 {
688 arm11->reg_history[i].value = arm11->reg_values[i];
689 arm11->reg_history[i].valid = arm11->reg_list[i].valid;
690
691 arm11->reg_list[i].valid = 0;
692 arm11->reg_list[i].dirty = 0;
693 }
694 }
695
696
697 /* poll current target status */
698 int arm11_poll(struct target_s *target)
699 {
700 FNC_INFO;
701 int retval;
702
703 arm11_common_t * arm11 = target->arch_info;
704
705 if (arm11->trst_active)
706 return ERROR_OK;
707
708 uint32_t dscr;
709
710 CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
711
712 LOG_DEBUG("DSCR %08" PRIx32 "", dscr);
713
714 CHECK_RETVAL(arm11_check_init(arm11, &dscr));
715
716 if (dscr & ARM11_DSCR_CORE_HALTED)
717 {
718 if (target->state != TARGET_HALTED)
719 {
720 enum target_state old_state = target->state;
721
722 LOG_DEBUG("enter TARGET_HALTED");
723 target->state = TARGET_HALTED;
724 target->debug_reason = arm11_get_DSCR_debug_reason(dscr);
725 retval = arm11_on_enter_debug_state(arm11);
726 if (retval != ERROR_OK)
727 return retval;
728
729 target_call_event_callbacks(target,
730 old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED);
731 }
732 }
733 else
734 {
735 if (target->state != TARGET_RUNNING && target->state != TARGET_DEBUG_RUNNING)
736 {
737 LOG_DEBUG("enter TARGET_RUNNING");
738 target->state = TARGET_RUNNING;
739 target->debug_reason = DBG_REASON_NOTHALTED;
740 }
741 }
742
743 return ERROR_OK;
744 }
745 /* architecture specific status reply */
746 int arm11_arch_state(struct target_s *target)
747 {
748 arm11_common_t * arm11 = target->arch_info;
749
750 LOG_USER("target halted due to %s\ncpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "",
751 Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name,
752 R(CPSR),
753 R(PC));
754
755 return ERROR_OK;
756 }
757
758 /* target request support */
759 int arm11_target_request_data(struct target_s *target, uint32_t size, uint8_t *buffer)
760 {
761 FNC_INFO_NOTIMPLEMENTED;
762
763 return ERROR_OK;
764 }
765
766 /* target execution control */
767 int arm11_halt(struct target_s *target)
768 {
769 FNC_INFO;
770
771 arm11_common_t * arm11 = target->arch_info;
772
773 LOG_DEBUG("target->state: %s",
774 target_state_name(target));
775
776 if (target->state == TARGET_UNKNOWN)
777 {
778 arm11->simulate_reset_on_next_halt = true;
779 }
780
781 if (target->state == TARGET_HALTED)
782 {
783 LOG_DEBUG("target was already halted");
784 return ERROR_OK;
785 }
786
787 if (arm11->trst_active)
788 {
789 arm11->halt_requested = true;
790 return ERROR_OK;
791 }
792
793 arm11_add_IR(arm11, ARM11_HALT, TAP_IDLE);
794
795 CHECK_RETVAL(jtag_execute_queue());
796
797 uint32_t dscr;
798
799 int i = 0;
800 while (1)
801 {
802 CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
803
804 if (dscr & ARM11_DSCR_CORE_HALTED)
805 break;
806
807
808 long long then = 0;
809 if (i == 1000)
810 {
811 then = timeval_ms();
812 }
813 if (i >= 1000)
814 {
815 if ((timeval_ms()-then) > 1000)
816 {
817 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
818 return ERROR_FAIL;
819 }
820 }
821 i++;
822 }
823
824 arm11_on_enter_debug_state(arm11);
825
826 enum target_state old_state = target->state;
827
828 target->state = TARGET_HALTED;
829 target->debug_reason = arm11_get_DSCR_debug_reason(dscr);
830
831 CHECK_RETVAL(
832 target_call_event_callbacks(target,
833 old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED));
834
835 return ERROR_OK;
836 }
837
838 int arm11_resume(struct target_s *target, int current, uint32_t address, int handle_breakpoints, int debug_execution)
839 {
840 FNC_INFO;
841
842 // LOG_DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d",
843 // current, address, handle_breakpoints, debug_execution);
844
845 arm11_common_t * arm11 = target->arch_info;
846
847 LOG_DEBUG("target->state: %s",
848 target_state_name(target));
849
850
851 if (target->state != TARGET_HALTED)
852 {
853 LOG_ERROR("Target not halted");
854 return ERROR_TARGET_NOT_HALTED;
855 }
856
857 if (!current)
858 R(PC) = address;
859
860 LOG_DEBUG("RESUME PC %08" PRIx32 "%s", R(PC), !current ? "!" : "");
861
862 /* clear breakpoints/watchpoints and VCR*/
863 arm11_sc7_clear_vbw(arm11);
864
865 /* Set up breakpoints */
866 if (!debug_execution)
867 {
868 /* check if one matches PC and step over it if necessary */
869
870 breakpoint_t * bp;
871
872 for (bp = target->breakpoints; bp; bp = bp->next)
873 {
874 if (bp->address == R(PC))
875 {
876 LOG_DEBUG("must step over %08" PRIx32 "", bp->address);
877 arm11_step(target, 1, 0, 0);
878 break;
879 }
880 }
881
882 /* set all breakpoints */
883
884 size_t brp_num = 0;
885
886 for (bp = target->breakpoints; bp; bp = bp->next)
887 {
888 arm11_sc7_action_t brp[2];
889
890 brp[0].write = 1;
891 brp[0].address = ARM11_SC7_BVR0 + brp_num;
892 brp[0].value = bp->address;
893 brp[1].write = 1;
894 brp[1].address = ARM11_SC7_BCR0 + brp_num;
895 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
896
897 arm11_sc7_run(arm11, brp, asizeof(brp));
898
899 LOG_DEBUG("Add BP " ZU " at %08" PRIx32 "", brp_num, bp->address);
900
901 brp_num++;
902 }
903
904 arm11_sc7_set_vcr(arm11, arm11_vcr);
905 }
906
907 arm11_leave_debug_state(arm11);
908
909 arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
910
911 CHECK_RETVAL(jtag_execute_queue());
912
913 int i = 0;
914 while (1)
915 {
916 uint32_t dscr;
917
918 CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
919
920 LOG_DEBUG("DSCR %08" PRIx32 "", dscr);
921
922 if (dscr & ARM11_DSCR_CORE_RESTARTED)
923 break;
924
925
926 long long then = 0;
927 if (i == 1000)
928 {
929 then = timeval_ms();
930 }
931 if (i >= 1000)
932 {
933 if ((timeval_ms()-then) > 1000)
934 {
935 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
936 return ERROR_FAIL;
937 }
938 }
939 i++;
940 }
941
942 if (!debug_execution)
943 {
944 target->state = TARGET_RUNNING;
945 target->debug_reason = DBG_REASON_NOTHALTED;
946
947 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
948 }
949 else
950 {
951 target->state = TARGET_DEBUG_RUNNING;
952 target->debug_reason = DBG_REASON_NOTHALTED;
953
954 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
955 }
956
957 return ERROR_OK;
958 }
959
960
961 static int armv4_5_to_arm11(int reg)
962 {
963 if (reg < 16)
964 return reg;
965 switch (reg)
966 {
967 case ARMV4_5_CPSR:
968 return ARM11_RC_CPSR;
969 case 16:
970 /* FIX!!! handle thumb better! */
971 return ARM11_RC_CPSR;
972 default:
973 LOG_ERROR("BUG: register translation from armv4_5 to arm11 not supported %d", reg);
974 exit(-1);
975 }
976 }
977
978
979 static uint32_t arm11_sim_get_reg(struct arm_sim_interface *sim, int reg)
980 {
981 arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
982
983 reg=armv4_5_to_arm11(reg);
984
985 return buf_get_u32(arm11->reg_list[reg].value, 0, 32);
986 }
987
988 static void arm11_sim_set_reg(struct arm_sim_interface *sim, int reg, uint32_t value)
989 {
990 arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
991
992 reg=armv4_5_to_arm11(reg);
993
994 buf_set_u32(arm11->reg_list[reg].value, 0, 32, value);
995 }
996
997 static uint32_t arm11_sim_get_cpsr(struct arm_sim_interface *sim, int pos, int bits)
998 {
999 arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
1000
1001 return buf_get_u32(arm11->reg_list[ARM11_RC_CPSR].value, pos, bits);
1002 }
1003
1004 static enum armv4_5_state arm11_sim_get_state(struct arm_sim_interface *sim)
1005 {
1006 // arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
1007
1008 /* FIX!!!! we should implement thumb for arm11 */
1009 return ARMV4_5_STATE_ARM;
1010 }
1011
1012 static void arm11_sim_set_state(struct arm_sim_interface *sim, enum armv4_5_state mode)
1013 {
1014 // arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
1015
1016 /* FIX!!!! we should implement thumb for arm11 */
1017 LOG_ERROR("Not implemetned!");
1018 }
1019
1020
1021 static enum armv4_5_mode arm11_sim_get_mode(struct arm_sim_interface *sim)
1022 {
1023 //arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
1024
1025 /* FIX!!!! we should implement something that returns the current mode here!!! */
1026 return ARMV4_5_MODE_USR;
1027 }
1028
1029 static int arm11_simulate_step(target_t *target, uint32_t *dry_run_pc)
1030 {
1031 struct arm_sim_interface sim;
1032
1033 sim.user_data=target->arch_info;
1034 sim.get_reg=&arm11_sim_get_reg;
1035 sim.set_reg=&arm11_sim_set_reg;
1036 sim.get_reg_mode=&arm11_sim_get_reg;
1037 sim.set_reg_mode=&arm11_sim_set_reg;
1038 sim.get_cpsr=&arm11_sim_get_cpsr;
1039 sim.get_mode=&arm11_sim_get_mode;
1040 sim.get_state=&arm11_sim_get_state;
1041 sim.set_state=&arm11_sim_set_state;
1042
1043 return arm_simulate_step_core(target, dry_run_pc, &sim);
1044
1045 }
1046
1047 int arm11_step(struct target_s *target, int current, uint32_t address, int handle_breakpoints)
1048 {
1049 FNC_INFO;
1050
1051 LOG_DEBUG("target->state: %s",
1052 target_state_name(target));
1053
1054 if (target->state != TARGET_HALTED)
1055 {
1056 LOG_WARNING("target was not halted");
1057 return ERROR_TARGET_NOT_HALTED;
1058 }
1059
1060 arm11_common_t * arm11 = target->arch_info;
1061
1062 if (!current)
1063 R(PC) = address;
1064
1065 LOG_DEBUG("STEP PC %08" PRIx32 "%s", R(PC), !current ? "!" : "");
1066
1067
1068 /** \todo TODO: Thumb not supported here */
1069
1070 uint32_t next_instruction;
1071
1072 CHECK_RETVAL(arm11_read_memory_word(arm11, R(PC), &next_instruction));
1073
1074 /* skip over BKPT */
1075 if ((next_instruction & 0xFFF00070) == 0xe1200070)
1076 {
1077 R(PC) += 4;
1078 arm11->reg_list[ARM11_RC_PC].valid = 1;
1079 arm11->reg_list[ARM11_RC_PC].dirty = 0;
1080 LOG_DEBUG("Skipping BKPT");
1081 }
1082 /* skip over Wait for interrupt / Standby */
1083 /* mcr 15, 0, r?, cr7, cr0, {4} */
1084 else if ((next_instruction & 0xFFFF0FFF) == 0xee070f90)
1085 {
1086 R(PC) += 4;
1087 arm11->reg_list[ARM11_RC_PC].valid = 1;
1088 arm11->reg_list[ARM11_RC_PC].dirty = 0;
1089 LOG_DEBUG("Skipping WFI");
1090 }
1091 /* ignore B to self */
1092 else if ((next_instruction & 0xFEFFFFFF) == 0xeafffffe)
1093 {
1094 LOG_DEBUG("Not stepping jump to self");
1095 }
1096 else
1097 {
1098 /** \todo TODO: check if break-/watchpoints make any sense at all in combination
1099 * with this. */
1100
1101 /** \todo TODO: check if disabling IRQs might be a good idea here. Alternatively
1102 * the VCR might be something worth looking into. */
1103
1104
1105 /* Set up breakpoint for stepping */
1106
1107 arm11_sc7_action_t brp[2];
1108
1109 brp[0].write = 1;
1110 brp[0].address = ARM11_SC7_BVR0;
1111 brp[1].write = 1;
1112 brp[1].address = ARM11_SC7_BCR0;
1113
1114 if (arm11_config_hardware_step)
1115 {
1116 /* hardware single stepping be used if possible or is it better to
1117 * always use the same code path? Hardware single stepping is not supported
1118 * on all hardware
1119 */
1120 brp[0].value = R(PC);
1121 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (2 << 21);
1122 } else
1123 {
1124 /* sets a breakpoint on the next PC(calculated by simulation),
1125 */
1126 uint32_t next_pc;
1127 int retval;
1128 retval = arm11_simulate_step(target, &next_pc);
1129 if (retval != ERROR_OK)
1130 return retval;
1131
1132 brp[0].value = next_pc;
1133 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
1134 }
1135
1136 CHECK_RETVAL(arm11_sc7_run(arm11, brp, asizeof(brp)));
1137
1138 /* resume */
1139
1140
1141 if (arm11_config_step_irq_enable)
1142 R(DSCR) &= ~ARM11_DSCR_INTERRUPTS_DISABLE; /* should be redundant */
1143 else
1144 R(DSCR) |= ARM11_DSCR_INTERRUPTS_DISABLE;
1145
1146
1147 CHECK_RETVAL(arm11_leave_debug_state(arm11));
1148
1149 arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
1150
1151 CHECK_RETVAL(jtag_execute_queue());
1152
1153 /* wait for halt */
1154 int i = 0;
1155 while (1)
1156 {
1157 uint32_t dscr;
1158
1159 CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
1160
1161 LOG_DEBUG("DSCR %08" PRIx32 "e", dscr);
1162
1163 if ((dscr & (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED)) ==
1164 (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED))
1165 break;
1166
1167 long long then = 0;
1168 if (i == 1000)
1169 {
1170 then = timeval_ms();
1171 }
1172 if (i >= 1000)
1173 {
1174 if ((timeval_ms()-then) > 1000)
1175 {
1176 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
1177 return ERROR_FAIL;
1178 }
1179 }
1180 i++;
1181 }
1182
1183 /* clear breakpoint */
1184 arm11_sc7_clear_vbw(arm11);
1185
1186 /* save state */
1187 CHECK_RETVAL(arm11_on_enter_debug_state(arm11));
1188
1189 /* restore default state */
1190 R(DSCR) &= ~ARM11_DSCR_INTERRUPTS_DISABLE;
1191
1192 }
1193
1194 // target->state = TARGET_HALTED;
1195 target->debug_reason = DBG_REASON_SINGLESTEP;
1196
1197 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_HALTED));
1198
1199 return ERROR_OK;
1200 }
1201
1202 /* target reset control */
1203 int arm11_assert_reset(struct target_s *target)
1204 {
1205 FNC_INFO;
1206
1207 #if 0
1208 /* assert reset lines */
1209 /* resets only the DBGTAP, not the ARM */
1210
1211 jtag_add_reset(1, 0);
1212 jtag_add_sleep(5000);
1213
1214 arm11_common_t * arm11 = target->arch_info;
1215 arm11->trst_active = true;
1216 #endif
1217
1218 if (target->reset_halt)
1219 {
1220 CHECK_RETVAL(target_halt(target));
1221 }
1222
1223 return ERROR_OK;
1224 }
1225
1226 int arm11_deassert_reset(struct target_s *target)
1227 {
1228 FNC_INFO;
1229
1230 #if 0
1231 LOG_DEBUG("target->state: %s",
1232 target_state_name(target));
1233
1234
1235 /* deassert reset lines */
1236 jtag_add_reset(0, 0);
1237
1238 arm11_common_t * arm11 = target->arch_info;
1239 arm11->trst_active = false;
1240
1241 if (arm11->halt_requested)
1242 return arm11_halt(target);
1243 #endif
1244
1245 return ERROR_OK;
1246 }
1247
1248 int arm11_soft_reset_halt(struct target_s *target)
1249 {
1250 FNC_INFO_NOTIMPLEMENTED;
1251
1252 return ERROR_OK;
1253 }
1254
1255 /* target register access for gdb */
1256 int arm11_get_gdb_reg_list(struct target_s *target, struct reg_s **reg_list[], int *reg_list_size)
1257 {
1258 FNC_INFO;
1259
1260 arm11_common_t * arm11 = target->arch_info;
1261
1262 *reg_list_size = ARM11_GDB_REGISTER_COUNT;
1263 *reg_list = malloc(sizeof(reg_t*) * ARM11_GDB_REGISTER_COUNT);
1264
1265 for (size_t i = 16; i < 24; i++)
1266 {
1267 (*reg_list)[i] = &arm11_gdb_dummy_fp_reg;
1268 }
1269
1270 (*reg_list)[24] = &arm11_gdb_dummy_fps_reg;
1271
1272 for (size_t i = 0; i < ARM11_REGCACHE_COUNT; i++)
1273 {
1274 if (arm11_reg_defs[i].gdb_num == -1)
1275 continue;
1276
1277 (*reg_list)[arm11_reg_defs[i].gdb_num] = arm11->reg_list + i;
1278 }
1279
1280 return ERROR_OK;
1281 }
1282
1283 /* target memory access
1284 * size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
1285 * count: number of items of <size>
1286 */
1287 int arm11_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
1288 {
1289 /** \todo TODO: check if buffer cast to uint32_t* and uint16_t* might cause alignment problems */
1290 int retval;
1291
1292 FNC_INFO;
1293
1294 if (target->state != TARGET_HALTED)
1295 {
1296 LOG_WARNING("target was not halted");
1297 return ERROR_TARGET_NOT_HALTED;
1298 }
1299
1300 LOG_DEBUG("ADDR %08" PRIx32 " SIZE %08" PRIx32 " COUNT %08" PRIx32 "", address, size, count);
1301
1302 arm11_common_t * arm11 = target->arch_info;
1303
1304 retval = arm11_run_instr_data_prepare(arm11);
1305 if (retval != ERROR_OK)
1306 return retval;
1307
1308 /* MRC p14,0,r0,c0,c5,0 */
1309 retval = arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
1310 if (retval != ERROR_OK)
1311 return retval;
1312
1313 switch (size)
1314 {
1315 case 1:
1316 /** \todo TODO: check if dirty is the right choice to force a rewrite on arm11_resume() */
1317 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1318
1319 for (size_t i = 0; i < count; i++)
1320 {
1321 /* ldrb r1, [r0], #1 */
1322 /* ldrb r1, [r0] */
1323 arm11_run_instr_no_data1(arm11,
1324 !arm11_config_memrw_no_increment ? 0xe4d01001 : 0xe5d01000);
1325
1326 uint32_t res;
1327 /* MCR p14,0,R1,c0,c5,0 */
1328 arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
1329
1330 *buffer++ = res;
1331 }
1332
1333 break;
1334
1335 case 2:
1336 {
1337 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1338
1339 for (size_t i = 0; i < count; i++)
1340 {
1341 /* ldrh r1, [r0], #2 */
1342 arm11_run_instr_no_data1(arm11,
1343 !arm11_config_memrw_no_increment ? 0xe0d010b2 : 0xe1d010b0);
1344
1345 uint32_t res;
1346
1347 /* MCR p14,0,R1,c0,c5,0 */
1348 arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
1349
1350 uint16_t svalue = res;
1351 memcpy(buffer + i * sizeof(uint16_t), &svalue, sizeof(uint16_t));
1352 }
1353
1354 break;
1355 }
1356
1357 case 4:
1358 {
1359 uint32_t instr = !arm11_config_memrw_no_increment ? 0xecb05e01 : 0xed905e00;
1360 /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
1361 uint32_t *words = (uint32_t *)buffer;
1362
1363 /* LDC p14,c5,[R0],#4 */
1364 /* LDC p14,c5,[R0] */
1365 arm11_run_instr_data_from_core(arm11, instr, words, count);
1366 break;
1367 }
1368 }
1369
1370 return arm11_run_instr_data_finish(arm11);
1371 }
1372
1373 int arm11_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
1374 {
1375 int retval;
1376 FNC_INFO;
1377
1378 if (target->state != TARGET_HALTED)
1379 {
1380 LOG_WARNING("target was not halted");
1381 return ERROR_TARGET_NOT_HALTED;
1382 }
1383
1384 LOG_DEBUG("ADDR %08" PRIx32 " SIZE %08" PRIx32 " COUNT %08" PRIx32 "", address, size, count);
1385
1386 arm11_common_t * arm11 = target->arch_info;
1387
1388 arm11_run_instr_data_prepare(arm11);
1389
1390 /* MRC p14,0,r0,c0,c5,0 */
1391 retval = arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
1392 if (retval != ERROR_OK)
1393 return retval;
1394
1395 switch (size)
1396 {
1397 case 1:
1398 {
1399 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1400
1401 for (size_t i = 0; i < count; i++)
1402 {
1403 /* MRC p14,0,r1,c0,c5,0 */
1404 retval = arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buffer++);
1405 if (retval != ERROR_OK)
1406 return retval;
1407
1408 /* strb r1, [r0], #1 */
1409 /* strb r1, [r0] */
1410 retval = arm11_run_instr_no_data1(arm11,
1411 !arm11_config_memrw_no_increment ? 0xe4c01001 : 0xe5c01000);
1412 if (retval != ERROR_OK)
1413 return retval;
1414 }
1415
1416 break;
1417 }
1418
1419 case 2:
1420 {
1421 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1422
1423 for (size_t i = 0; i < count; i++)
1424 {
1425 uint16_t value;
1426 memcpy(&value, buffer + i * sizeof(uint16_t), sizeof(uint16_t));
1427
1428 /* MRC p14,0,r1,c0,c5,0 */
1429 retval = arm11_run_instr_data_to_core1(arm11, 0xee101e15, value);
1430 if (retval != ERROR_OK)
1431 return retval;
1432
1433 /* strh r1, [r0], #2 */
1434 /* strh r1, [r0] */
1435 retval = arm11_run_instr_no_data1(arm11,
1436 !arm11_config_memrw_no_increment ? 0xe0c010b2 : 0xe1c010b0);
1437 if (retval != ERROR_OK)
1438 return retval;
1439 }
1440
1441 break;
1442 }
1443
1444 case 4: {
1445 uint32_t instr = !arm11_config_memrw_no_increment ? 0xeca05e01 : 0xed805e00;
1446
1447 /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
1448 uint32_t *words = (uint32_t*)buffer;
1449
1450 if (!arm11_config_memwrite_burst)
1451 {
1452 /* STC p14,c5,[R0],#4 */
1453 /* STC p14,c5,[R0]*/
1454 retval = arm11_run_instr_data_to_core(arm11, instr, words, count);
1455 if (retval != ERROR_OK)
1456 return retval;
1457 }
1458 else
1459 {
1460 /* STC p14,c5,[R0],#4 */
1461 /* STC p14,c5,[R0]*/
1462 retval = arm11_run_instr_data_to_core_noack(arm11, instr, words, count);
1463 if (retval != ERROR_OK)
1464 return retval;
1465 }
1466
1467 break;
1468 }
1469 }
1470
1471 /* r0 verification */
1472 if (!arm11_config_memrw_no_increment)
1473 {
1474 uint32_t r0;
1475
1476 /* MCR p14,0,R0,c0,c5,0 */
1477 retval = arm11_run_instr_data_from_core(arm11, 0xEE000E15, &r0, 1);
1478 if (retval != ERROR_OK)
1479 return retval;
1480
1481 if (address + size * count != r0)
1482 {
1483 LOG_ERROR("Data transfer failed. Expected end address 0x%08x, got 0x%08x",
1484 address + size * count, r0);
1485
1486 if (arm11_config_memwrite_burst)
1487 LOG_ERROR("use 'arm11 memwrite burst disable' to disable fast burst mode");
1488
1489 if (arm11_config_memwrite_error_fatal)
1490 return ERROR_FAIL;
1491 }
1492 }
1493
1494 return arm11_run_instr_data_finish(arm11);
1495 }
1496
1497
1498 /* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
1499 int arm11_bulk_write_memory(struct target_s *target, uint32_t address, uint32_t count, uint8_t *buffer)
1500 {
1501 FNC_INFO;
1502
1503 if (target->state != TARGET_HALTED)
1504 {
1505 LOG_WARNING("target was not halted");
1506 return ERROR_TARGET_NOT_HALTED;
1507 }
1508
1509 return arm11_write_memory(target, address, 4, count, buffer);
1510 }
1511
1512 /* here we have nothing target specific to contribute, so we fail and then the
1513 * fallback code will read data from the target and calculate the CRC on the
1514 * host.
1515 */
1516 int arm11_checksum_memory(struct target_s *target, uint32_t address, uint32_t count, uint32_t* checksum)
1517 {
1518 return ERROR_FAIL;
1519 }
1520
1521 /* target break-/watchpoint control
1522 * rw: 0 = write, 1 = read, 2 = access
1523 */
1524 int arm11_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
1525 {
1526 FNC_INFO;
1527
1528 arm11_common_t * arm11 = target->arch_info;
1529
1530 #if 0
1531 if (breakpoint->type == BKPT_SOFT)
1532 {
1533 LOG_INFO("sw breakpoint requested, but software breakpoints not enabled");
1534 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1535 }
1536 #endif
1537
1538 if (!arm11->free_brps)
1539 {
1540 LOG_DEBUG("no breakpoint unit available for hardware breakpoint");
1541 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1542 }
1543
1544 if (breakpoint->length != 4)
1545 {
1546 LOG_DEBUG("only breakpoints of four bytes length supported");
1547 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1548 }
1549
1550 arm11->free_brps--;
1551
1552 return ERROR_OK;
1553 }
1554
1555 int arm11_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
1556 {
1557 FNC_INFO;
1558
1559 arm11_common_t * arm11 = target->arch_info;
1560
1561 arm11->free_brps++;
1562
1563 return ERROR_OK;
1564 }
1565
1566 int arm11_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
1567 {
1568 FNC_INFO_NOTIMPLEMENTED;
1569
1570 return ERROR_OK;
1571 }
1572
1573 int arm11_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
1574 {
1575 FNC_INFO_NOTIMPLEMENTED;
1576
1577 return ERROR_OK;
1578 }
1579
1580 // HACKHACKHACK - FIXME mode/state
1581 /* target algorithm support */
1582 int arm11_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params,
1583 int num_reg_params, reg_param_t *reg_params, uint32_t entry_point, uint32_t exit_point,
1584 int timeout_ms, void *arch_info)
1585 {
1586 arm11_common_t *arm11 = target->arch_info;
1587 // enum armv4_5_state core_state = arm11->core_state;
1588 // enum armv4_5_mode core_mode = arm11->core_mode;
1589 uint32_t context[16];
1590 uint32_t cpsr;
1591 int exit_breakpoint_size = 0;
1592 int retval = ERROR_OK;
1593 LOG_DEBUG("Running algorithm");
1594
1595
1596 if (target->state != TARGET_HALTED)
1597 {
1598 LOG_WARNING("target not halted");
1599 return ERROR_TARGET_NOT_HALTED;
1600 }
1601
1602 // FIXME
1603 // if (armv4_5_mode_to_number(arm11->core_mode)==-1)
1604 // return ERROR_FAIL;
1605
1606 // Save regs
1607 for (size_t i = 0; i < 16; i++)
1608 {
1609 context[i] = buf_get_u32((uint8_t*)(&arm11->reg_values[i]),0,32);
1610 LOG_DEBUG("Save %zi: 0x%" PRIx32 "",i,context[i]);
1611 }
1612
1613 cpsr = buf_get_u32((uint8_t*)(arm11->reg_values + ARM11_RC_CPSR),0,32);
1614 LOG_DEBUG("Save CPSR: 0x%" PRIx32 "", cpsr);
1615
1616 for (int i = 0; i < num_mem_params; i++)
1617 {
1618 target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
1619 }
1620
1621 // Set register parameters
1622 for (int i = 0; i < num_reg_params; i++)
1623 {
1624 reg_t *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0);
1625 if (!reg)
1626 {
1627 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
1628 exit(-1);
1629 }
1630
1631 if (reg->size != reg_params[i].size)
1632 {
1633 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
1634 exit(-1);
1635 }
1636 arm11_set_reg(reg,reg_params[i].value);
1637 // printf("%i: Set %s =%08x\n", i, reg_params[i].reg_name,val);
1638 }
1639
1640 exit_breakpoint_size = 4;
1641
1642 /* arm11->core_state = arm11_algorithm_info->core_state;
1643 if (arm11->core_state == ARMV4_5_STATE_ARM)
1644 exit_breakpoint_size = 4;
1645 else if (arm11->core_state == ARMV4_5_STATE_THUMB)
1646 exit_breakpoint_size = 2;
1647 else
1648 {
1649 LOG_ERROR("BUG: can't execute algorithms when not in ARM or Thumb state");
1650 exit(-1);
1651 }
1652 */
1653
1654
1655 /* arm11 at this point only supports ARM not THUMB mode
1656 however if this test needs to be reactivated the current state can be read back
1657 from CPSR */
1658 #if 0
1659 if (arm11_algorithm_info->core_mode != ARMV4_5_MODE_ANY)
1660 {
1661 LOG_DEBUG("setting core_mode: 0x%2.2x", arm11_algorithm_info->core_mode);
1662 buf_set_u32(arm11->reg_list[ARM11_RC_CPSR].value, 0, 5, arm11_algorithm_info->core_mode);
1663 arm11->reg_list[ARM11_RC_CPSR].dirty = 1;
1664 arm11->reg_list[ARM11_RC_CPSR].valid = 1;
1665 }
1666 #endif
1667
1668 if ((retval = breakpoint_add(target, exit_point, exit_breakpoint_size, BKPT_HARD)) != ERROR_OK)
1669 {
1670 LOG_ERROR("can't add breakpoint to finish algorithm execution");
1671 retval = ERROR_TARGET_FAILURE;
1672 goto restore;
1673 }
1674
1675 // no debug, otherwise breakpoint is not set
1676 CHECK_RETVAL(target_resume(target, 0, entry_point, 1, 0));
1677
1678 CHECK_RETVAL(target_wait_state(target, TARGET_HALTED, timeout_ms));
1679
1680 if (target->state != TARGET_HALTED)
1681 {
1682 CHECK_RETVAL(target_halt(target));
1683
1684 CHECK_RETVAL(target_wait_state(target, TARGET_HALTED, 500));
1685
1686 retval = ERROR_TARGET_TIMEOUT;
1687
1688 goto del_breakpoint;
1689 }
1690
1691 if (buf_get_u32(arm11->reg_list[15].value, 0, 32) != exit_point)
1692 {
1693 LOG_WARNING("target reentered debug state, but not at the desired exit point: 0x%4.4" PRIx32 "",
1694 buf_get_u32(arm11->reg_list[15].value, 0, 32));
1695 retval = ERROR_TARGET_TIMEOUT;
1696 goto del_breakpoint;
1697 }
1698
1699 for (int i = 0; i < num_mem_params; i++)
1700 {
1701 if (mem_params[i].direction != PARAM_OUT)
1702 target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
1703 }
1704
1705 for (int i = 0; i < num_reg_params; i++)
1706 {
1707 if (reg_params[i].direction != PARAM_OUT)
1708 {
1709 reg_t *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0);
1710 if (!reg)
1711 {
1712 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
1713 exit(-1);
1714 }
1715
1716 if (reg->size != reg_params[i].size)
1717 {
1718 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
1719 exit(-1);
1720 }
1721
1722 buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
1723 }
1724 }
1725
1726 del_breakpoint:
1727 breakpoint_remove(target, exit_point);
1728
1729 restore:
1730 // Restore context
1731 for (size_t i = 0; i < 16; i++)
1732 {
1733 LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32 "",
1734 arm11->reg_list[i].name, context[i]);
1735 arm11_set_reg(&arm11->reg_list[i], (uint8_t*)&context[i]);
1736 }
1737 LOG_DEBUG("restoring CPSR with value 0x%8.8" PRIx32 "", cpsr);
1738 arm11_set_reg(&arm11->reg_list[ARM11_RC_CPSR], (uint8_t*)&cpsr);
1739
1740 // arm11->core_state = core_state;
1741 // arm11->core_mode = core_mode;
1742
1743 return retval;
1744 }
1745
1746 int arm11_target_create(struct target_s *target, Jim_Interp *interp)
1747 {
1748 FNC_INFO;
1749
1750 NEW(arm11_common_t, arm11, 1);
1751
1752 arm11->target = target;
1753
1754 if (target->tap == NULL)
1755 return ERROR_FAIL;
1756
1757 if (target->tap->ir_length != 5)
1758 {
1759 LOG_ERROR("'target arm11' expects IR LENGTH = 5");
1760 return ERROR_COMMAND_SYNTAX_ERROR;
1761 }
1762
1763 target->arch_info = arm11;
1764
1765 return ERROR_OK;
1766 }
1767
1768 int arm11_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
1769 {
1770 /* Initialize anything we can set up without talking to the target */
1771 return arm11_build_reg_cache(target);
1772 }
1773
1774 /* talk to the target and set things up */
1775 int arm11_examine(struct target_s *target)
1776 {
1777 FNC_INFO;
1778
1779 arm11_common_t * arm11 = target->arch_info;
1780
1781 /* check IDCODE */
1782
1783 arm11_add_IR(arm11, ARM11_IDCODE, ARM11_TAP_DEFAULT);
1784
1785 scan_field_t idcode_field;
1786
1787 arm11_setup_field(arm11, 32, NULL, &arm11->device_id, &idcode_field);
1788
1789 arm11_add_dr_scan_vc(1, &idcode_field, TAP_DRPAUSE);
1790
1791 /* check DIDR */
1792
1793 arm11_add_debug_SCAN_N(arm11, 0x00, ARM11_TAP_DEFAULT);
1794
1795 arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
1796
1797 scan_field_t chain0_fields[2];
1798
1799 arm11_setup_field(arm11, 32, NULL, &arm11->didr, chain0_fields + 0);
1800 arm11_setup_field(arm11, 8, NULL, &arm11->implementor, chain0_fields + 1);
1801
1802 arm11_add_dr_scan_vc(asizeof(chain0_fields), chain0_fields, TAP_IDLE);
1803
1804 CHECK_RETVAL(jtag_execute_queue());
1805
1806 switch (arm11->device_id & 0x0FFFF000)
1807 {
1808 case 0x07B36000: LOG_INFO("found ARM1136"); break;
1809 case 0x07B56000: LOG_INFO("found ARM1156"); break;
1810 case 0x07B76000: LOG_INFO("found ARM1176"); break;
1811 default:
1812 {
1813 LOG_ERROR("'target arm11' expects IDCODE 0x*7B*7****");
1814 return ERROR_FAIL;
1815 }
1816 }
1817
1818 arm11->debug_version = (arm11->didr >> 16) & 0x0F;
1819
1820 if (arm11->debug_version != ARM11_DEBUG_V6 &&
1821 arm11->debug_version != ARM11_DEBUG_V61)
1822 {
1823 LOG_ERROR("Only ARMv6 v6 and v6.1 architectures supported.");
1824 return ERROR_FAIL;
1825 }
1826
1827 arm11->brp = ((arm11->didr >> 24) & 0x0F) + 1;
1828 arm11->wrp = ((arm11->didr >> 28) & 0x0F) + 1;
1829
1830 /** \todo TODO: reserve one brp slot if we allow breakpoints during step */
1831 arm11->free_brps = arm11->brp;
1832 arm11->free_wrps = arm11->wrp;
1833
1834 LOG_DEBUG("IDCODE %08" PRIx32 " IMPLEMENTOR %02x DIDR %08" PRIx32 "",
1835 arm11->device_id,
1836 (int)(arm11->implementor),
1837 arm11->didr);
1838
1839 /* as a side-effect this reads DSCR and thus
1840 * clears the ARM11_DSCR_STICKY_PRECISE_DATA_ABORT / Sticky Precise Data Abort Flag
1841 * as suggested by the spec.
1842 */
1843
1844 arm11_check_init(arm11, NULL);
1845
1846 target_set_examined(target);
1847
1848 return ERROR_OK;
1849 }
1850
1851 int arm11_quit(void)
1852 {
1853 FNC_INFO_NOTIMPLEMENTED;
1854
1855 return ERROR_OK;
1856 }
1857
1858 /** Load a register that is marked !valid in the register cache */
1859 int arm11_get_reg(reg_t *reg)
1860 {
1861 FNC_INFO;
1862
1863 target_t * target = ((arm11_reg_state_t *)reg->arch_info)->target;
1864
1865 if (target->state != TARGET_HALTED)
1866 {
1867 LOG_WARNING("target was not halted");
1868 return ERROR_TARGET_NOT_HALTED;
1869 }
1870
1871 /** \todo TODO: Check this. We assume that all registers are fetched at debug entry. */
1872
1873 #if 0
1874 arm11_common_t *arm11 = target->arch_info;
1875 const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index;
1876 #endif
1877
1878 return ERROR_OK;
1879 }
1880
1881 /** Change a value in the register cache */
1882 int arm11_set_reg(reg_t *reg, uint8_t *buf)
1883 {
1884 FNC_INFO;
1885
1886 target_t * target = ((arm11_reg_state_t *)reg->arch_info)->target;
1887 arm11_common_t *arm11 = target->arch_info;
1888 // const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index;
1889
1890 arm11->reg_values[((arm11_reg_state_t *)reg->arch_info)->def_index] = buf_get_u32(buf, 0, 32);
1891 reg->valid = 1;
1892 reg->dirty = 1;
1893
1894 return ERROR_OK;
1895 }
1896
1897 int arm11_build_reg_cache(target_t *target)
1898 {
1899 arm11_common_t *arm11 = target->arch_info;
1900
1901 NEW(reg_cache_t, cache, 1);
1902 NEW(reg_t, reg_list, ARM11_REGCACHE_COUNT);
1903 NEW(arm11_reg_state_t, arm11_reg_states, ARM11_REGCACHE_COUNT);
1904
1905 if (arm11_regs_arch_type == -1)
1906 arm11_regs_arch_type = register_reg_arch_type(arm11_get_reg, arm11_set_reg);
1907
1908 register_init_dummy(&arm11_gdb_dummy_fp_reg);
1909 register_init_dummy(&arm11_gdb_dummy_fps_reg);
1910
1911 arm11->reg_list = reg_list;
1912
1913 /* Build the process context cache */
1914 cache->name = "arm11 registers";
1915 cache->next = NULL;
1916 cache->reg_list = reg_list;
1917 cache->num_regs = ARM11_REGCACHE_COUNT;
1918
1919 reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
1920 (*cache_p) = cache;
1921
1922 arm11->core_cache = cache;
1923 // armv7m->process_context = cache;
1924
1925 size_t i;
1926
1927 /* Not very elegant assertion */
1928 if (ARM11_REGCACHE_COUNT != asizeof(arm11->reg_values) ||
1929 ARM11_REGCACHE_COUNT != asizeof(arm11_reg_defs) ||
1930 ARM11_REGCACHE_COUNT != ARM11_RC_MAX)
1931 {
1932 LOG_ERROR("BUG: arm11->reg_values inconsistent (%d " ZU " " ZU " %d)", ARM11_REGCACHE_COUNT, asizeof(arm11->reg_values), asizeof(arm11_reg_defs), ARM11_RC_MAX);
1933 exit(-1);
1934 }
1935
1936 for (i = 0; i < ARM11_REGCACHE_COUNT; i++)
1937 {
1938 reg_t * r = reg_list + i;
1939 const arm11_reg_defs_t * rd = arm11_reg_defs + i;
1940 arm11_reg_state_t * rs = arm11_reg_states + i;
1941
1942 r->name = rd->name;
1943 r->size = 32;
1944 r->value = (uint8_t *)(arm11->reg_values + i);
1945 r->dirty = 0;
1946 r->valid = 0;
1947 r->bitfield_desc = NULL;
1948 r->num_bitfields = 0;
1949 r->arch_type = arm11_regs_arch_type;
1950 r->arch_info = rs;
1951
1952 rs->def_index = i;
1953 rs->target = target;
1954 }
1955
1956 return ERROR_OK;
1957 }
1958
1959 int arm11_handle_bool(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, bool * var, char * name)
1960 {
1961 if (argc == 0)
1962 {
1963 LOG_INFO("%s is %s.", name, *var ? "enabled" : "disabled");
1964 return ERROR_OK;
1965 }
1966
1967 if (argc != 1)
1968 return ERROR_COMMAND_SYNTAX_ERROR;
1969
1970 switch (args[0][0])
1971 {
1972 case '0': /* 0 */
1973 case 'f': /* false */
1974 case 'F':
1975 case 'd': /* disable */
1976 case 'D':
1977 *var = false;
1978 break;
1979
1980 case '1': /* 1 */
1981 case 't': /* true */
1982 case 'T':
1983 case 'e': /* enable */
1984 case 'E':
1985 *var = true;
1986 break;
1987 }
1988
1989 LOG_INFO("%s %s.", *var ? "Enabled" : "Disabled", name);
1990
1991 return ERROR_OK;
1992 }
1993
1994 #define BOOL_WRAPPER(name, print_name) \
1995 int arm11_handle_bool_##name(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) \
1996 { \
1997 return arm11_handle_bool(cmd_ctx, cmd, args, argc, &arm11_config_##name, print_name); \
1998 }
1999
2000 BOOL_WRAPPER(memwrite_burst, "memory write burst mode")
2001 BOOL_WRAPPER(memwrite_error_fatal, "fatal error mode for memory writes")
2002 BOOL_WRAPPER(memrw_no_increment, "\"no increment\" mode for memory transfers")
2003 BOOL_WRAPPER(step_irq_enable, "IRQs while stepping")
2004 BOOL_WRAPPER(hardware_step, "hardware single step")
2005
2006 int arm11_handle_vcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2007 {
2008 if (argc == 1)
2009 {
2010 arm11_vcr = strtoul(args[0], NULL, 0);
2011 }
2012 else if (argc != 0)
2013 {
2014 return ERROR_COMMAND_SYNTAX_ERROR;
2015 }
2016
2017 LOG_INFO("VCR 0x%08" PRIx32 "", arm11_vcr);
2018 return ERROR_OK;
2019 }
2020
2021 const uint32_t arm11_coproc_instruction_limits[] =
2022 {
2023 15, /* coprocessor */
2024 7, /* opcode 1 */
2025 15, /* CRn */
2026 15, /* CRm */
2027 7, /* opcode 2 */
2028 0xFFFFFFFF, /* value */
2029 };
2030
2031 arm11_common_t * arm11_find_target(const char * arg)
2032 {
2033 jtag_tap_t * tap;
2034 target_t * t;
2035
2036 tap = jtag_tap_by_string(arg);
2037
2038 if (!tap)
2039 return 0;
2040
2041 for (t = all_targets; t; t = t->next)
2042 {
2043 if (t->tap != tap)
2044 continue;
2045
2046 /* if (t->type == arm11_target) */
2047 if (0 == strcmp(target_get_name(t), "arm11"))
2048 return t->arch_info;
2049 }
2050
2051 return 0;
2052 }
2053
2054 int arm11_handle_mrc_mcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, bool read)
2055 {
2056 int retval;
2057
2058 if (argc != (read ? 6 : 7))
2059 {
2060 LOG_ERROR("Invalid number of arguments.");
2061 return ERROR_COMMAND_SYNTAX_ERROR;
2062 }
2063
2064 arm11_common_t * arm11 = arm11_find_target(args[0]);
2065
2066 if (!arm11)
2067 {
2068 LOG_ERROR("Parameter 1 is not a the JTAG chain position of an ARM11 device.");
2069 return ERROR_COMMAND_SYNTAX_ERROR;
2070 }
2071
2072 if (arm11->target->state != TARGET_HALTED)
2073 {
2074 LOG_WARNING("target was not halted");
2075 return ERROR_TARGET_NOT_HALTED;
2076 }
2077
2078 uint32_t values[6];
2079
2080 for (size_t i = 0; i < (read ? 5 : 6); i++)
2081 {
2082 values[i] = strtoul(args[i + 1], NULL, 0);
2083
2084 if (values[i] > arm11_coproc_instruction_limits[i])
2085 {
2086 LOG_ERROR("Parameter %ld out of bounds (%" PRId32 " max).",
2087 (long)(i + 2),
2088 arm11_coproc_instruction_limits[i]);
2089 return ERROR_COMMAND_SYNTAX_ERROR;
2090 }
2091 }
2092
2093 uint32_t instr = 0xEE000010 |
2094 (values[0] << 8) |
2095 (values[1] << 21) |
2096 (values[2] << 16) |
2097 (values[3] << 0) |
2098 (values[4] << 5);
2099
2100 if (read)
2101 instr |= 0x00100000;
2102
2103 retval = arm11_run_instr_data_prepare(arm11);
2104 if (retval != ERROR_OK)
2105 return retval;
2106
2107 if (read)
2108 {
2109 uint32_t result;
2110 retval = arm11_run_instr_data_from_core_via_r0(arm11, instr, &result);
2111 if (retval != ERROR_OK)
2112 return retval;
2113
2114 LOG_INFO("MRC p%d, %d, R0, c%d, c%d, %d = 0x%08" PRIx32 " (%" PRId32 ")",
2115 (int)(values[0]),
2116 (int)(values[1]),
2117 (int)(values[2]),
2118 (int)(values[3]),
2119 (int)(values[4]), result, result);
2120 }
2121 else
2122 {
2123 retval = arm11_run_instr_data_to_core_via_r0(arm11, instr, values[5]);
2124 if (retval != ERROR_OK)
2125 return retval;
2126
2127 LOG_INFO("MRC p%d, %d, R0 (#0x%08" PRIx32 "), c%d, c%d, %d",
2128 (int)(values[0]), (int)(values[1]),
2129 values[5],
2130 (int)(values[2]), (int)(values[3]), (int)(values[4]));
2131 }
2132
2133 return arm11_run_instr_data_finish(arm11);
2134 }
2135
2136 int arm11_handle_mrc(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2137 {
2138 return arm11_handle_mrc_mcr(cmd_ctx, cmd, args, argc, true);
2139 }
2140
2141 int arm11_handle_mcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2142 {
2143 return arm11_handle_mrc_mcr(cmd_ctx, cmd, args, argc, false);
2144 }
2145
2146 int arm11_register_commands(struct command_context_s *cmd_ctx)
2147 {
2148 FNC_INFO;
2149
2150 command_t *top_cmd, *mw_cmd;
2151
2152 top_cmd = register_command(cmd_ctx, NULL, "arm11",
2153 NULL, COMMAND_ANY, NULL);
2154
2155 /* "hardware_step" is only here to check if the default
2156 * simulate + breakpoint implementation is broken.
2157 * TEMPORARY! NOT DOCUMENTED!
2158 */
2159 register_command(cmd_ctx, top_cmd, "hardware_step",
2160 arm11_handle_bool_hardware_step, COMMAND_ANY,
2161 "DEBUG ONLY - Hardware single stepping"
2162 " (default: disabled)");
2163
2164 register_command(cmd_ctx, top_cmd, "mcr",
2165 arm11_handle_mcr, COMMAND_ANY,
2166 "Write Coprocessor register. mcr <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2> <32bit value to write>. All parameters are numbers only.");
2167
2168 mw_cmd = register_command(cmd_ctx, top_cmd, "memwrite",
2169 NULL, COMMAND_ANY, NULL);
2170 register_command(cmd_ctx, mw_cmd, "burst",
2171 arm11_handle_bool_memwrite_burst, COMMAND_ANY,
2172 "Enable/Disable non-standard but fast burst mode"
2173 " (default: enabled)");
2174 register_command(cmd_ctx, mw_cmd, "error_fatal",
2175 arm11_handle_bool_memwrite_error_fatal, COMMAND_ANY,
2176 "Terminate program if transfer error was found"
2177 " (default: enabled)");
2178
2179 register_command(cmd_ctx, top_cmd, "mrc",
2180 arm11_handle_mrc, COMMAND_ANY,
2181 "Read Coprocessor register. mrc <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2>. All parameters are numbers only.");
2182 register_command(cmd_ctx, top_cmd, "no_increment",
2183 arm11_handle_bool_memrw_no_increment, COMMAND_ANY,
2184 "Don't increment address on multi-read/-write"
2185 " (default: disabled)");
2186 register_command(cmd_ctx, top_cmd, "step_irq_enable",
2187 arm11_handle_bool_step_irq_enable, COMMAND_ANY,
2188 "Enable interrupts while stepping"
2189 " (default: disabled)");
2190 register_command(cmd_ctx, top_cmd, "vcr",
2191 arm11_handle_vcr, COMMAND_ANY,
2192 "Control (Interrupt) Vector Catch Register");
2193
2194 return ERROR_OK;
2195 }
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