build: cleanup src/target directory
[openocd.git] / src / target / arm11.c
1 /***************************************************************************
2 * Copyright (C) 2008 digenius technology GmbH. *
3 * Michael Bruck *
4 * *
5 * Copyright (C) 2008,2009 Oyvind Harboe oyvind.harboe@zylin.com *
6 * *
7 * Copyright (C) 2008 Georg Acher <acher@in.tum.de> *
8 * *
9 * Copyright (C) 2009 David Brownell *
10 * *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
26
27 #ifdef HAVE_CONFIG_H
28 #include "config.h"
29 #endif
30
31 #include "etm.h"
32 #include "breakpoints.h"
33 #include "arm11_dbgtap.h"
34 #include "arm_simulator.h"
35 #include <helper/time_support.h>
36 #include "target_type.h"
37 #include "algorithm.h"
38 #include "register.h"
39 #include "arm_opcodes.h"
40
41 #if 0
42 #define _DEBUG_INSTRUCTION_EXECUTION_
43 #endif
44
45
46 static int arm11_step(struct target *target, int current,
47 uint32_t address, int handle_breakpoints);
48
49
50 /** Check and if necessary take control of the system
51 *
52 * \param arm11 Target state variable.
53 */
54 static int arm11_check_init(struct arm11_common *arm11)
55 {
56 CHECK_RETVAL(arm11_read_DSCR(arm11));
57
58 if (!(arm11->dscr & DSCR_HALT_DBG_MODE)) {
59 LOG_DEBUG("DSCR %08x", (unsigned) arm11->dscr);
60 LOG_DEBUG("Bringing target into debug mode");
61
62 arm11->dscr |= DSCR_HALT_DBG_MODE;
63 CHECK_RETVAL(arm11_write_DSCR(arm11, arm11->dscr));
64
65 /* add further reset initialization here */
66
67 arm11->simulate_reset_on_next_halt = true;
68
69 if (arm11->dscr & DSCR_CORE_HALTED) {
70 /** \todo TODO: this needs further scrutiny because
71 * arm11_debug_entry() never gets called. (WHY NOT?)
72 * As a result we don't read the actual register states from
73 * the target.
74 */
75
76 arm11->arm.target->state = TARGET_HALTED;
77 arm_dpm_report_dscr(arm11->arm.dpm, arm11->dscr);
78 } else {
79 arm11->arm.target->state = TARGET_RUNNING;
80 arm11->arm.target->debug_reason = DBG_REASON_NOTHALTED;
81 }
82
83 CHECK_RETVAL(arm11_sc7_clear_vbw(arm11));
84 }
85
86 return ERROR_OK;
87 }
88
89 /**
90 * Save processor state. This is called after a HALT instruction
91 * succeeds, and on other occasions the processor enters debug mode
92 * (breakpoint, watchpoint, etc). Caller has updated arm11->dscr.
93 */
94 static int arm11_debug_entry(struct arm11_common *arm11)
95 {
96 int retval;
97
98 arm11->arm.target->state = TARGET_HALTED;
99 arm_dpm_report_dscr(arm11->arm.dpm, arm11->dscr);
100
101 /* REVISIT entire cache should already be invalid !!! */
102 register_cache_invalidate(arm11->arm.core_cache);
103
104 /* See e.g. ARM1136 TRM, "14.8.4 Entering Debug state" */
105
106 /* maybe save wDTR (pending DCC write to debug SW, e.g. libdcc) */
107 arm11->is_wdtr_saved = !!(arm11->dscr & DSCR_DTR_TX_FULL);
108 if (arm11->is_wdtr_saved) {
109 arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
110
111 arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
112
113 struct scan_field chain5_fields[3];
114
115 arm11_setup_field(arm11, 32, NULL,
116 &arm11->saved_wdtr, chain5_fields + 0);
117 arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 1);
118 arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 2);
119
120 arm11_add_dr_scan_vc(arm11->arm.target->tap, ARRAY_SIZE(
121 chain5_fields), chain5_fields, TAP_DRPAUSE);
122
123 }
124
125 /* DSCR: set the Execute ARM instruction enable bit.
126 *
127 * ARM1176 spec says this is needed only for wDTR/rDTR's "ITR mode",
128 * but not to issue ITRs(?). The ARMv7 arch spec says it's required
129 * for executing instructions via ITR.
130 */
131 CHECK_RETVAL(arm11_write_DSCR(arm11, DSCR_ITR_EN | arm11->dscr));
132
133
134 /* From the spec:
135 Before executing any instruction in debug state you have to drain the write buffer.
136 This ensures that no imprecise Data Aborts can return at a later point:*/
137
138 /** \todo TODO: Test drain write buffer. */
139
140 #if 0
141 while (1) {
142 /* MRC p14,0,R0,c5,c10,0 */
143 /* arm11_run_instr_no_data1(arm11, / *0xee150e1a* /0xe320f000); */
144
145 /* mcr 15, 0, r0, cr7, cr10, {4} */
146 arm11_run_instr_no_data1(arm11, 0xee070f9a);
147
148 uint32_t dscr = arm11_read_DSCR(arm11);
149
150 LOG_DEBUG("DRAIN, DSCR %08x", dscr);
151
152 if (dscr & ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT) {
153 arm11_run_instr_no_data1(arm11, 0xe320f000);
154
155 dscr = arm11_read_DSCR(arm11);
156
157 LOG_DEBUG("DRAIN, DSCR %08x (DONE)", dscr);
158
159 break;
160 }
161 }
162 #endif
163
164 /* Save registers.
165 *
166 * NOTE: ARM1136 TRM suggests saving just R0 here now, then
167 * CPSR and PC after the rDTR stuff. We do it all at once.
168 */
169 retval = arm_dpm_read_current_registers(&arm11->dpm);
170 if (retval != ERROR_OK)
171 LOG_ERROR("DPM REG READ -- fail");
172
173 retval = arm11_run_instr_data_prepare(arm11);
174 if (retval != ERROR_OK)
175 return retval;
176
177 /* maybe save rDTR (pending DCC read from debug SW, e.g. libdcc) */
178 arm11->is_rdtr_saved = !!(arm11->dscr & DSCR_DTR_RX_FULL);
179 if (arm11->is_rdtr_saved) {
180 /* MRC p14,0,R0,c0,c5,0 (move rDTR -> r0 (-> wDTR -> local var)) */
181 retval = arm11_run_instr_data_from_core_via_r0(arm11,
182 0xEE100E15, &arm11->saved_rdtr);
183 if (retval != ERROR_OK)
184 return retval;
185 }
186
187 /* REVISIT Now that we've saved core state, there's may also
188 * be MMU and cache state to care about ...
189 */
190
191 if (arm11->simulate_reset_on_next_halt) {
192 arm11->simulate_reset_on_next_halt = false;
193
194 LOG_DEBUG("Reset c1 Control Register");
195
196 /* Write 0 (reset value) to Control register 0 to disable MMU/Cache etc. */
197
198 /* MCR p15,0,R0,c1,c0,0 */
199 retval = arm11_run_instr_data_to_core_via_r0(arm11, 0xee010f10, 0);
200 if (retval != ERROR_OK)
201 return retval;
202
203 }
204
205 if (arm11->arm.target->debug_reason == DBG_REASON_WATCHPOINT) {
206 uint32_t wfar;
207
208 /* MRC p15, 0, <Rd>, c6, c0, 1 ; Read WFAR */
209 retval = arm11_run_instr_data_from_core_via_r0(arm11,
210 ARMV4_5_MRC(15, 0, 0, 6, 0, 1),
211 &wfar);
212 if (retval != ERROR_OK)
213 return retval;
214 arm_dpm_report_wfar(arm11->arm.dpm, wfar);
215 }
216
217
218 retval = arm11_run_instr_data_finish(arm11);
219 if (retval != ERROR_OK)
220 return retval;
221
222 return ERROR_OK;
223 }
224
225 /**
226 * Restore processor state. This is called in preparation for
227 * the RESTART function.
228 */
229 static int arm11_leave_debug_state(struct arm11_common *arm11, bool bpwp)
230 {
231 int retval;
232
233 /* See e.g. ARM1136 TRM, "14.8.5 Leaving Debug state" */
234
235 /* NOTE: the ARM1136 TRM suggests restoring all registers
236 * except R0/PC/CPSR right now. Instead, we do them all
237 * at once, just a bit later on.
238 */
239
240 /* REVISIT once we start caring about MMU and cache state,
241 * address it here ...
242 */
243
244 /* spec says clear wDTR and rDTR; we assume they are clear as
245 otherwise our programming would be sloppy */
246 {
247 CHECK_RETVAL(arm11_read_DSCR(arm11));
248
249 if (arm11->dscr & (DSCR_DTR_RX_FULL | DSCR_DTR_TX_FULL)) {
250 /*
251 The wDTR/rDTR two registers that are used to send/receive data to/from
252 the core in tandem with corresponding instruction codes that are
253 written into the core. The RDTR FULL/WDTR FULL flag indicates that the
254 registers hold data that was written by one side (CPU or JTAG) and not
255 read out by the other side.
256 */
257 LOG_ERROR("wDTR/rDTR inconsistent (DSCR %08x)",
258 (unsigned) arm11->dscr);
259 return ERROR_FAIL;
260 }
261 }
262
263 /* maybe restore original wDTR */
264 if (arm11->is_wdtr_saved) {
265 retval = arm11_run_instr_data_prepare(arm11);
266 if (retval != ERROR_OK)
267 return retval;
268
269 /* MCR p14,0,R0,c0,c5,0 */
270 retval = arm11_run_instr_data_to_core_via_r0(arm11,
271 0xee000e15, arm11->saved_wdtr);
272 if (retval != ERROR_OK)
273 return retval;
274
275 retval = arm11_run_instr_data_finish(arm11);
276 if (retval != ERROR_OK)
277 return retval;
278 }
279
280 /* restore CPSR, PC, and R0 ... after flushing any modified
281 * registers.
282 */
283 CHECK_RETVAL(arm_dpm_write_dirty_registers(&arm11->dpm, bpwp));
284
285 CHECK_RETVAL(arm11_bpwp_flush(arm11));
286
287 register_cache_invalidate(arm11->arm.core_cache);
288
289 /* restore DSCR */
290 CHECK_RETVAL(arm11_write_DSCR(arm11, arm11->dscr));
291
292 /* maybe restore rDTR */
293 if (arm11->is_rdtr_saved) {
294 arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
295
296 arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT);
297
298 struct scan_field chain5_fields[3];
299
300 uint8_t Ready = 0; /* ignored */
301 uint8_t Valid = 0; /* ignored */
302
303 arm11_setup_field(arm11, 32, &arm11->saved_rdtr,
304 NULL, chain5_fields + 0);
305 arm11_setup_field(arm11, 1, &Ready, NULL, chain5_fields + 1);
306 arm11_setup_field(arm11, 1, &Valid, NULL, chain5_fields + 2);
307
308 arm11_add_dr_scan_vc(arm11->arm.target->tap, ARRAY_SIZE(
309 chain5_fields), chain5_fields, TAP_DRPAUSE);
310 }
311
312 /* now processor is ready to RESTART */
313
314 return ERROR_OK;
315 }
316
317 /* poll current target status */
318 static int arm11_poll(struct target *target)
319 {
320 int retval;
321 struct arm11_common *arm11 = target_to_arm11(target);
322
323 CHECK_RETVAL(arm11_check_init(arm11));
324
325 if (arm11->dscr & DSCR_CORE_HALTED) {
326 if (target->state != TARGET_HALTED) {
327 enum target_state old_state = target->state;
328
329 LOG_DEBUG("enter TARGET_HALTED");
330 retval = arm11_debug_entry(arm11);
331 if (retval != ERROR_OK)
332 return retval;
333
334 target_call_event_callbacks(target,
335 (old_state == TARGET_DEBUG_RUNNING)
336 ? TARGET_EVENT_DEBUG_HALTED
337 : TARGET_EVENT_HALTED);
338 }
339 } else {
340 if (target->state != TARGET_RUNNING && target->state != TARGET_DEBUG_RUNNING) {
341 LOG_DEBUG("enter TARGET_RUNNING");
342 target->state = TARGET_RUNNING;
343 target->debug_reason = DBG_REASON_NOTHALTED;
344 }
345 }
346
347 return ERROR_OK;
348 }
349 /* architecture specific status reply */
350 static int arm11_arch_state(struct target *target)
351 {
352 struct arm11_common *arm11 = target_to_arm11(target);
353 int retval;
354
355 retval = arm_arch_state(target);
356
357 /* REVISIT also display ARM11-specific MMU and cache status ... */
358
359 if (target->debug_reason == DBG_REASON_WATCHPOINT)
360 LOG_USER("Watchpoint triggered at PC %#08x",
361 (unsigned) arm11->dpm.wp_pc);
362
363 return retval;
364 }
365
366 /* target request support */
367 static int arm11_target_request_data(struct target *target,
368 uint32_t size, uint8_t *buffer)
369 {
370 LOG_WARNING("Not implemented: %s", __func__);
371
372 return ERROR_FAIL;
373 }
374
375 /* target execution control */
376 static int arm11_halt(struct target *target)
377 {
378 struct arm11_common *arm11 = target_to_arm11(target);
379
380 LOG_DEBUG("target->state: %s",
381 target_state_name(target));
382
383 if (target->state == TARGET_UNKNOWN)
384 arm11->simulate_reset_on_next_halt = true;
385
386 if (target->state == TARGET_HALTED) {
387 LOG_DEBUG("target was already halted");
388 return ERROR_OK;
389 }
390
391 arm11_add_IR(arm11, ARM11_HALT, TAP_IDLE);
392
393 CHECK_RETVAL(jtag_execute_queue());
394
395 int i = 0;
396
397 while (1) {
398 CHECK_RETVAL(arm11_read_DSCR(arm11));
399
400 if (arm11->dscr & DSCR_CORE_HALTED)
401 break;
402
403
404 long long then = 0;
405 if (i == 1000)
406 then = timeval_ms();
407 if (i >= 1000) {
408 if ((timeval_ms()-then) > 1000) {
409 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
410 return ERROR_FAIL;
411 }
412 }
413 i++;
414 }
415
416 enum target_state old_state = target->state;
417
418 CHECK_RETVAL(arm11_debug_entry(arm11));
419
420 CHECK_RETVAL(
421 target_call_event_callbacks(target,
422 old_state ==
423 TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED));
424
425 return ERROR_OK;
426 }
427
428 static uint32_t arm11_nextpc(struct arm11_common *arm11, int current, uint32_t address)
429 {
430 void *value = arm11->arm.pc->value;
431
432 if (!current)
433 buf_set_u32(value, 0, 32, address);
434 else
435 address = buf_get_u32(value, 0, 32);
436
437 return address;
438 }
439
440 static int arm11_resume(struct target *target, int current,
441 uint32_t address, int handle_breakpoints, int debug_execution)
442 {
443 /* LOG_DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d", */
444 /* current, address, handle_breakpoints, debug_execution); */
445
446 struct arm11_common *arm11 = target_to_arm11(target);
447
448 LOG_DEBUG("target->state: %s",
449 target_state_name(target));
450
451
452 if (target->state != TARGET_HALTED) {
453 LOG_ERROR("Target not halted");
454 return ERROR_TARGET_NOT_HALTED;
455 }
456
457 address = arm11_nextpc(arm11, current, address);
458
459 LOG_DEBUG("RESUME PC %08" PRIx32 "%s", address, !current ? "!" : "");
460
461 /* clear breakpoints/watchpoints and VCR*/
462 CHECK_RETVAL(arm11_sc7_clear_vbw(arm11));
463
464 if (!debug_execution)
465 target_free_all_working_areas(target);
466
467 /* Should we skip over breakpoints matching the PC? */
468 if (handle_breakpoints) {
469 struct breakpoint *bp;
470
471 for (bp = target->breakpoints; bp; bp = bp->next) {
472 if (bp->address == address) {
473 LOG_DEBUG("must step over %08" PRIx32 "", bp->address);
474 arm11_step(target, 1, 0, 0);
475 break;
476 }
477 }
478 }
479
480 /* activate all breakpoints */
481 if (true) {
482 struct breakpoint *bp;
483 unsigned brp_num = 0;
484
485 for (bp = target->breakpoints; bp; bp = bp->next) {
486 struct arm11_sc7_action brp[2];
487
488 brp[0].write = 1;
489 brp[0].address = ARM11_SC7_BVR0 + brp_num;
490 brp[0].value = bp->address;
491 brp[1].write = 1;
492 brp[1].address = ARM11_SC7_BCR0 + brp_num;
493 brp[1].value = 0x1 |
494 (3 <<
495 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
496
497 CHECK_RETVAL(arm11_sc7_run(arm11, brp, ARRAY_SIZE(brp)));
498
499 LOG_DEBUG("Add BP %d at %08" PRIx32, brp_num,
500 bp->address);
501
502 brp_num++;
503 }
504
505 if (arm11->vcr)
506 CHECK_RETVAL(arm11_sc7_set_vcr(arm11, arm11->vcr));
507 }
508
509 /* activate all watchpoints and breakpoints */
510 CHECK_RETVAL(arm11_leave_debug_state(arm11, true));
511
512 arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
513
514 CHECK_RETVAL(jtag_execute_queue());
515
516 int i = 0;
517 while (1) {
518 CHECK_RETVAL(arm11_read_DSCR(arm11));
519
520 LOG_DEBUG("DSCR %08x", (unsigned) arm11->dscr);
521
522 if (arm11->dscr & DSCR_CORE_RESTARTED)
523 break;
524
525
526 long long then = 0;
527 if (i == 1000)
528 then = timeval_ms();
529 if (i >= 1000) {
530 if ((timeval_ms()-then) > 1000) {
531 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
532 return ERROR_FAIL;
533 }
534 }
535 i++;
536 }
537
538 target->debug_reason = DBG_REASON_NOTHALTED;
539 if (!debug_execution)
540 target->state = TARGET_RUNNING;
541 else
542 target->state = TARGET_DEBUG_RUNNING;
543 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
544
545 return ERROR_OK;
546 }
547
548 static int arm11_step(struct target *target, int current,
549 uint32_t address, int handle_breakpoints)
550 {
551 LOG_DEBUG("target->state: %s",
552 target_state_name(target));
553
554 if (target->state != TARGET_HALTED) {
555 LOG_WARNING("target was not halted");
556 return ERROR_TARGET_NOT_HALTED;
557 }
558
559 struct arm11_common *arm11 = target_to_arm11(target);
560
561 address = arm11_nextpc(arm11, current, address);
562
563 LOG_DEBUG("STEP PC %08" PRIx32 "%s", address, !current ? "!" : "");
564
565
566 /** \todo TODO: Thumb not supported here */
567
568 uint32_t next_instruction;
569
570 CHECK_RETVAL(arm11_read_memory_word(arm11, address, &next_instruction));
571
572 /* skip over BKPT */
573 if ((next_instruction & 0xFFF00070) == 0xe1200070) {
574 address = arm11_nextpc(arm11, 0, address + 4);
575 LOG_DEBUG("Skipping BKPT %08" PRIx32, address);
576 }
577 /* skip over Wait for interrupt / Standby
578 * mcr 15, 0, r?, cr7, cr0, {4} */
579 else if ((next_instruction & 0xFFFF0FFF) == 0xee070f90) {
580 address = arm11_nextpc(arm11, 0, address + 4);
581 LOG_DEBUG("Skipping WFI %08" PRIx32, address);
582 }
583 /* ignore B to self */
584 else if ((next_instruction & 0xFEFFFFFF) == 0xeafffffe)
585 LOG_DEBUG("Not stepping jump to self");
586 else {
587 /** \todo TODO: check if break-/watchpoints make any sense at all in combination
588 * with this. */
589
590 /** \todo TODO: check if disabling IRQs might be a good idea here. Alternatively
591 * the VCR might be something worth looking into. */
592
593
594 /* Set up breakpoint for stepping */
595
596 struct arm11_sc7_action brp[2];
597
598 brp[0].write = 1;
599 brp[0].address = ARM11_SC7_BVR0;
600 brp[1].write = 1;
601 brp[1].address = ARM11_SC7_BCR0;
602
603 if (arm11->hardware_step) {
604 /* Hardware single stepping ("instruction address
605 * mismatch") is used if enabled. It's not quite
606 * exactly "run one instruction"; "branch to here"
607 * loops won't break, neither will some other cases,
608 * but it's probably the best default.
609 *
610 * Hardware single stepping isn't supported on v6
611 * debug modules. ARM1176 and v7 can support it...
612 *
613 * FIXME Thumb stepping likely needs to use 0x03
614 * or 0xc0 byte masks, not 0x0f.
615 */
616 brp[0].value = address;
617 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5)
618 | (0 << 14) | (0 << 16) | (0 << 20)
619 | (2 << 21);
620 } else {
621 /* Sets a breakpoint on the next PC, as calculated
622 * by instruction set simulation.
623 *
624 * REVISIT stepping Thumb on ARM1156 requires Thumb2
625 * support from the simulator.
626 */
627 uint32_t next_pc;
628 int retval;
629
630 retval = arm_simulate_step(target, &next_pc);
631 if (retval != ERROR_OK)
632 return retval;
633
634 brp[0].value = next_pc;
635 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5)
636 | (0 << 14) | (0 << 16) | (0 << 20)
637 | (0 << 21);
638 }
639
640 CHECK_RETVAL(arm11_sc7_run(arm11, brp, ARRAY_SIZE(brp)));
641
642 /* resume */
643
644
645 if (arm11->step_irq_enable)
646 /* this disable should be redundant ... */
647 arm11->dscr &= ~DSCR_INT_DIS;
648 else
649 arm11->dscr |= DSCR_INT_DIS;
650
651
652 CHECK_RETVAL(arm11_leave_debug_state(arm11, handle_breakpoints));
653
654 arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
655
656 CHECK_RETVAL(jtag_execute_queue());
657
658 /* wait for halt */
659 int i = 0;
660
661 while (1) {
662 const uint32_t mask = DSCR_CORE_RESTARTED
663 | DSCR_CORE_HALTED;
664
665 CHECK_RETVAL(arm11_read_DSCR(arm11));
666 LOG_DEBUG("DSCR %08x e", (unsigned) arm11->dscr);
667
668 if ((arm11->dscr & mask) == mask)
669 break;
670
671 long long then = 0;
672 if (i == 1000)
673 then = timeval_ms();
674 if (i >= 1000) {
675 if ((timeval_ms()-then) > 1000) {
676 LOG_WARNING(
677 "Timeout (1000ms) waiting for instructions to complete");
678 return ERROR_FAIL;
679 }
680 }
681 i++;
682 }
683
684 /* clear breakpoint */
685 CHECK_RETVAL(arm11_sc7_clear_vbw(arm11));
686
687 /* save state */
688 CHECK_RETVAL(arm11_debug_entry(arm11));
689
690 /* restore default state */
691 arm11->dscr &= ~DSCR_INT_DIS;
692
693 }
694
695 target->debug_reason = DBG_REASON_SINGLESTEP;
696
697 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_HALTED));
698
699 return ERROR_OK;
700 }
701
702 static int arm11_assert_reset(struct target *target)
703 {
704 struct arm11_common *arm11 = target_to_arm11(target);
705
706 /* optionally catch reset vector */
707 if (target->reset_halt && !(arm11->vcr & 1))
708 CHECK_RETVAL(arm11_sc7_set_vcr(arm11, arm11->vcr | 1));
709
710 /* Issue some kind of warm reset. */
711 if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT))
712 target_handle_event(target, TARGET_EVENT_RESET_ASSERT);
713 else if (jtag_get_reset_config() & RESET_HAS_SRST) {
714 /* REVISIT handle "pulls" cases, if there's
715 * hardware that needs them to work.
716 */
717 jtag_add_reset(0, 1);
718 } else {
719 LOG_ERROR("%s: how to reset?", target_name(target));
720 return ERROR_FAIL;
721 }
722
723 /* registers are now invalid */
724 register_cache_invalidate(arm11->arm.core_cache);
725
726 target->state = TARGET_RESET;
727
728 return ERROR_OK;
729 }
730
731 /*
732 * - There is another bug in the arm11 core. (iMX31 specific again?)
733 * When you generate an access to external logic (for example DDR
734 * controller via AHB bus) and that block is not configured (perhaps
735 * it is still held in reset), that transaction will never complete.
736 * This will hang arm11 core but it will also hang JTAG controller.
737 * Nothing short of srst assertion will bring it out of this.
738 */
739
740 static int arm11_deassert_reset(struct target *target)
741 {
742 struct arm11_common *arm11 = target_to_arm11(target);
743 int retval;
744
745 /* be certain SRST is off */
746 jtag_add_reset(0, 0);
747
748 /* WORKAROUND i.MX31 problems: SRST goofs the TAP, and resets
749 * at least DSCR. OMAP24xx doesn't show that problem, though
750 * SRST-only reset seems to be problematic for other reasons.
751 * (Secure boot sequences being one likelihood!)
752 */
753 jtag_add_tlr();
754
755 CHECK_RETVAL(arm11_poll(target));
756
757 if (target->reset_halt) {
758 if (target->state != TARGET_HALTED) {
759 LOG_WARNING("%s: ran after reset and before halt ...",
760 target_name(target));
761 retval = target_halt(target);
762 if (retval != ERROR_OK)
763 return retval;
764 }
765 }
766
767 /* maybe restore vector catch config */
768 if (target->reset_halt && !(arm11->vcr & 1))
769 CHECK_RETVAL(arm11_sc7_set_vcr(arm11, arm11->vcr));
770
771 return ERROR_OK;
772 }
773
774 static int arm11_soft_reset_halt(struct target *target)
775 {
776 LOG_WARNING("Not implemented: %s", __func__);
777
778 return ERROR_FAIL;
779 }
780
781 /* target memory access
782 * size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
783 * count: number of items of <size>
784 *
785 * arm11_config_memrw_no_increment - in the future we may want to be able
786 * to read/write a range of data to a "port". a "port" is an action on
787 * read memory address for some peripheral.
788 */
789 static int arm11_read_memory_inner(struct target *target,
790 uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer,
791 bool arm11_config_memrw_no_increment)
792 {
793 /** \todo TODO: check if buffer cast to uint32_t* and uint16_t* might cause alignment
794 *problems */
795 int retval;
796
797 if (target->state != TARGET_HALTED) {
798 LOG_WARNING("target was not halted");
799 return ERROR_TARGET_NOT_HALTED;
800 }
801
802 LOG_DEBUG("ADDR %08" PRIx32 " SIZE %08" PRIx32 " COUNT %08" PRIx32 "",
803 address,
804 size,
805 count);
806
807 struct arm11_common *arm11 = target_to_arm11(target);
808
809 retval = arm11_run_instr_data_prepare(arm11);
810 if (retval != ERROR_OK)
811 return retval;
812
813 /* MRC p14,0,r0,c0,c5,0 */
814 retval = arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
815 if (retval != ERROR_OK)
816 return retval;
817
818 switch (size) {
819 case 1:
820 arm11->arm.core_cache->reg_list[1].dirty = true;
821
822 for (size_t i = 0; i < count; i++) {
823 /* ldrb r1, [r0], #1 */
824 /* ldrb r1, [r0] */
825 CHECK_RETVAL(arm11_run_instr_no_data1(arm11,
826 !arm11_config_memrw_no_increment ? 0xe4d01001 : 0xe5d01000));
827
828 uint32_t res;
829 /* MCR p14,0,R1,c0,c5,0 */
830 CHECK_RETVAL(arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1));
831
832 *buffer++ = res;
833 }
834
835 break;
836
837 case 2:
838 {
839 arm11->arm.core_cache->reg_list[1].dirty = true;
840
841 for (size_t i = 0; i < count; i++) {
842 /* ldrh r1, [r0], #2 */
843 CHECK_RETVAL(arm11_run_instr_no_data1(arm11,
844 !arm11_config_memrw_no_increment ? 0xe0d010b2 : 0xe1d010b0));
845
846 uint32_t res;
847
848 /* MCR p14,0,R1,c0,c5,0 */
849 CHECK_RETVAL(arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1));
850
851 uint16_t svalue = res;
852 memcpy(buffer + i * sizeof(uint16_t), &svalue, sizeof(uint16_t));
853 }
854
855 break;
856 }
857
858 case 4:
859 {
860 uint32_t instr = !arm11_config_memrw_no_increment ? 0xecb05e01 : 0xed905e00;
861 /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
862 uint32_t *words = (uint32_t *)(void *)buffer;
863
864 /* LDC p14,c5,[R0],#4 */
865 /* LDC p14,c5,[R0] */
866 CHECK_RETVAL(arm11_run_instr_data_from_core(arm11, instr, words, count));
867 break;
868 }
869 }
870
871 return arm11_run_instr_data_finish(arm11);
872 }
873
874 static int arm11_read_memory(struct target *target,
875 uint32_t address,
876 uint32_t size,
877 uint32_t count,
878 uint8_t *buffer)
879 {
880 return arm11_read_memory_inner(target, address, size, count, buffer, false);
881 }
882
883 /*
884 * no_increment - in the future we may want to be able
885 * to read/write a range of data to a "port". a "port" is an action on
886 * read memory address for some peripheral.
887 */
888 static int arm11_write_memory_inner(struct target *target,
889 uint32_t address, uint32_t size,
890 uint32_t count, const uint8_t *buffer,
891 bool no_increment)
892 {
893 int retval;
894
895 if (target->state != TARGET_HALTED) {
896 LOG_WARNING("target was not halted");
897 return ERROR_TARGET_NOT_HALTED;
898 }
899
900 LOG_DEBUG("ADDR %08" PRIx32 " SIZE %08" PRIx32 " COUNT %08" PRIx32 "",
901 address,
902 size,
903 count);
904
905 struct arm11_common *arm11 = target_to_arm11(target);
906
907 retval = arm11_run_instr_data_prepare(arm11);
908 if (retval != ERROR_OK)
909 return retval;
910
911 /* load r0 with buffer address
912 * MRC p14,0,r0,c0,c5,0 */
913 retval = arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
914 if (retval != ERROR_OK)
915 return retval;
916
917 /* burst writes are not used for single words as those may well be
918 * reset init script writes.
919 *
920 * The other advantage is that as burst writes are default, we'll
921 * now exercise both burst and non-burst code paths with the
922 * default settings, increasing code coverage.
923 */
924 bool burst = arm11->memwrite_burst && (count > 1);
925
926 switch (size) {
927 case 1:
928 {
929 arm11->arm.core_cache->reg_list[1].dirty = true;
930
931 for (size_t i = 0; i < count; i++) {
932 /* load r1 from DCC with byte data */
933 /* MRC p14,0,r1,c0,c5,0 */
934 retval = arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buffer++);
935 if (retval != ERROR_OK)
936 return retval;
937
938 /* write r1 to memory */
939 /* strb r1, [r0], #1 */
940 /* strb r1, [r0] */
941 retval = arm11_run_instr_no_data1(arm11,
942 !no_increment ? 0xe4c01001 : 0xe5c01000);
943 if (retval != ERROR_OK)
944 return retval;
945 }
946
947 break;
948 }
949
950 case 2:
951 {
952 arm11->arm.core_cache->reg_list[1].dirty = true;
953
954 for (size_t i = 0; i < count; i++) {
955 uint16_t value;
956 memcpy(&value, buffer + i * sizeof(uint16_t), sizeof(uint16_t));
957
958 /* load r1 from DCC with halfword data */
959 /* MRC p14,0,r1,c0,c5,0 */
960 retval = arm11_run_instr_data_to_core1(arm11, 0xee101e15, value);
961 if (retval != ERROR_OK)
962 return retval;
963
964 /* write r1 to memory */
965 /* strh r1, [r0], #2 */
966 /* strh r1, [r0] */
967 retval = arm11_run_instr_no_data1(arm11,
968 !no_increment ? 0xe0c010b2 : 0xe1c010b0);
969 if (retval != ERROR_OK)
970 return retval;
971 }
972
973 break;
974 }
975
976 case 4: {
977 /* stream word data through DCC directly to memory */
978 /* increment: STC p14,c5,[R0],#4 */
979 /* no increment: STC p14,c5,[R0]*/
980 uint32_t instr = !no_increment ? 0xeca05e01 : 0xed805e00;
981
982 /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
983 uint32_t *words = (uint32_t *)(void *)buffer;
984
985 /* "burst" here just means trusting each instruction executes
986 * fully before we run the next one: per-word roundtrips, to
987 * check the Ready flag, are not used.
988 */
989 if (!burst)
990 retval = arm11_run_instr_data_to_core(arm11,
991 instr, words, count);
992 else
993 retval = arm11_run_instr_data_to_core_noack(arm11,
994 instr, words, count);
995 if (retval != ERROR_OK)
996 return retval;
997
998 break;
999 }
1000 }
1001
1002 /* r0 verification */
1003 if (!no_increment) {
1004 uint32_t r0;
1005
1006 /* MCR p14,0,R0,c0,c5,0 */
1007 retval = arm11_run_instr_data_from_core(arm11, 0xEE000E15, &r0, 1);
1008 if (retval != ERROR_OK)
1009 return retval;
1010
1011 if (address + size * count != r0) {
1012 LOG_ERROR("Data transfer failed. Expected end "
1013 "address 0x%08x, got 0x%08x",
1014 (unsigned) (address + size * count),
1015 (unsigned) r0);
1016
1017 if (burst)
1018 LOG_ERROR(
1019 "use 'arm11 memwrite burst disable' to disable fast burst mode");
1020
1021
1022 if (arm11->memwrite_error_fatal)
1023 return ERROR_FAIL;
1024 }
1025 }
1026
1027 return arm11_run_instr_data_finish(arm11);
1028 }
1029
1030 static int arm11_write_memory(struct target *target,
1031 uint32_t address, uint32_t size,
1032 uint32_t count, const uint8_t *buffer)
1033 {
1034 /* pointer increment matters only for multi-unit writes ...
1035 * not e.g. to a "reset the chip" controller.
1036 */
1037 return arm11_write_memory_inner(target, address, size,
1038 count, buffer, count == 1);
1039 }
1040
1041 /* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
1042 static int arm11_bulk_write_memory(struct target *target,
1043 uint32_t address, uint32_t count, const uint8_t *buffer)
1044 {
1045 if (target->state != TARGET_HALTED) {
1046 LOG_WARNING("target was not halted");
1047 return ERROR_TARGET_NOT_HALTED;
1048 }
1049
1050 return arm11_write_memory(target, address, 4, count, buffer);
1051 }
1052
1053 /* target break-/watchpoint control
1054 * rw: 0 = write, 1 = read, 2 = access
1055 */
1056 static int arm11_add_breakpoint(struct target *target,
1057 struct breakpoint *breakpoint)
1058 {
1059 struct arm11_common *arm11 = target_to_arm11(target);
1060
1061 #if 0
1062 if (breakpoint->type == BKPT_SOFT) {
1063 LOG_INFO("sw breakpoint requested, but software breakpoints not enabled");
1064 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1065 }
1066 #endif
1067
1068 if (!arm11->free_brps) {
1069 LOG_DEBUG("no breakpoint unit available for hardware breakpoint");
1070 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1071 }
1072
1073 if (breakpoint->length != 4) {
1074 LOG_DEBUG("only breakpoints of four bytes length supported");
1075 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1076 }
1077
1078 arm11->free_brps--;
1079
1080 return ERROR_OK;
1081 }
1082
1083 static int arm11_remove_breakpoint(struct target *target,
1084 struct breakpoint *breakpoint)
1085 {
1086 struct arm11_common *arm11 = target_to_arm11(target);
1087
1088 arm11->free_brps++;
1089
1090 return ERROR_OK;
1091 }
1092
1093 static int arm11_target_create(struct target *target, Jim_Interp *interp)
1094 {
1095 struct arm11_common *arm11;
1096
1097 if (target->tap == NULL)
1098 return ERROR_FAIL;
1099
1100 if (target->tap->ir_length != 5) {
1101 LOG_ERROR("'target arm11' expects IR LENGTH = 5");
1102 return ERROR_COMMAND_SYNTAX_ERROR;
1103 }
1104
1105 arm11 = calloc(1, sizeof *arm11);
1106 if (!arm11)
1107 return ERROR_FAIL;
1108
1109 arm_init_arch_info(target, &arm11->arm);
1110
1111 arm11->jtag_info.tap = target->tap;
1112 arm11->jtag_info.scann_size = 5;
1113 arm11->jtag_info.scann_instr = ARM11_SCAN_N;
1114 arm11->jtag_info.cur_scan_chain = ~0; /* invalid/unknown */
1115 arm11->jtag_info.intest_instr = ARM11_INTEST;
1116
1117 arm11->memwrite_burst = true;
1118 arm11->memwrite_error_fatal = true;
1119
1120 return ERROR_OK;
1121 }
1122
1123 static int arm11_init_target(struct command_context *cmd_ctx,
1124 struct target *target)
1125 {
1126 /* Initialize anything we can set up without talking to the target */
1127 return ERROR_OK;
1128 }
1129
1130 /* talk to the target and set things up */
1131 static int arm11_examine(struct target *target)
1132 {
1133 int retval;
1134 char *type;
1135 struct arm11_common *arm11 = target_to_arm11(target);
1136 uint32_t didr, device_id;
1137 uint8_t implementor;
1138
1139 /* FIXME split into do-first-time and do-every-time logic ... */
1140
1141 /* check IDCODE */
1142
1143 arm11_add_IR(arm11, ARM11_IDCODE, ARM11_TAP_DEFAULT);
1144
1145 struct scan_field idcode_field;
1146
1147 arm11_setup_field(arm11, 32, NULL, &device_id, &idcode_field);
1148
1149 arm11_add_dr_scan_vc(arm11->arm.target->tap, 1, &idcode_field, TAP_DRPAUSE);
1150
1151 /* check DIDR */
1152
1153 arm11_add_debug_SCAN_N(arm11, 0x00, ARM11_TAP_DEFAULT);
1154
1155 arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
1156
1157 struct scan_field chain0_fields[2];
1158
1159 arm11_setup_field(arm11, 32, NULL, &didr, chain0_fields + 0);
1160 arm11_setup_field(arm11, 8, NULL, &implementor, chain0_fields + 1);
1161
1162 arm11_add_dr_scan_vc(arm11->arm.target->tap, ARRAY_SIZE(
1163 chain0_fields), chain0_fields, TAP_IDLE);
1164
1165 CHECK_RETVAL(jtag_execute_queue());
1166
1167 /* assume the manufacturer id is ok; check the part # */
1168 switch ((device_id >> 12) & 0xFFFF) {
1169 case 0x7B36:
1170 type = "ARM1136";
1171 break;
1172 case 0x7B37:
1173 type = "ARM11 MPCore";
1174 break;
1175 case 0x7B56:
1176 type = "ARM1156";
1177 break;
1178 case 0x7B76:
1179 arm11->arm.core_type = ARM_MODE_MON;
1180 /* NOTE: could default arm11->hardware_step to true */
1181 type = "ARM1176";
1182 break;
1183 default:
1184 LOG_ERROR("unexpected ARM11 ID code");
1185 return ERROR_FAIL;
1186 }
1187 LOG_INFO("found %s", type);
1188
1189 /* unlikely this could ever fail, but ... */
1190 switch ((didr >> 16) & 0x0F) {
1191 case ARM11_DEBUG_V6:
1192 case ARM11_DEBUG_V61: /* supports security extensions */
1193 break;
1194 default:
1195 LOG_ERROR("Only ARM v6 and v6.1 debug supported.");
1196 return ERROR_FAIL;
1197 }
1198
1199 arm11->brp = ((didr >> 24) & 0x0F) + 1;
1200
1201 /** \todo TODO: reserve one brp slot if we allow breakpoints during step */
1202 arm11->free_brps = arm11->brp;
1203
1204 LOG_DEBUG("IDCODE %08" PRIx32 " IMPLEMENTOR %02x DIDR %08" PRIx32,
1205 device_id, implementor, didr);
1206
1207 /* as a side-effect this reads DSCR and thus
1208 * clears the ARM11_DSCR_STICKY_PRECISE_DATA_ABORT / Sticky Precise Data Abort Flag
1209 * as suggested by the spec.
1210 */
1211
1212 retval = arm11_check_init(arm11);
1213 if (retval != ERROR_OK)
1214 return retval;
1215
1216 /* Build register cache "late", after target_init(), since we
1217 * want to know if this core supports Secure Monitor mode.
1218 */
1219 if (!target_was_examined(target))
1220 CHECK_RETVAL(arm11_dpm_init(arm11, didr));
1221
1222 /* ETM on ARM11 still uses original scanchain 6 access mode */
1223 if (arm11->arm.etm && !target_was_examined(target)) {
1224 *register_get_last_cache_p(&target->reg_cache) =
1225 etm_build_reg_cache(target, &arm11->jtag_info,
1226 arm11->arm.etm);
1227 CHECK_RETVAL(etm_setup(target));
1228 }
1229
1230 target_set_examined(target);
1231
1232 return ERROR_OK;
1233 }
1234
1235 #define ARM11_BOOL_WRAPPER(name, print_name) \
1236 COMMAND_HANDLER(arm11_handle_bool_ ## name) \
1237 { \
1238 struct target *target = get_current_target(CMD_CTX); \
1239 struct arm11_common *arm11 = target_to_arm11(target); \
1240 \
1241 return CALL_COMMAND_HANDLER(handle_command_parse_bool, \
1242 &arm11->name, print_name); \
1243 }
1244
1245 ARM11_BOOL_WRAPPER(memwrite_burst, "memory write burst mode")
1246 ARM11_BOOL_WRAPPER(memwrite_error_fatal, "fatal error mode for memory writes")
1247 ARM11_BOOL_WRAPPER(step_irq_enable, "IRQs while stepping")
1248 ARM11_BOOL_WRAPPER(hardware_step, "hardware single step")
1249
1250 /* REVISIT handle the VCR bits like other ARMs: use symbols for
1251 * input and output values.
1252 */
1253
1254 COMMAND_HANDLER(arm11_handle_vcr)
1255 {
1256 struct target *target = get_current_target(CMD_CTX);
1257 struct arm11_common *arm11 = target_to_arm11(target);
1258
1259 switch (CMD_ARGC) {
1260 case 0:
1261 break;
1262 case 1:
1263 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], arm11->vcr);
1264 break;
1265 default:
1266 return ERROR_COMMAND_SYNTAX_ERROR;
1267 }
1268
1269 LOG_INFO("VCR 0x%08" PRIx32 "", arm11->vcr);
1270 return ERROR_OK;
1271 }
1272
1273 static const struct command_registration arm11_mw_command_handlers[] = {
1274 {
1275 .name = "burst",
1276 .handler = arm11_handle_bool_memwrite_burst,
1277 .mode = COMMAND_ANY,
1278 .help = "Display or modify flag controlling potentially "
1279 "risky fast burst mode (default: enabled)",
1280 .usage = "['enable'|'disable']",
1281 },
1282 {
1283 .name = "error_fatal",
1284 .handler = arm11_handle_bool_memwrite_error_fatal,
1285 .mode = COMMAND_ANY,
1286 .help = "Display or modify flag controlling transfer "
1287 "termination on transfer errors"
1288 " (default: enabled)",
1289 .usage = "['enable'|'disable']",
1290 },
1291 COMMAND_REGISTRATION_DONE
1292 };
1293 static const struct command_registration arm11_any_command_handlers[] = {
1294 {
1295 /* "hardware_step" is only here to check if the default
1296 * simulate + breakpoint implementation is broken.
1297 * TEMPORARY! NOT DOCUMENTED! */
1298 .name = "hardware_step",
1299 .handler = arm11_handle_bool_hardware_step,
1300 .mode = COMMAND_ANY,
1301 .help = "DEBUG ONLY - Hardware single stepping"
1302 " (default: disabled)",
1303 .usage = "['enable'|'disable']",
1304 },
1305 {
1306 .name = "memwrite",
1307 .mode = COMMAND_ANY,
1308 .help = "memwrite command group",
1309 .usage = "",
1310 .chain = arm11_mw_command_handlers,
1311 },
1312 {
1313 .name = "step_irq_enable",
1314 .handler = arm11_handle_bool_step_irq_enable,
1315 .mode = COMMAND_ANY,
1316 .help = "Display or modify flag controlling interrupt "
1317 "enable while stepping (default: disabled)",
1318 .usage = "['enable'|'disable']",
1319 },
1320 {
1321 .name = "vcr",
1322 .handler = arm11_handle_vcr,
1323 .mode = COMMAND_ANY,
1324 .help = "Display or modify Vector Catch Register",
1325 .usage = "[value]",
1326 },
1327 COMMAND_REGISTRATION_DONE
1328 };
1329
1330 static const struct command_registration arm11_command_handlers[] = {
1331 {
1332 .chain = arm_command_handlers,
1333 },
1334 {
1335 .chain = etm_command_handlers,
1336 },
1337 {
1338 .name = "arm11",
1339 .mode = COMMAND_ANY,
1340 .help = "ARM11 command group",
1341 .usage = "",
1342 .chain = arm11_any_command_handlers,
1343 },
1344 COMMAND_REGISTRATION_DONE
1345 };
1346
1347 /** Holds methods for ARM11xx targets. */
1348 struct target_type arm11_target = {
1349 .name = "arm11",
1350
1351 .poll = arm11_poll,
1352 .arch_state = arm11_arch_state,
1353
1354 .target_request_data = arm11_target_request_data,
1355
1356 .halt = arm11_halt,
1357 .resume = arm11_resume,
1358 .step = arm11_step,
1359
1360 .assert_reset = arm11_assert_reset,
1361 .deassert_reset = arm11_deassert_reset,
1362 .soft_reset_halt = arm11_soft_reset_halt,
1363
1364 .get_gdb_reg_list = arm_get_gdb_reg_list,
1365
1366 .read_memory = arm11_read_memory,
1367 .write_memory = arm11_write_memory,
1368
1369 .bulk_write_memory = arm11_bulk_write_memory,
1370
1371 .checksum_memory = arm_checksum_memory,
1372 .blank_check_memory = arm_blank_check_memory,
1373
1374 .add_breakpoint = arm11_add_breakpoint,
1375 .remove_breakpoint = arm11_remove_breakpoint,
1376
1377 .run_algorithm = armv4_5_run_algorithm,
1378
1379 .commands = arm11_command_handlers,
1380 .target_create = arm11_target_create,
1381 .init_target = arm11_init_target,
1382 .examine = arm11_examine,
1383 };