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arm11 hardware step using simulation + breakpoint. Use "hardware_step enable" command...
[openocd.git] / src / target / arm11.c
1 /***************************************************************************
2 * Copyright (C) 2008 digenius technology GmbH. *
3 * Michael Bruck *
4 * *
5 * Copyright (C) 2008 Oyvind Harboe oyvind.harboe@zylin.com *
6 * *
7 * Copyright (C) 2008 Georg Acher <acher@in.tum.de> *
8 * *
9 * This program is free software; you can redistribute it and/or modify *
10 * it under the terms of the GNU General Public License as published by *
11 * the Free Software Foundation; either version 2 of the License, or *
12 * (at your option) any later version. *
13 * *
14 * This program is distributed in the hope that it will be useful, *
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
17 * GNU General Public License for more details. *
18 * *
19 * You should have received a copy of the GNU General Public License *
20 * along with this program; if not, write to the *
21 * Free Software Foundation, Inc., *
22 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
23 ***************************************************************************/
24
25 #ifdef HAVE_CONFIG_H
26 #include "config.h"
27 #endif
28
29 #include "arm11.h"
30 #include "armv4_5.h"
31 #include "arm_simulator.h"
32 #include "target_type.h"
33
34
35 #if 0
36 #define _DEBUG_INSTRUCTION_EXECUTION_
37 #endif
38
39 #if 0
40 #define FNC_INFO LOG_DEBUG("-")
41 #else
42 #define FNC_INFO
43 #endif
44
45 #if 1
46 #define FNC_INFO_NOTIMPLEMENTED do { LOG_DEBUG("NOT IMPLEMENTED"); /*exit(-1);*/ } while (0)
47 #else
48 #define FNC_INFO_NOTIMPLEMENTED
49 #endif
50
51 static int arm11_on_enter_debug_state(arm11_common_t * arm11);
52
53 bool arm11_config_memwrite_burst = true;
54 bool arm11_config_memwrite_error_fatal = true;
55 uint32_t arm11_vcr = 0;
56 bool arm11_config_memrw_no_increment = false;
57 bool arm11_config_step_irq_enable = false;
58 bool arm11_config_hardware_step = false;
59
60 #define ARM11_HANDLER(x) \
61 .x = arm11_##x
62
63 target_type_t arm11_target =
64 {
65 .name = "arm11",
66
67 ARM11_HANDLER(poll),
68 ARM11_HANDLER(arch_state),
69
70 ARM11_HANDLER(target_request_data),
71
72 ARM11_HANDLER(halt),
73 ARM11_HANDLER(resume),
74 ARM11_HANDLER(step),
75
76 ARM11_HANDLER(assert_reset),
77 ARM11_HANDLER(deassert_reset),
78 ARM11_HANDLER(soft_reset_halt),
79
80 ARM11_HANDLER(get_gdb_reg_list),
81
82 ARM11_HANDLER(read_memory),
83 ARM11_HANDLER(write_memory),
84
85 ARM11_HANDLER(bulk_write_memory),
86
87 ARM11_HANDLER(checksum_memory),
88
89 ARM11_HANDLER(add_breakpoint),
90 ARM11_HANDLER(remove_breakpoint),
91 ARM11_HANDLER(add_watchpoint),
92 ARM11_HANDLER(remove_watchpoint),
93
94 ARM11_HANDLER(run_algorithm),
95
96 ARM11_HANDLER(register_commands),
97 ARM11_HANDLER(target_create),
98 ARM11_HANDLER(init_target),
99 ARM11_HANDLER(examine),
100 ARM11_HANDLER(quit),
101 };
102
103 int arm11_regs_arch_type = -1;
104
105
106 enum arm11_regtype
107 {
108 ARM11_REGISTER_CORE,
109 ARM11_REGISTER_CPSR,
110
111 ARM11_REGISTER_FX,
112 ARM11_REGISTER_FPS,
113
114 ARM11_REGISTER_FIQ,
115 ARM11_REGISTER_SVC,
116 ARM11_REGISTER_ABT,
117 ARM11_REGISTER_IRQ,
118 ARM11_REGISTER_UND,
119 ARM11_REGISTER_MON,
120
121 ARM11_REGISTER_SPSR_FIQ,
122 ARM11_REGISTER_SPSR_SVC,
123 ARM11_REGISTER_SPSR_ABT,
124 ARM11_REGISTER_SPSR_IRQ,
125 ARM11_REGISTER_SPSR_UND,
126 ARM11_REGISTER_SPSR_MON,
127
128 /* debug regs */
129 ARM11_REGISTER_DSCR,
130 ARM11_REGISTER_WDTR,
131 ARM11_REGISTER_RDTR,
132 };
133
134
135 typedef struct arm11_reg_defs_s
136 {
137 char * name;
138 uint32_t num;
139 int gdb_num;
140 enum arm11_regtype type;
141 } arm11_reg_defs_t;
142
143 /* update arm11_regcache_ids when changing this */
144 static const arm11_reg_defs_t arm11_reg_defs[] =
145 {
146 {"r0", 0, 0, ARM11_REGISTER_CORE},
147 {"r1", 1, 1, ARM11_REGISTER_CORE},
148 {"r2", 2, 2, ARM11_REGISTER_CORE},
149 {"r3", 3, 3, ARM11_REGISTER_CORE},
150 {"r4", 4, 4, ARM11_REGISTER_CORE},
151 {"r5", 5, 5, ARM11_REGISTER_CORE},
152 {"r6", 6, 6, ARM11_REGISTER_CORE},
153 {"r7", 7, 7, ARM11_REGISTER_CORE},
154 {"r8", 8, 8, ARM11_REGISTER_CORE},
155 {"r9", 9, 9, ARM11_REGISTER_CORE},
156 {"r10", 10, 10, ARM11_REGISTER_CORE},
157 {"r11", 11, 11, ARM11_REGISTER_CORE},
158 {"r12", 12, 12, ARM11_REGISTER_CORE},
159 {"sp", 13, 13, ARM11_REGISTER_CORE},
160 {"lr", 14, 14, ARM11_REGISTER_CORE},
161 {"pc", 15, 15, ARM11_REGISTER_CORE},
162
163 #if ARM11_REGCACHE_FREGS
164 {"f0", 0, 16, ARM11_REGISTER_FX},
165 {"f1", 1, 17, ARM11_REGISTER_FX},
166 {"f2", 2, 18, ARM11_REGISTER_FX},
167 {"f3", 3, 19, ARM11_REGISTER_FX},
168 {"f4", 4, 20, ARM11_REGISTER_FX},
169 {"f5", 5, 21, ARM11_REGISTER_FX},
170 {"f6", 6, 22, ARM11_REGISTER_FX},
171 {"f7", 7, 23, ARM11_REGISTER_FX},
172 {"fps", 0, 24, ARM11_REGISTER_FPS},
173 #endif
174
175 {"cpsr", 0, 25, ARM11_REGISTER_CPSR},
176
177 #if ARM11_REGCACHE_MODEREGS
178 {"r8_fiq", 8, -1, ARM11_REGISTER_FIQ},
179 {"r9_fiq", 9, -1, ARM11_REGISTER_FIQ},
180 {"r10_fiq", 10, -1, ARM11_REGISTER_FIQ},
181 {"r11_fiq", 11, -1, ARM11_REGISTER_FIQ},
182 {"r12_fiq", 12, -1, ARM11_REGISTER_FIQ},
183 {"r13_fiq", 13, -1, ARM11_REGISTER_FIQ},
184 {"r14_fiq", 14, -1, ARM11_REGISTER_FIQ},
185 {"spsr_fiq", 0, -1, ARM11_REGISTER_SPSR_FIQ},
186
187 {"r13_svc", 13, -1, ARM11_REGISTER_SVC},
188 {"r14_svc", 14, -1, ARM11_REGISTER_SVC},
189 {"spsr_svc", 0, -1, ARM11_REGISTER_SPSR_SVC},
190
191 {"r13_abt", 13, -1, ARM11_REGISTER_ABT},
192 {"r14_abt", 14, -1, ARM11_REGISTER_ABT},
193 {"spsr_abt", 0, -1, ARM11_REGISTER_SPSR_ABT},
194
195 {"r13_irq", 13, -1, ARM11_REGISTER_IRQ},
196 {"r14_irq", 14, -1, ARM11_REGISTER_IRQ},
197 {"spsr_irq", 0, -1, ARM11_REGISTER_SPSR_IRQ},
198
199 {"r13_und", 13, -1, ARM11_REGISTER_UND},
200 {"r14_und", 14, -1, ARM11_REGISTER_UND},
201 {"spsr_und", 0, -1, ARM11_REGISTER_SPSR_UND},
202
203 /* ARM1176 only */
204 {"r13_mon", 13, -1, ARM11_REGISTER_MON},
205 {"r14_mon", 14, -1, ARM11_REGISTER_MON},
206 {"spsr_mon", 0, -1, ARM11_REGISTER_SPSR_MON},
207 #endif
208
209 /* Debug Registers */
210 {"dscr", 0, -1, ARM11_REGISTER_DSCR},
211 {"wdtr", 0, -1, ARM11_REGISTER_WDTR},
212 {"rdtr", 0, -1, ARM11_REGISTER_RDTR},
213 };
214
215 enum arm11_regcache_ids
216 {
217 ARM11_RC_R0,
218 ARM11_RC_RX = ARM11_RC_R0,
219
220 ARM11_RC_R1,
221 ARM11_RC_R2,
222 ARM11_RC_R3,
223 ARM11_RC_R4,
224 ARM11_RC_R5,
225 ARM11_RC_R6,
226 ARM11_RC_R7,
227 ARM11_RC_R8,
228 ARM11_RC_R9,
229 ARM11_RC_R10,
230 ARM11_RC_R11,
231 ARM11_RC_R12,
232 ARM11_RC_R13,
233 ARM11_RC_SP = ARM11_RC_R13,
234 ARM11_RC_R14,
235 ARM11_RC_LR = ARM11_RC_R14,
236 ARM11_RC_R15,
237 ARM11_RC_PC = ARM11_RC_R15,
238
239 #if ARM11_REGCACHE_FREGS
240 ARM11_RC_F0,
241 ARM11_RC_FX = ARM11_RC_F0,
242 ARM11_RC_F1,
243 ARM11_RC_F2,
244 ARM11_RC_F3,
245 ARM11_RC_F4,
246 ARM11_RC_F5,
247 ARM11_RC_F6,
248 ARM11_RC_F7,
249 ARM11_RC_FPS,
250 #endif
251
252 ARM11_RC_CPSR,
253
254 #if ARM11_REGCACHE_MODEREGS
255 ARM11_RC_R8_FIQ,
256 ARM11_RC_R9_FIQ,
257 ARM11_RC_R10_FIQ,
258 ARM11_RC_R11_FIQ,
259 ARM11_RC_R12_FIQ,
260 ARM11_RC_R13_FIQ,
261 ARM11_RC_R14_FIQ,
262 ARM11_RC_SPSR_FIQ,
263
264 ARM11_RC_R13_SVC,
265 ARM11_RC_R14_SVC,
266 ARM11_RC_SPSR_SVC,
267
268 ARM11_RC_R13_ABT,
269 ARM11_RC_R14_ABT,
270 ARM11_RC_SPSR_ABT,
271
272 ARM11_RC_R13_IRQ,
273 ARM11_RC_R14_IRQ,
274 ARM11_RC_SPSR_IRQ,
275
276 ARM11_RC_R13_UND,
277 ARM11_RC_R14_UND,
278 ARM11_RC_SPSR_UND,
279
280 ARM11_RC_R13_MON,
281 ARM11_RC_R14_MON,
282 ARM11_RC_SPSR_MON,
283 #endif
284
285 ARM11_RC_DSCR,
286 ARM11_RC_WDTR,
287 ARM11_RC_RDTR,
288
289 ARM11_RC_MAX,
290 };
291
292 #define ARM11_GDB_REGISTER_COUNT 26
293
294 uint8_t arm11_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
295
296 reg_t arm11_gdb_dummy_fp_reg =
297 {
298 "GDB dummy floating-point register", arm11_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0
299 };
300
301 uint8_t arm11_gdb_dummy_fps_value[] = {0, 0, 0, 0};
302
303 reg_t arm11_gdb_dummy_fps_reg =
304 {
305 "GDB dummy floating-point status register", arm11_gdb_dummy_fps_value, 0, 1, 32, NULL, 0, NULL, 0
306 };
307
308
309
310 /** Check and if necessary take control of the system
311 *
312 * \param arm11 Target state variable.
313 * \param dscr If the current DSCR content is
314 * available a pointer to a word holding the
315 * DSCR can be passed. Otherwise use NULL.
316 */
317 int arm11_check_init(arm11_common_t * arm11, uint32_t * dscr)
318 {
319 FNC_INFO;
320
321 uint32_t dscr_local_tmp_copy;
322
323 if (!dscr)
324 {
325 dscr = &dscr_local_tmp_copy;
326
327 CHECK_RETVAL(arm11_read_DSCR(arm11, dscr));
328 }
329
330 if (!(*dscr & ARM11_DSCR_MODE_SELECT))
331 {
332 LOG_DEBUG("Bringing target into debug mode");
333
334 *dscr |= ARM11_DSCR_MODE_SELECT; /* Halt debug-mode */
335 arm11_write_DSCR(arm11, *dscr);
336
337 /* add further reset initialization here */
338
339 arm11->simulate_reset_on_next_halt = true;
340
341 if (*dscr & ARM11_DSCR_CORE_HALTED)
342 {
343 /** \todo TODO: this needs further scrutiny because
344 * arm11_on_enter_debug_state() never gets properly called.
345 * As a result we don't read the actual register states from
346 * the target.
347 */
348
349 arm11->target->state = TARGET_HALTED;
350 arm11->target->debug_reason = arm11_get_DSCR_debug_reason(*dscr);
351 }
352 else
353 {
354 arm11->target->state = TARGET_RUNNING;
355 arm11->target->debug_reason = DBG_REASON_NOTHALTED;
356 }
357
358 arm11_sc7_clear_vbw(arm11);
359 }
360
361 return ERROR_OK;
362 }
363
364
365
366 #define R(x) \
367 (arm11->reg_values[ARM11_RC_##x])
368
369 /** Save processor state.
370 *
371 * This is called when the HALT instruction has succeeded
372 * or on other occasions that stop the processor.
373 *
374 */
375 static int arm11_on_enter_debug_state(arm11_common_t * arm11)
376 {
377 FNC_INFO;
378
379 for (size_t i = 0; i < asizeof(arm11->reg_values); i++)
380 {
381 arm11->reg_list[i].valid = 1;
382 arm11->reg_list[i].dirty = 0;
383 }
384
385 /* Save DSCR */
386 CHECK_RETVAL(arm11_read_DSCR(arm11, &R(DSCR)));
387
388 /* Save wDTR */
389
390 if (R(DSCR) & ARM11_DSCR_WDTR_FULL)
391 {
392 arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
393
394 arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
395
396 scan_field_t chain5_fields[3];
397
398 arm11_setup_field(arm11, 32, NULL, &R(WDTR), chain5_fields + 0);
399 arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 1);
400 arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 2);
401
402 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
403 }
404 else
405 {
406 arm11->reg_list[ARM11_RC_WDTR].valid = 0;
407 }
408
409
410 /* DSCR: set ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE */
411 /* ARM1176 spec says this is needed only for wDTR/rDTR's "ITR mode", but not to issue ITRs
412 ARM1136 seems to require this to issue ITR's as well */
413
414 uint32_t new_dscr = R(DSCR) | ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE;
415
416 /* this executes JTAG queue: */
417
418 arm11_write_DSCR(arm11, new_dscr);
419
420
421 /* From the spec:
422 Before executing any instruction in debug state you have to drain the write buffer.
423 This ensures that no imprecise Data Aborts can return at a later point:*/
424
425 /** \todo TODO: Test drain write buffer. */
426
427 #if 0
428 while (1)
429 {
430 /* MRC p14,0,R0,c5,c10,0 */
431 // arm11_run_instr_no_data1(arm11, /*0xee150e1a*/0xe320f000);
432
433 /* mcr 15, 0, r0, cr7, cr10, {4} */
434 arm11_run_instr_no_data1(arm11, 0xee070f9a);
435
436 uint32_t dscr = arm11_read_DSCR(arm11);
437
438 LOG_DEBUG("DRAIN, DSCR %08x", dscr);
439
440 if (dscr & ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT)
441 {
442 arm11_run_instr_no_data1(arm11, 0xe320f000);
443
444 dscr = arm11_read_DSCR(arm11);
445
446 LOG_DEBUG("DRAIN, DSCR %08x (DONE)", dscr);
447
448 break;
449 }
450 }
451 #endif
452
453 arm11_run_instr_data_prepare(arm11);
454
455 /* save r0 - r14 */
456
457 /** \todo TODO: handle other mode registers */
458
459 for (size_t i = 0; i < 15; i++)
460 {
461 /* MCR p14,0,R?,c0,c5,0 */
462 arm11_run_instr_data_from_core(arm11, 0xEE000E15 | (i << 12), &R(RX + i), 1);
463 }
464
465 /* save rDTR */
466
467 /* check rDTRfull in DSCR */
468
469 if (R(DSCR) & ARM11_DSCR_RDTR_FULL)
470 {
471 /* MRC p14,0,R0,c0,c5,0 (move rDTR -> r0 (-> wDTR -> local var)) */
472 arm11_run_instr_data_from_core_via_r0(arm11, 0xEE100E15, &R(RDTR));
473 }
474 else
475 {
476 arm11->reg_list[ARM11_RC_RDTR].valid = 0;
477 }
478
479 /* save CPSR */
480
481 /* MRS r0,CPSR (move CPSR -> r0 (-> wDTR -> local var)) */
482 arm11_run_instr_data_from_core_via_r0(arm11, 0xE10F0000, &R(CPSR));
483
484 /* save PC */
485
486 /* MOV R0,PC (move PC -> r0 (-> wDTR -> local var)) */
487 arm11_run_instr_data_from_core_via_r0(arm11, 0xE1A0000F, &R(PC));
488
489 /* adjust PC depending on ARM state */
490
491 if (R(CPSR) & ARM11_CPSR_J) /* Java state */
492 {
493 arm11->reg_values[ARM11_RC_PC] -= 0;
494 }
495 else if (R(CPSR) & ARM11_CPSR_T) /* Thumb state */
496 {
497 arm11->reg_values[ARM11_RC_PC] -= 4;
498 }
499 else /* ARM state */
500 {
501 arm11->reg_values[ARM11_RC_PC] -= 8;
502 }
503
504 if (arm11->simulate_reset_on_next_halt)
505 {
506 arm11->simulate_reset_on_next_halt = false;
507
508 LOG_DEBUG("Reset c1 Control Register");
509
510 /* Write 0 (reset value) to Control register 0 to disable MMU/Cache etc. */
511
512 /* MCR p15,0,R0,c1,c0,0 */
513 arm11_run_instr_data_to_core_via_r0(arm11, 0xee010f10, 0);
514
515 }
516
517 arm11_run_instr_data_finish(arm11);
518
519 arm11_dump_reg_changes(arm11);
520
521 return ERROR_OK;
522 }
523
524 void arm11_dump_reg_changes(arm11_common_t * arm11)
525 {
526
527 if (!(debug_level >= LOG_LVL_DEBUG))
528 {
529 return;
530 }
531
532 for (size_t i = 0; i < ARM11_REGCACHE_COUNT; i++)
533 {
534 if (!arm11->reg_list[i].valid)
535 {
536 if (arm11->reg_history[i].valid)
537 LOG_DEBUG("%8s INVALID (%08" PRIx32 ")", arm11_reg_defs[i].name, arm11->reg_history[i].value);
538 }
539 else
540 {
541 if (arm11->reg_history[i].valid)
542 {
543 if (arm11->reg_history[i].value != arm11->reg_values[i])
544 LOG_DEBUG("%8s %08" PRIx32 " (%08" PRIx32 ")", arm11_reg_defs[i].name, arm11->reg_values[i], arm11->reg_history[i].value);
545 }
546 else
547 {
548 LOG_DEBUG("%8s %08" PRIx32 " (INVALID)", arm11_reg_defs[i].name, arm11->reg_values[i]);
549 }
550 }
551 }
552 }
553
554 /** Restore processor state
555 *
556 * This is called in preparation for the RESTART function.
557 *
558 */
559 int arm11_leave_debug_state(arm11_common_t * arm11)
560 {
561 FNC_INFO;
562
563 arm11_run_instr_data_prepare(arm11);
564
565 /** \todo TODO: handle other mode registers */
566
567 /* restore R1 - R14 */
568
569 for (size_t i = 1; i < 15; i++)
570 {
571 if (!arm11->reg_list[ARM11_RC_RX + i].dirty)
572 continue;
573
574 /* MRC p14,0,r?,c0,c5,0 */
575 arm11_run_instr_data_to_core1(arm11, 0xee100e15 | (i << 12), R(RX + i));
576
577 // LOG_DEBUG("RESTORE R" ZU " %08x", i, R(RX + i));
578 }
579
580 arm11_run_instr_data_finish(arm11);
581
582 /* spec says clear wDTR and rDTR; we assume they are clear as
583 otherwise our programming would be sloppy */
584 {
585 uint32_t DSCR;
586
587 CHECK_RETVAL(arm11_read_DSCR(arm11, &DSCR));
588
589 if (DSCR & (ARM11_DSCR_RDTR_FULL | ARM11_DSCR_WDTR_FULL))
590 {
591 LOG_ERROR("wDTR/rDTR inconsistent (DSCR %08" PRIx32 ")", DSCR);
592 }
593 }
594
595 arm11_run_instr_data_prepare(arm11);
596
597 /* restore original wDTR */
598
599 if ((R(DSCR) & ARM11_DSCR_WDTR_FULL) || arm11->reg_list[ARM11_RC_WDTR].dirty)
600 {
601 /* MCR p14,0,R0,c0,c5,0 */
602 arm11_run_instr_data_to_core_via_r0(arm11, 0xee000e15, R(WDTR));
603 }
604
605 /* restore CPSR */
606
607 /* MSR CPSR,R0*/
608 arm11_run_instr_data_to_core_via_r0(arm11, 0xe129f000, R(CPSR));
609
610 /* restore PC */
611
612 /* MOV PC,R0 */
613 arm11_run_instr_data_to_core_via_r0(arm11, 0xe1a0f000, R(PC));
614
615 /* restore R0 */
616
617 /* MRC p14,0,r0,c0,c5,0 */
618 arm11_run_instr_data_to_core1(arm11, 0xee100e15, R(R0));
619
620 arm11_run_instr_data_finish(arm11);
621
622 /* restore DSCR */
623
624 arm11_write_DSCR(arm11, R(DSCR));
625
626 /* restore rDTR */
627
628 if (R(DSCR) & ARM11_DSCR_RDTR_FULL || arm11->reg_list[ARM11_RC_RDTR].dirty)
629 {
630 arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
631
632 arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT);
633
634 scan_field_t chain5_fields[3];
635
636 uint8_t Ready = 0; /* ignored */
637 uint8_t Valid = 0; /* ignored */
638
639 arm11_setup_field(arm11, 32, &R(RDTR), NULL, chain5_fields + 0);
640 arm11_setup_field(arm11, 1, &Ready, NULL, chain5_fields + 1);
641 arm11_setup_field(arm11, 1, &Valid, NULL, chain5_fields + 2);
642
643 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
644 }
645
646 arm11_record_register_history(arm11);
647
648 return ERROR_OK;
649 }
650
651 void arm11_record_register_history(arm11_common_t * arm11)
652 {
653 for (size_t i = 0; i < ARM11_REGCACHE_COUNT; i++)
654 {
655 arm11->reg_history[i].value = arm11->reg_values[i];
656 arm11->reg_history[i].valid = arm11->reg_list[i].valid;
657
658 arm11->reg_list[i].valid = 0;
659 arm11->reg_list[i].dirty = 0;
660 }
661 }
662
663
664 /* poll current target status */
665 int arm11_poll(struct target_s *target)
666 {
667 FNC_INFO;
668
669 arm11_common_t * arm11 = target->arch_info;
670
671 if (arm11->trst_active)
672 return ERROR_OK;
673
674 uint32_t dscr;
675
676 CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
677
678 LOG_DEBUG("DSCR %08" PRIx32 "", dscr);
679
680 CHECK_RETVAL(arm11_check_init(arm11, &dscr));
681
682 if (dscr & ARM11_DSCR_CORE_HALTED)
683 {
684 if (target->state != TARGET_HALTED)
685 {
686 enum target_state old_state = target->state;
687
688 LOG_DEBUG("enter TARGET_HALTED");
689 target->state = TARGET_HALTED;
690 target->debug_reason = arm11_get_DSCR_debug_reason(dscr);
691 arm11_on_enter_debug_state(arm11);
692
693 target_call_event_callbacks(target,
694 old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED);
695 }
696 }
697 else
698 {
699 if (target->state != TARGET_RUNNING && target->state != TARGET_DEBUG_RUNNING)
700 {
701 LOG_DEBUG("enter TARGET_RUNNING");
702 target->state = TARGET_RUNNING;
703 target->debug_reason = DBG_REASON_NOTHALTED;
704 }
705 }
706
707 return ERROR_OK;
708 }
709 /* architecture specific status reply */
710 int arm11_arch_state(struct target_s *target)
711 {
712 arm11_common_t * arm11 = target->arch_info;
713
714 LOG_USER("target halted due to %s\ncpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "",
715 Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name,
716 R(CPSR),
717 R(PC));
718
719 return ERROR_OK;
720 }
721
722 /* target request support */
723 int arm11_target_request_data(struct target_s *target, uint32_t size, uint8_t *buffer)
724 {
725 FNC_INFO_NOTIMPLEMENTED;
726
727 return ERROR_OK;
728 }
729
730 /* target execution control */
731 int arm11_halt(struct target_s *target)
732 {
733 FNC_INFO;
734
735 arm11_common_t * arm11 = target->arch_info;
736
737 LOG_DEBUG("target->state: %s",
738 target_state_name(target));
739
740 if (target->state == TARGET_UNKNOWN)
741 {
742 arm11->simulate_reset_on_next_halt = true;
743 }
744
745 if (target->state == TARGET_HALTED)
746 {
747 LOG_DEBUG("target was already halted");
748 return ERROR_OK;
749 }
750
751 if (arm11->trst_active)
752 {
753 arm11->halt_requested = true;
754 return ERROR_OK;
755 }
756
757 arm11_add_IR(arm11, ARM11_HALT, TAP_IDLE);
758
759 CHECK_RETVAL(jtag_execute_queue());
760
761 uint32_t dscr;
762
763 while (1)
764 {
765 CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
766
767 if (dscr & ARM11_DSCR_CORE_HALTED)
768 break;
769 }
770
771 arm11_on_enter_debug_state(arm11);
772
773 enum target_state old_state = target->state;
774
775 target->state = TARGET_HALTED;
776 target->debug_reason = arm11_get_DSCR_debug_reason(dscr);
777
778 CHECK_RETVAL(
779 target_call_event_callbacks(target,
780 old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED));
781
782 return ERROR_OK;
783 }
784
785 int arm11_resume(struct target_s *target, int current, uint32_t address, int handle_breakpoints, int debug_execution)
786 {
787 FNC_INFO;
788
789 // LOG_DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d",
790 // current, address, handle_breakpoints, debug_execution);
791
792 arm11_common_t * arm11 = target->arch_info;
793
794 LOG_DEBUG("target->state: %s",
795 target_state_name(target));
796
797
798 if (target->state != TARGET_HALTED)
799 {
800 LOG_ERROR("Target not halted");
801 return ERROR_TARGET_NOT_HALTED;
802 }
803
804 if (!current)
805 R(PC) = address;
806
807 LOG_DEBUG("RESUME PC %08" PRIx32 "%s", R(PC), !current ? "!" : "");
808
809 /* clear breakpoints/watchpoints and VCR*/
810 arm11_sc7_clear_vbw(arm11);
811
812 /* Set up breakpoints */
813 if (!debug_execution)
814 {
815 /* check if one matches PC and step over it if necessary */
816
817 breakpoint_t * bp;
818
819 for (bp = target->breakpoints; bp; bp = bp->next)
820 {
821 if (bp->address == R(PC))
822 {
823 LOG_DEBUG("must step over %08" PRIx32 "", bp->address);
824 arm11_step(target, 1, 0, 0);
825 break;
826 }
827 }
828
829 /* set all breakpoints */
830
831 size_t brp_num = 0;
832
833 for (bp = target->breakpoints; bp; bp = bp->next)
834 {
835 arm11_sc7_action_t brp[2];
836
837 brp[0].write = 1;
838 brp[0].address = ARM11_SC7_BVR0 + brp_num;
839 brp[0].value = bp->address;
840 brp[1].write = 1;
841 brp[1].address = ARM11_SC7_BCR0 + brp_num;
842 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
843
844 arm11_sc7_run(arm11, brp, asizeof(brp));
845
846 LOG_DEBUG("Add BP " ZU " at %08" PRIx32 "", brp_num, bp->address);
847
848 brp_num++;
849 }
850
851 arm11_sc7_set_vcr(arm11, arm11_vcr);
852 }
853
854 arm11_leave_debug_state(arm11);
855
856 arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
857
858 CHECK_RETVAL(jtag_execute_queue());
859
860 while (1)
861 {
862 uint32_t dscr;
863
864 CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
865
866 LOG_DEBUG("DSCR %08" PRIx32 "", dscr);
867
868 if (dscr & ARM11_DSCR_CORE_RESTARTED)
869 break;
870 }
871
872 if (!debug_execution)
873 {
874 target->state = TARGET_RUNNING;
875 target->debug_reason = DBG_REASON_NOTHALTED;
876
877 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
878 }
879 else
880 {
881 target->state = TARGET_DEBUG_RUNNING;
882 target->debug_reason = DBG_REASON_NOTHALTED;
883
884 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
885 }
886
887 return ERROR_OK;
888 }
889
890
891 static int armv4_5_to_arm11(int reg)
892 {
893 if (reg < 16)
894 return reg;
895 switch (reg)
896 {
897 case ARMV4_5_CPSR:
898 return ARM11_RC_CPSR;
899 case 16:
900 /* FIX!!! handle thumb better! */
901 return ARM11_RC_CPSR;
902 default:
903 LOG_ERROR("BUG: register translation from armv4_5 to arm11 not supported %d", reg);
904 exit(-1);
905 }
906 }
907
908
909 static uint32_t arm11_sim_get_reg(struct arm_sim_interface *sim, int reg)
910 {
911 arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
912
913 reg=armv4_5_to_arm11(reg);
914
915 return buf_get_u32(arm11->reg_list[reg].value, 0, 32);
916 }
917
918 static void arm11_sim_set_reg(struct arm_sim_interface *sim, int reg, uint32_t value)
919 {
920 arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
921
922 reg=armv4_5_to_arm11(reg);
923
924 buf_set_u32(arm11->reg_list[reg].value, 0, 32, value);
925 }
926
927 static uint32_t arm11_sim_get_cpsr(struct arm_sim_interface *sim, int pos, int bits)
928 {
929 arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
930
931 return buf_get_u32(arm11->reg_list[ARM11_RC_CPSR].value, pos, bits);
932 }
933
934 static enum armv4_5_state arm11_sim_get_state(struct arm_sim_interface *sim)
935 {
936 // arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
937
938 /* FIX!!!! we should implement thumb for arm11 */
939 return ARMV4_5_STATE_ARM;
940 }
941
942 static void arm11_sim_set_state(struct arm_sim_interface *sim, enum armv4_5_state mode)
943 {
944 // arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
945
946 /* FIX!!!! we should implement thumb for arm11 */
947 LOG_ERROR("Not implemetned!");
948 }
949
950
951 static enum armv4_5_mode arm11_sim_get_mode(struct arm_sim_interface *sim)
952 {
953 //arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
954
955 /* FIX!!!! we should implement something that returns the current mode here!!! */
956 return ARMV4_5_MODE_USR;
957 }
958
959 static int arm11_simulate_step(target_t *target, uint32_t *dry_run_pc)
960 {
961 struct arm_sim_interface sim;
962
963 sim.user_data=target->arch_info;
964 sim.get_reg=&arm11_sim_get_reg;
965 sim.set_reg=&arm11_sim_set_reg;
966 sim.get_reg_mode=&arm11_sim_get_reg;
967 sim.set_reg_mode=&arm11_sim_set_reg;
968 sim.get_cpsr=&arm11_sim_get_cpsr;
969 sim.get_mode=&arm11_sim_get_mode;
970 sim.get_state=&arm11_sim_get_state;
971 sim.set_state=&arm11_sim_set_state;
972
973 return arm_simulate_step_core(target, dry_run_pc, &sim);
974
975 }
976
977 int arm11_step(struct target_s *target, int current, uint32_t address, int handle_breakpoints)
978 {
979 FNC_INFO;
980
981 LOG_DEBUG("target->state: %s",
982 target_state_name(target));
983
984 if (target->state != TARGET_HALTED)
985 {
986 LOG_WARNING("target was not halted");
987 return ERROR_TARGET_NOT_HALTED;
988 }
989
990 arm11_common_t * arm11 = target->arch_info;
991
992 if (!current)
993 R(PC) = address;
994
995 LOG_DEBUG("STEP PC %08" PRIx32 "%s", R(PC), !current ? "!" : "");
996
997
998 /** \todo TODO: Thumb not supported here */
999
1000 uint32_t next_instruction;
1001
1002 CHECK_RETVAL(arm11_read_memory_word(arm11, R(PC), &next_instruction));
1003
1004 /* skip over BKPT */
1005 if ((next_instruction & 0xFFF00070) == 0xe1200070)
1006 {
1007 R(PC) += 4;
1008 arm11->reg_list[ARM11_RC_PC].valid = 1;
1009 arm11->reg_list[ARM11_RC_PC].dirty = 0;
1010 LOG_DEBUG("Skipping BKPT");
1011 }
1012 /* skip over Wait for interrupt / Standby */
1013 /* mcr 15, 0, r?, cr7, cr0, {4} */
1014 else if ((next_instruction & 0xFFFF0FFF) == 0xee070f90)
1015 {
1016 R(PC) += 4;
1017 arm11->reg_list[ARM11_RC_PC].valid = 1;
1018 arm11->reg_list[ARM11_RC_PC].dirty = 0;
1019 LOG_DEBUG("Skipping WFI");
1020 }
1021 /* ignore B to self */
1022 else if ((next_instruction & 0xFEFFFFFF) == 0xeafffffe)
1023 {
1024 LOG_DEBUG("Not stepping jump to self");
1025 }
1026 else
1027 {
1028 /** \todo TODO: check if break-/watchpoints make any sense at all in combination
1029 * with this. */
1030
1031 /** \todo TODO: check if disabling IRQs might be a good idea here. Alternatively
1032 * the VCR might be something worth looking into. */
1033
1034
1035 /* Set up breakpoint for stepping */
1036
1037 arm11_sc7_action_t brp[2];
1038
1039 brp[0].write = 1;
1040 brp[0].address = ARM11_SC7_BVR0;
1041 brp[1].write = 1;
1042 brp[1].address = ARM11_SC7_BCR0;
1043
1044 if (arm11_config_hardware_step)
1045 {
1046 /* hardware single stepping be used if possible or is it better to
1047 * always use the same code path? Hardware single stepping is not supported
1048 * on all hardware
1049 */
1050 brp[0].value = R(PC);
1051 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (2 << 21);
1052 } else
1053 {
1054 /* sets a breakpoint on the next PC(calculated by simulation),
1055 */
1056 uint32_t next_pc;
1057 int retval;
1058 retval = arm11_simulate_step(target, &next_pc);
1059 if (retval != ERROR_OK)
1060 return retval;
1061
1062 brp[0].value = next_pc;
1063 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
1064 }
1065
1066 CHECK_RETVAL(arm11_sc7_run(arm11, brp, asizeof(brp)));
1067
1068 /* resume */
1069
1070
1071 if (arm11_config_step_irq_enable)
1072 R(DSCR) &= ~ARM11_DSCR_INTERRUPTS_DISABLE; /* should be redundant */
1073 else
1074 R(DSCR) |= ARM11_DSCR_INTERRUPTS_DISABLE;
1075
1076
1077 CHECK_RETVAL(arm11_leave_debug_state(arm11));
1078
1079 arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
1080
1081 CHECK_RETVAL(jtag_execute_queue());
1082
1083 /** \todo TODO: add a timeout */
1084
1085 /* wait for halt */
1086
1087 while (1)
1088 {
1089 uint32_t dscr;
1090
1091 CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
1092
1093 LOG_DEBUG("DSCR %08" PRIx32 "e", dscr);
1094
1095 if ((dscr & (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED)) ==
1096 (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED))
1097 break;
1098 }
1099
1100 /* clear breakpoint */
1101 arm11_sc7_clear_vbw(arm11);
1102
1103 /* save state */
1104 CHECK_RETVAL(arm11_on_enter_debug_state(arm11));
1105
1106 /* restore default state */
1107 R(DSCR) &= ~ARM11_DSCR_INTERRUPTS_DISABLE;
1108
1109 }
1110
1111 // target->state = TARGET_HALTED;
1112 target->debug_reason = DBG_REASON_SINGLESTEP;
1113
1114 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_HALTED));
1115
1116 return ERROR_OK;
1117 }
1118
1119 /* target reset control */
1120 int arm11_assert_reset(struct target_s *target)
1121 {
1122 FNC_INFO;
1123
1124 #if 0
1125 /* assert reset lines */
1126 /* resets only the DBGTAP, not the ARM */
1127
1128 jtag_add_reset(1, 0);
1129 jtag_add_sleep(5000);
1130
1131 arm11_common_t * arm11 = target->arch_info;
1132 arm11->trst_active = true;
1133 #endif
1134
1135 if (target->reset_halt)
1136 {
1137 CHECK_RETVAL(target_halt(target));
1138 }
1139
1140 return ERROR_OK;
1141 }
1142
1143 int arm11_deassert_reset(struct target_s *target)
1144 {
1145 FNC_INFO;
1146
1147 #if 0
1148 LOG_DEBUG("target->state: %s",
1149 target_state_name(target));
1150
1151
1152 /* deassert reset lines */
1153 jtag_add_reset(0, 0);
1154
1155 arm11_common_t * arm11 = target->arch_info;
1156 arm11->trst_active = false;
1157
1158 if (arm11->halt_requested)
1159 return arm11_halt(target);
1160 #endif
1161
1162 return ERROR_OK;
1163 }
1164
1165 int arm11_soft_reset_halt(struct target_s *target)
1166 {
1167 FNC_INFO_NOTIMPLEMENTED;
1168
1169 return ERROR_OK;
1170 }
1171
1172 /* target register access for gdb */
1173 int arm11_get_gdb_reg_list(struct target_s *target, struct reg_s **reg_list[], int *reg_list_size)
1174 {
1175 FNC_INFO;
1176
1177 arm11_common_t * arm11 = target->arch_info;
1178
1179 *reg_list_size = ARM11_GDB_REGISTER_COUNT;
1180 *reg_list = malloc(sizeof(reg_t*) * ARM11_GDB_REGISTER_COUNT);
1181
1182 for (size_t i = 16; i < 24; i++)
1183 {
1184 (*reg_list)[i] = &arm11_gdb_dummy_fp_reg;
1185 }
1186
1187 (*reg_list)[24] = &arm11_gdb_dummy_fps_reg;
1188
1189 for (size_t i = 0; i < ARM11_REGCACHE_COUNT; i++)
1190 {
1191 if (arm11_reg_defs[i].gdb_num == -1)
1192 continue;
1193
1194 (*reg_list)[arm11_reg_defs[i].gdb_num] = arm11->reg_list + i;
1195 }
1196
1197 return ERROR_OK;
1198 }
1199
1200 /* target memory access
1201 * size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
1202 * count: number of items of <size>
1203 */
1204 int arm11_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
1205 {
1206 /** \todo TODO: check if buffer cast to uint32_t* and uint16_t* might cause alignment problems */
1207
1208 FNC_INFO;
1209
1210 if (target->state != TARGET_HALTED)
1211 {
1212 LOG_WARNING("target was not halted");
1213 return ERROR_TARGET_NOT_HALTED;
1214 }
1215
1216 LOG_DEBUG("ADDR %08" PRIx32 " SIZE %08" PRIx32 " COUNT %08" PRIx32 "", address, size, count);
1217
1218 arm11_common_t * arm11 = target->arch_info;
1219
1220 arm11_run_instr_data_prepare(arm11);
1221
1222 /* MRC p14,0,r0,c0,c5,0 */
1223 arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
1224
1225 switch (size)
1226 {
1227 case 1:
1228 /** \todo TODO: check if dirty is the right choice to force a rewrite on arm11_resume() */
1229 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1230
1231 for (size_t i = 0; i < count; i++)
1232 {
1233 /* ldrb r1, [r0], #1 */
1234 /* ldrb r1, [r0] */
1235 arm11_run_instr_no_data1(arm11,
1236 !arm11_config_memrw_no_increment ? 0xe4d01001 : 0xe5d01000);
1237
1238 uint32_t res;
1239 /* MCR p14,0,R1,c0,c5,0 */
1240 arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
1241
1242 *buffer++ = res;
1243 }
1244
1245 break;
1246
1247 case 2:
1248 {
1249 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1250
1251 for (size_t i = 0; i < count; i++)
1252 {
1253 /* ldrh r1, [r0], #2 */
1254 arm11_run_instr_no_data1(arm11,
1255 !arm11_config_memrw_no_increment ? 0xe0d010b2 : 0xe1d010b0);
1256
1257 uint32_t res;
1258
1259 /* MCR p14,0,R1,c0,c5,0 */
1260 arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
1261
1262 uint16_t svalue = res;
1263 memcpy(buffer + i * sizeof(uint16_t), &svalue, sizeof(uint16_t));
1264 }
1265
1266 break;
1267 }
1268
1269 case 4:
1270 {
1271 uint32_t instr = !arm11_config_memrw_no_increment ? 0xecb05e01 : 0xed905e00;
1272 /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
1273 uint32_t *words = (uint32_t *)buffer;
1274
1275 /* LDC p14,c5,[R0],#4 */
1276 /* LDC p14,c5,[R0] */
1277 arm11_run_instr_data_from_core(arm11, instr, words, count);
1278 break;
1279 }
1280 }
1281
1282 arm11_run_instr_data_finish(arm11);
1283
1284 return ERROR_OK;
1285 }
1286
1287 int arm11_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
1288 {
1289 FNC_INFO;
1290
1291 if (target->state != TARGET_HALTED)
1292 {
1293 LOG_WARNING("target was not halted");
1294 return ERROR_TARGET_NOT_HALTED;
1295 }
1296
1297 LOG_DEBUG("ADDR %08" PRIx32 " SIZE %08" PRIx32 " COUNT %08" PRIx32 "", address, size, count);
1298
1299 arm11_common_t * arm11 = target->arch_info;
1300
1301 arm11_run_instr_data_prepare(arm11);
1302
1303 /* MRC p14,0,r0,c0,c5,0 */
1304 arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
1305
1306 switch (size)
1307 {
1308 case 1:
1309 {
1310 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1311
1312 for (size_t i = 0; i < count; i++)
1313 {
1314 /* MRC p14,0,r1,c0,c5,0 */
1315 arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buffer++);
1316
1317 /* strb r1, [r0], #1 */
1318 /* strb r1, [r0] */
1319 arm11_run_instr_no_data1(arm11,
1320 !arm11_config_memrw_no_increment ? 0xe4c01001 : 0xe5c01000);
1321 }
1322
1323 break;
1324 }
1325
1326 case 2:
1327 {
1328 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1329
1330 for (size_t i = 0; i < count; i++)
1331 {
1332 uint16_t value;
1333 memcpy(&value, buffer + i * sizeof(uint16_t), sizeof(uint16_t));
1334
1335 /* MRC p14,0,r1,c0,c5,0 */
1336 arm11_run_instr_data_to_core1(arm11, 0xee101e15, value);
1337
1338 /* strh r1, [r0], #2 */
1339 /* strh r1, [r0] */
1340 arm11_run_instr_no_data1(arm11,
1341 !arm11_config_memrw_no_increment ? 0xe0c010b2 : 0xe1c010b0);
1342 }
1343
1344 break;
1345 }
1346
1347 case 4: {
1348 uint32_t instr = !arm11_config_memrw_no_increment ? 0xeca05e01 : 0xed805e00;
1349
1350 /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
1351 uint32_t *words = (uint32_t*)buffer;
1352
1353 if (!arm11_config_memwrite_burst)
1354 {
1355 /* STC p14,c5,[R0],#4 */
1356 /* STC p14,c5,[R0]*/
1357 arm11_run_instr_data_to_core(arm11, instr, words, count);
1358 }
1359 else
1360 {
1361 /* STC p14,c5,[R0],#4 */
1362 /* STC p14,c5,[R0]*/
1363 arm11_run_instr_data_to_core_noack(arm11, instr, words, count);
1364 }
1365
1366 break;
1367 }
1368 }
1369
1370 #if 1
1371 /* r0 verification */
1372 if (!arm11_config_memrw_no_increment)
1373 {
1374 uint32_t r0;
1375
1376 /* MCR p14,0,R0,c0,c5,0 */
1377 arm11_run_instr_data_from_core(arm11, 0xEE000E15, &r0, 1);
1378
1379 if (address + size * count != r0)
1380 {
1381 LOG_ERROR("Data transfer failed. (%d)", (int)((r0 - address) - size * count));
1382
1383 if (arm11_config_memwrite_burst)
1384 LOG_ERROR("use 'arm11 memwrite burst disable' to disable fast burst mode");
1385
1386 if (arm11_config_memwrite_error_fatal)
1387 return ERROR_FAIL;
1388 }
1389 }
1390 #endif
1391
1392 arm11_run_instr_data_finish(arm11);
1393
1394 return ERROR_OK;
1395 }
1396
1397
1398 /* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
1399 int arm11_bulk_write_memory(struct target_s *target, uint32_t address, uint32_t count, uint8_t *buffer)
1400 {
1401 FNC_INFO;
1402
1403 if (target->state != TARGET_HALTED)
1404 {
1405 LOG_WARNING("target was not halted");
1406 return ERROR_TARGET_NOT_HALTED;
1407 }
1408
1409 return arm11_write_memory(target, address, 4, count, buffer);
1410 }
1411
1412 /* here we have nothing target specific to contribute, so we fail and then the
1413 * fallback code will read data from the target and calculate the CRC on the
1414 * host.
1415 */
1416 int arm11_checksum_memory(struct target_s *target, uint32_t address, uint32_t count, uint32_t* checksum)
1417 {
1418 return ERROR_FAIL;
1419 }
1420
1421 /* target break-/watchpoint control
1422 * rw: 0 = write, 1 = read, 2 = access
1423 */
1424 int arm11_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
1425 {
1426 FNC_INFO;
1427
1428 arm11_common_t * arm11 = target->arch_info;
1429
1430 #if 0
1431 if (breakpoint->type == BKPT_SOFT)
1432 {
1433 LOG_INFO("sw breakpoint requested, but software breakpoints not enabled");
1434 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1435 }
1436 #endif
1437
1438 if (!arm11->free_brps)
1439 {
1440 LOG_DEBUG("no breakpoint unit available for hardware breakpoint");
1441 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1442 }
1443
1444 if (breakpoint->length != 4)
1445 {
1446 LOG_DEBUG("only breakpoints of four bytes length supported");
1447 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1448 }
1449
1450 arm11->free_brps--;
1451
1452 return ERROR_OK;
1453 }
1454
1455 int arm11_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
1456 {
1457 FNC_INFO;
1458
1459 arm11_common_t * arm11 = target->arch_info;
1460
1461 arm11->free_brps++;
1462
1463 return ERROR_OK;
1464 }
1465
1466 int arm11_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
1467 {
1468 FNC_INFO_NOTIMPLEMENTED;
1469
1470 return ERROR_OK;
1471 }
1472
1473 int arm11_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
1474 {
1475 FNC_INFO_NOTIMPLEMENTED;
1476
1477 return ERROR_OK;
1478 }
1479
1480 // HACKHACKHACK - FIXME mode/state
1481 /* target algorithm support */
1482 int arm11_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params,
1483 int num_reg_params, reg_param_t *reg_params, uint32_t entry_point, uint32_t exit_point,
1484 int timeout_ms, void *arch_info)
1485 {
1486 arm11_common_t *arm11 = target->arch_info;
1487 // enum armv4_5_state core_state = arm11->core_state;
1488 // enum armv4_5_mode core_mode = arm11->core_mode;
1489 uint32_t context[16];
1490 uint32_t cpsr;
1491 int exit_breakpoint_size = 0;
1492 int retval = ERROR_OK;
1493 LOG_DEBUG("Running algorithm");
1494
1495
1496 if (target->state != TARGET_HALTED)
1497 {
1498 LOG_WARNING("target not halted");
1499 return ERROR_TARGET_NOT_HALTED;
1500 }
1501
1502 // FIXME
1503 // if (armv4_5_mode_to_number(arm11->core_mode)==-1)
1504 // return ERROR_FAIL;
1505
1506 // Save regs
1507 for (size_t i = 0; i < 16; i++)
1508 {
1509 context[i] = buf_get_u32((uint8_t*)(&arm11->reg_values[i]),0,32);
1510 LOG_DEBUG("Save %zi: 0x%" PRIx32 "",i,context[i]);
1511 }
1512
1513 cpsr = buf_get_u32((uint8_t*)(arm11->reg_values + ARM11_RC_CPSR),0,32);
1514 LOG_DEBUG("Save CPSR: 0x%" PRIx32 "", cpsr);
1515
1516 for (int i = 0; i < num_mem_params; i++)
1517 {
1518 target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
1519 }
1520
1521 // Set register parameters
1522 for (int i = 0; i < num_reg_params; i++)
1523 {
1524 reg_t *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0);
1525 if (!reg)
1526 {
1527 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
1528 exit(-1);
1529 }
1530
1531 if (reg->size != reg_params[i].size)
1532 {
1533 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
1534 exit(-1);
1535 }
1536 arm11_set_reg(reg,reg_params[i].value);
1537 // printf("%i: Set %s =%08x\n", i, reg_params[i].reg_name,val);
1538 }
1539
1540 exit_breakpoint_size = 4;
1541
1542 /* arm11->core_state = arm11_algorithm_info->core_state;
1543 if (arm11->core_state == ARMV4_5_STATE_ARM)
1544 exit_breakpoint_size = 4;
1545 else if (arm11->core_state == ARMV4_5_STATE_THUMB)
1546 exit_breakpoint_size = 2;
1547 else
1548 {
1549 LOG_ERROR("BUG: can't execute algorithms when not in ARM or Thumb state");
1550 exit(-1);
1551 }
1552 */
1553
1554
1555 /* arm11 at this point only supports ARM not THUMB mode
1556 however if this test needs to be reactivated the current state can be read back
1557 from CPSR */
1558 #if 0
1559 if (arm11_algorithm_info->core_mode != ARMV4_5_MODE_ANY)
1560 {
1561 LOG_DEBUG("setting core_mode: 0x%2.2x", arm11_algorithm_info->core_mode);
1562 buf_set_u32(arm11->reg_list[ARM11_RC_CPSR].value, 0, 5, arm11_algorithm_info->core_mode);
1563 arm11->reg_list[ARM11_RC_CPSR].dirty = 1;
1564 arm11->reg_list[ARM11_RC_CPSR].valid = 1;
1565 }
1566 #endif
1567
1568 if ((retval = breakpoint_add(target, exit_point, exit_breakpoint_size, BKPT_HARD)) != ERROR_OK)
1569 {
1570 LOG_ERROR("can't add breakpoint to finish algorithm execution");
1571 retval = ERROR_TARGET_FAILURE;
1572 goto restore;
1573 }
1574
1575 // no debug, otherwise breakpoint is not set
1576 CHECK_RETVAL(target_resume(target, 0, entry_point, 1, 0));
1577
1578 CHECK_RETVAL(target_wait_state(target, TARGET_HALTED, timeout_ms));
1579
1580 if (target->state != TARGET_HALTED)
1581 {
1582 CHECK_RETVAL(target_halt(target));
1583
1584 CHECK_RETVAL(target_wait_state(target, TARGET_HALTED, 500));
1585
1586 retval = ERROR_TARGET_TIMEOUT;
1587
1588 goto del_breakpoint;
1589 }
1590
1591 if (buf_get_u32(arm11->reg_list[15].value, 0, 32) != exit_point)
1592 {
1593 LOG_WARNING("target reentered debug state, but not at the desired exit point: 0x%4.4" PRIx32 "",
1594 buf_get_u32(arm11->reg_list[15].value, 0, 32));
1595 retval = ERROR_TARGET_TIMEOUT;
1596 goto del_breakpoint;
1597 }
1598
1599 for (int i = 0; i < num_mem_params; i++)
1600 {
1601 if (mem_params[i].direction != PARAM_OUT)
1602 target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
1603 }
1604
1605 for (int i = 0; i < num_reg_params; i++)
1606 {
1607 if (reg_params[i].direction != PARAM_OUT)
1608 {
1609 reg_t *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0);
1610 if (!reg)
1611 {
1612 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
1613 exit(-1);
1614 }
1615
1616 if (reg->size != reg_params[i].size)
1617 {
1618 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
1619 exit(-1);
1620 }
1621
1622 buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
1623 }
1624 }
1625
1626 del_breakpoint:
1627 breakpoint_remove(target, exit_point);
1628
1629 restore:
1630 // Restore context
1631 for (size_t i = 0; i < 16; i++)
1632 {
1633 LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32 "",
1634 arm11->reg_list[i].name, context[i]);
1635 arm11_set_reg(&arm11->reg_list[i], (uint8_t*)&context[i]);
1636 }
1637 LOG_DEBUG("restoring CPSR with value 0x%8.8" PRIx32 "", cpsr);
1638 arm11_set_reg(&arm11->reg_list[ARM11_RC_CPSR], (uint8_t*)&cpsr);
1639
1640 // arm11->core_state = core_state;
1641 // arm11->core_mode = core_mode;
1642
1643 return retval;
1644 }
1645
1646 int arm11_target_create(struct target_s *target, Jim_Interp *interp)
1647 {
1648 FNC_INFO;
1649
1650 NEW(arm11_common_t, arm11, 1);
1651
1652 arm11->target = target;
1653
1654 if (target->tap == NULL)
1655 return ERROR_FAIL;
1656
1657 if (target->tap->ir_length != 5)
1658 {
1659 LOG_ERROR("'target arm11' expects IR LENGTH = 5");
1660 return ERROR_COMMAND_SYNTAX_ERROR;
1661 }
1662
1663 target->arch_info = arm11;
1664
1665 return ERROR_OK;
1666 }
1667
1668 int arm11_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
1669 {
1670 /* Initialize anything we can set up without talking to the target */
1671 return arm11_build_reg_cache(target);
1672 }
1673
1674 /* talk to the target and set things up */
1675 int arm11_examine(struct target_s *target)
1676 {
1677 FNC_INFO;
1678
1679 arm11_common_t * arm11 = target->arch_info;
1680
1681 /* check IDCODE */
1682
1683 arm11_add_IR(arm11, ARM11_IDCODE, ARM11_TAP_DEFAULT);
1684
1685 scan_field_t idcode_field;
1686
1687 arm11_setup_field(arm11, 32, NULL, &arm11->device_id, &idcode_field);
1688
1689 arm11_add_dr_scan_vc(1, &idcode_field, TAP_DRPAUSE);
1690
1691 /* check DIDR */
1692
1693 arm11_add_debug_SCAN_N(arm11, 0x00, ARM11_TAP_DEFAULT);
1694
1695 arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
1696
1697 scan_field_t chain0_fields[2];
1698
1699 arm11_setup_field(arm11, 32, NULL, &arm11->didr, chain0_fields + 0);
1700 arm11_setup_field(arm11, 8, NULL, &arm11->implementor, chain0_fields + 1);
1701
1702 arm11_add_dr_scan_vc(asizeof(chain0_fields), chain0_fields, TAP_IDLE);
1703
1704 CHECK_RETVAL(jtag_execute_queue());
1705
1706 switch (arm11->device_id & 0x0FFFF000)
1707 {
1708 case 0x07B36000: LOG_INFO("found ARM1136"); break;
1709 case 0x07B56000: LOG_INFO("found ARM1156"); break;
1710 case 0x07B76000: LOG_INFO("found ARM1176"); break;
1711 default:
1712 {
1713 LOG_ERROR("'target arm11' expects IDCODE 0x*7B*7****");
1714 return ERROR_FAIL;
1715 }
1716 }
1717
1718 arm11->debug_version = (arm11->didr >> 16) & 0x0F;
1719
1720 if (arm11->debug_version != ARM11_DEBUG_V6 &&
1721 arm11->debug_version != ARM11_DEBUG_V61)
1722 {
1723 LOG_ERROR("Only ARMv6 v6 and v6.1 architectures supported.");
1724 return ERROR_FAIL;
1725 }
1726
1727 arm11->brp = ((arm11->didr >> 24) & 0x0F) + 1;
1728 arm11->wrp = ((arm11->didr >> 28) & 0x0F) + 1;
1729
1730 /** \todo TODO: reserve one brp slot if we allow breakpoints during step */
1731 arm11->free_brps = arm11->brp;
1732 arm11->free_wrps = arm11->wrp;
1733
1734 LOG_DEBUG("IDCODE %08" PRIx32 " IMPLEMENTOR %02x DIDR %08" PRIx32 "",
1735 arm11->device_id,
1736 (int)(arm11->implementor),
1737 arm11->didr);
1738
1739 /* as a side-effect this reads DSCR and thus
1740 * clears the ARM11_DSCR_STICKY_PRECISE_DATA_ABORT / Sticky Precise Data Abort Flag
1741 * as suggested by the spec.
1742 */
1743
1744 arm11_check_init(arm11, NULL);
1745
1746 target_set_examined(target);
1747
1748 return ERROR_OK;
1749 }
1750
1751 int arm11_quit(void)
1752 {
1753 FNC_INFO_NOTIMPLEMENTED;
1754
1755 return ERROR_OK;
1756 }
1757
1758 /** Load a register that is marked !valid in the register cache */
1759 int arm11_get_reg(reg_t *reg)
1760 {
1761 FNC_INFO;
1762
1763 target_t * target = ((arm11_reg_state_t *)reg->arch_info)->target;
1764
1765 if (target->state != TARGET_HALTED)
1766 {
1767 LOG_WARNING("target was not halted");
1768 return ERROR_TARGET_NOT_HALTED;
1769 }
1770
1771 /** \todo TODO: Check this. We assume that all registers are fetched at debug entry. */
1772
1773 #if 0
1774 arm11_common_t *arm11 = target->arch_info;
1775 const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index;
1776 #endif
1777
1778 return ERROR_OK;
1779 }
1780
1781 /** Change a value in the register cache */
1782 int arm11_set_reg(reg_t *reg, uint8_t *buf)
1783 {
1784 FNC_INFO;
1785
1786 target_t * target = ((arm11_reg_state_t *)reg->arch_info)->target;
1787 arm11_common_t *arm11 = target->arch_info;
1788 // const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index;
1789
1790 arm11->reg_values[((arm11_reg_state_t *)reg->arch_info)->def_index] = buf_get_u32(buf, 0, 32);
1791 reg->valid = 1;
1792 reg->dirty = 1;
1793
1794 return ERROR_OK;
1795 }
1796
1797 int arm11_build_reg_cache(target_t *target)
1798 {
1799 arm11_common_t *arm11 = target->arch_info;
1800
1801 NEW(reg_cache_t, cache, 1);
1802 NEW(reg_t, reg_list, ARM11_REGCACHE_COUNT);
1803 NEW(arm11_reg_state_t, arm11_reg_states, ARM11_REGCACHE_COUNT);
1804
1805 if (arm11_regs_arch_type == -1)
1806 arm11_regs_arch_type = register_reg_arch_type(arm11_get_reg, arm11_set_reg);
1807
1808 register_init_dummy(&arm11_gdb_dummy_fp_reg);
1809 register_init_dummy(&arm11_gdb_dummy_fps_reg);
1810
1811 arm11->reg_list = reg_list;
1812
1813 /* Build the process context cache */
1814 cache->name = "arm11 registers";
1815 cache->next = NULL;
1816 cache->reg_list = reg_list;
1817 cache->num_regs = ARM11_REGCACHE_COUNT;
1818
1819 reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
1820 (*cache_p) = cache;
1821
1822 arm11->core_cache = cache;
1823 // armv7m->process_context = cache;
1824
1825 size_t i;
1826
1827 /* Not very elegant assertion */
1828 if (ARM11_REGCACHE_COUNT != asizeof(arm11->reg_values) ||
1829 ARM11_REGCACHE_COUNT != asizeof(arm11_reg_defs) ||
1830 ARM11_REGCACHE_COUNT != ARM11_RC_MAX)
1831 {
1832 LOG_ERROR("BUG: arm11->reg_values inconsistent (%d " ZU " " ZU " %d)", ARM11_REGCACHE_COUNT, asizeof(arm11->reg_values), asizeof(arm11_reg_defs), ARM11_RC_MAX);
1833 exit(-1);
1834 }
1835
1836 for (i = 0; i < ARM11_REGCACHE_COUNT; i++)
1837 {
1838 reg_t * r = reg_list + i;
1839 const arm11_reg_defs_t * rd = arm11_reg_defs + i;
1840 arm11_reg_state_t * rs = arm11_reg_states + i;
1841
1842 r->name = rd->name;
1843 r->size = 32;
1844 r->value = (uint8_t *)(arm11->reg_values + i);
1845 r->dirty = 0;
1846 r->valid = 0;
1847 r->bitfield_desc = NULL;
1848 r->num_bitfields = 0;
1849 r->arch_type = arm11_regs_arch_type;
1850 r->arch_info = rs;
1851
1852 rs->def_index = i;
1853 rs->target = target;
1854 }
1855
1856 return ERROR_OK;
1857 }
1858
1859 int arm11_handle_bool(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, bool * var, char * name)
1860 {
1861 if (argc == 0)
1862 {
1863 LOG_INFO("%s is %s.", name, *var ? "enabled" : "disabled");
1864 return ERROR_OK;
1865 }
1866
1867 if (argc != 1)
1868 return ERROR_COMMAND_SYNTAX_ERROR;
1869
1870 switch (args[0][0])
1871 {
1872 case '0': /* 0 */
1873 case 'f': /* false */
1874 case 'F':
1875 case 'd': /* disable */
1876 case 'D':
1877 *var = false;
1878 break;
1879
1880 case '1': /* 1 */
1881 case 't': /* true */
1882 case 'T':
1883 case 'e': /* enable */
1884 case 'E':
1885 *var = true;
1886 break;
1887 }
1888
1889 LOG_INFO("%s %s.", *var ? "Enabled" : "Disabled", name);
1890
1891 return ERROR_OK;
1892 }
1893
1894 #define BOOL_WRAPPER(name, print_name) \
1895 int arm11_handle_bool_##name(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) \
1896 { \
1897 return arm11_handle_bool(cmd_ctx, cmd, args, argc, &arm11_config_##name, print_name); \
1898 }
1899
1900 #define RC_TOP(name, descr, more) \
1901 { \
1902 command_t * new_cmd = register_command(cmd_ctx, top_cmd, name, NULL, COMMAND_ANY, descr); \
1903 command_t * top_cmd = new_cmd; \
1904 more \
1905 }
1906
1907 #define RC_FINAL(name, descr, handler) \
1908 register_command(cmd_ctx, top_cmd, name, handler, COMMAND_ANY, descr);
1909
1910 #define RC_FINAL_BOOL(name, descr, var) \
1911 register_command(cmd_ctx, top_cmd, name, arm11_handle_bool_##var, COMMAND_ANY, descr);
1912
1913 BOOL_WRAPPER(memwrite_burst, "memory write burst mode")
1914 BOOL_WRAPPER(memwrite_error_fatal, "fatal error mode for memory writes")
1915 BOOL_WRAPPER(memrw_no_increment, "\"no increment\" mode for memory transfers")
1916 BOOL_WRAPPER(step_irq_enable, "IRQs while stepping")
1917 BOOL_WRAPPER(hardware_step, "hardware single step")
1918
1919 int arm11_handle_vcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1920 {
1921 if (argc == 1)
1922 {
1923 arm11_vcr = strtoul(args[0], NULL, 0);
1924 }
1925 else if (argc != 0)
1926 {
1927 return ERROR_COMMAND_SYNTAX_ERROR;
1928 }
1929
1930 LOG_INFO("VCR 0x%08" PRIx32 "", arm11_vcr);
1931 return ERROR_OK;
1932 }
1933
1934 const uint32_t arm11_coproc_instruction_limits[] =
1935 {
1936 15, /* coprocessor */
1937 7, /* opcode 1 */
1938 15, /* CRn */
1939 15, /* CRm */
1940 7, /* opcode 2 */
1941 0xFFFFFFFF, /* value */
1942 };
1943
1944 const char arm11_mrc_syntax[] = "Syntax: mrc <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2>. All parameters are numbers only.";
1945 const char arm11_mcr_syntax[] = "Syntax: mcr <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2> <32bit value to write>. All parameters are numbers only.";
1946
1947 arm11_common_t * arm11_find_target(const char * arg)
1948 {
1949 jtag_tap_t * tap;
1950 target_t * t;
1951
1952 tap = jtag_tap_by_string(arg);
1953
1954 if (!tap)
1955 return 0;
1956
1957 for (t = all_targets; t; t = t->next)
1958 {
1959 if (t->tap != tap)
1960 continue;
1961
1962 /* if (t->type == arm11_target) */
1963 if (0 == strcmp(target_get_name(t), "arm11"))
1964 return t->arch_info;
1965 }
1966
1967 return 0;
1968 }
1969
1970 int arm11_handle_mrc_mcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, bool read)
1971 {
1972 if (argc != (read ? 6 : 7))
1973 {
1974 LOG_ERROR("Invalid number of arguments. %s", read ? arm11_mrc_syntax : arm11_mcr_syntax);
1975 return -1;
1976 }
1977
1978 arm11_common_t * arm11 = arm11_find_target(args[0]);
1979
1980 if (!arm11)
1981 {
1982 LOG_ERROR("Parameter 1 is not a the JTAG chain position of an ARM11 device. %s",
1983 read ? arm11_mrc_syntax : arm11_mcr_syntax);
1984
1985 return -1;
1986 }
1987
1988 if (arm11->target->state != TARGET_HALTED)
1989 {
1990 LOG_WARNING("target was not halted");
1991 return ERROR_TARGET_NOT_HALTED;
1992 }
1993
1994 uint32_t values[6];
1995
1996 for (size_t i = 0; i < (read ? 5 : 6); i++)
1997 {
1998 values[i] = strtoul(args[i + 1], NULL, 0);
1999
2000 if (values[i] > arm11_coproc_instruction_limits[i])
2001 {
2002 LOG_ERROR("Parameter %ld out of bounds (%" PRId32 " max). %s",
2003 (long)(i + 2),
2004 arm11_coproc_instruction_limits[i],
2005 read ? arm11_mrc_syntax : arm11_mcr_syntax);
2006 return -1;
2007 }
2008 }
2009
2010 uint32_t instr = 0xEE000010 |
2011 (values[0] << 8) |
2012 (values[1] << 21) |
2013 (values[2] << 16) |
2014 (values[3] << 0) |
2015 (values[4] << 5);
2016
2017 if (read)
2018 instr |= 0x00100000;
2019
2020 arm11_run_instr_data_prepare(arm11);
2021
2022 if (read)
2023 {
2024 uint32_t result;
2025 arm11_run_instr_data_from_core_via_r0(arm11, instr, &result);
2026
2027 LOG_INFO("MRC p%d, %d, R0, c%d, c%d, %d = 0x%08" PRIx32 " (%" PRId32 ")",
2028 (int)(values[0]),
2029 (int)(values[1]),
2030 (int)(values[2]),
2031 (int)(values[3]),
2032 (int)(values[4]), result, result);
2033 }
2034 else
2035 {
2036 arm11_run_instr_data_to_core_via_r0(arm11, instr, values[5]);
2037
2038 LOG_INFO("MRC p%d, %d, R0 (#0x%08" PRIx32 "), c%d, c%d, %d",
2039 (int)(values[0]), (int)(values[1]),
2040 values[5],
2041 (int)(values[2]), (int)(values[3]), (int)(values[4]));
2042 }
2043
2044 arm11_run_instr_data_finish(arm11);
2045
2046
2047 return ERROR_OK;
2048 }
2049
2050 int arm11_handle_mrc(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2051 {
2052 return arm11_handle_mrc_mcr(cmd_ctx, cmd, args, argc, true);
2053 }
2054
2055 int arm11_handle_mcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2056 {
2057 return arm11_handle_mrc_mcr(cmd_ctx, cmd, args, argc, false);
2058 }
2059
2060 int arm11_register_commands(struct command_context_s *cmd_ctx)
2061 {
2062 FNC_INFO;
2063
2064 command_t * top_cmd = NULL;
2065
2066 RC_TOP("arm11", "arm11 specific commands",
2067
2068 RC_TOP("memwrite", "Control memory write transfer mode",
2069
2070 RC_FINAL_BOOL("burst", "Enable/Disable non-standard but fast burst mode (default: enabled)",
2071 memwrite_burst)
2072
2073 RC_FINAL_BOOL("error_fatal", "Terminate program if transfer error was found (default: enabled)",
2074 memwrite_error_fatal)
2075 ) /* memwrite */
2076
2077 RC_FINAL_BOOL("no_increment", "Don't increment address on multi-read/-write (default: disabled)",
2078 memrw_no_increment)
2079
2080 RC_FINAL_BOOL("step_irq_enable", "Enable interrupts while stepping (default: disabled)",
2081 step_irq_enable)
2082 RC_FINAL_BOOL("hardware_step", "hardware single stepping. By default use simulate + breakpoint. This command is only here to check if simulate + breakpoint implementation is broken.",
2083 hardware_step)
2084
2085 RC_FINAL("vcr", "Control (Interrupt) Vector Catch Register",
2086 arm11_handle_vcr)
2087
2088 RC_FINAL("mrc", "Read Coprocessor register",
2089 arm11_handle_mrc)
2090
2091 RC_FINAL("mcr", "Write Coprocessor register",
2092 arm11_handle_mcr)
2093 ) /* arm11 */
2094
2095 return ERROR_OK;
2096 }
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