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Audit and eliminate redundant #include directives in arm target files.
[openocd.git] / src / target / arm11.c
1 /***************************************************************************
2 * Copyright (C) 2008 digenius technology GmbH. *
3 * *
4 * Copyright (C) 2008 Oyvind Harboe oyvind.harboe@zylin.com *
5 * *
6 * Copyright (C) 2008 Georg Acher <acher@in.tum.de> *
7 * *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
12 * *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
17 * *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
23
24 #ifdef HAVE_CONFIG_H
25 #include "config.h"
26 #endif
27
28 #include "arm11.h"
29
30
31 #if 0
32 #define _DEBUG_INSTRUCTION_EXECUTION_
33 #endif
34
35 #if 0
36 #define FNC_INFO LOG_DEBUG("-")
37 #else
38 #define FNC_INFO
39 #endif
40
41 #if 1
42 #define FNC_INFO_NOTIMPLEMENTED do { LOG_DEBUG("NOT IMPLEMENTED"); /*exit(-1);*/ } while (0)
43 #else
44 #define FNC_INFO_NOTIMPLEMENTED
45 #endif
46
47 static int arm11_on_enter_debug_state(arm11_common_t * arm11);
48
49 bool arm11_config_memwrite_burst = true;
50 bool arm11_config_memwrite_error_fatal = true;
51 u32 arm11_vcr = 0;
52 bool arm11_config_memrw_no_increment = false;
53 bool arm11_config_step_irq_enable = false;
54
55 #define ARM11_HANDLER(x) \
56 .x = arm11_##x
57
58 target_type_t arm11_target =
59 {
60 .name = "arm11",
61
62 ARM11_HANDLER(poll),
63 ARM11_HANDLER(arch_state),
64
65 ARM11_HANDLER(target_request_data),
66
67 ARM11_HANDLER(halt),
68 ARM11_HANDLER(resume),
69 ARM11_HANDLER(step),
70
71 ARM11_HANDLER(assert_reset),
72 ARM11_HANDLER(deassert_reset),
73 ARM11_HANDLER(soft_reset_halt),
74
75 ARM11_HANDLER(get_gdb_reg_list),
76
77 ARM11_HANDLER(read_memory),
78 ARM11_HANDLER(write_memory),
79
80 ARM11_HANDLER(bulk_write_memory),
81
82 ARM11_HANDLER(checksum_memory),
83
84 ARM11_HANDLER(add_breakpoint),
85 ARM11_HANDLER(remove_breakpoint),
86 ARM11_HANDLER(add_watchpoint),
87 ARM11_HANDLER(remove_watchpoint),
88
89 ARM11_HANDLER(run_algorithm),
90
91 ARM11_HANDLER(register_commands),
92 ARM11_HANDLER(target_create),
93 ARM11_HANDLER(init_target),
94 ARM11_HANDLER(examine),
95 ARM11_HANDLER(quit),
96 };
97
98 int arm11_regs_arch_type = -1;
99
100
101 enum arm11_regtype
102 {
103 ARM11_REGISTER_CORE,
104 ARM11_REGISTER_CPSR,
105
106 ARM11_REGISTER_FX,
107 ARM11_REGISTER_FPS,
108
109 ARM11_REGISTER_FIQ,
110 ARM11_REGISTER_SVC,
111 ARM11_REGISTER_ABT,
112 ARM11_REGISTER_IRQ,
113 ARM11_REGISTER_UND,
114 ARM11_REGISTER_MON,
115
116 ARM11_REGISTER_SPSR_FIQ,
117 ARM11_REGISTER_SPSR_SVC,
118 ARM11_REGISTER_SPSR_ABT,
119 ARM11_REGISTER_SPSR_IRQ,
120 ARM11_REGISTER_SPSR_UND,
121 ARM11_REGISTER_SPSR_MON,
122
123 /* debug regs */
124 ARM11_REGISTER_DSCR,
125 ARM11_REGISTER_WDTR,
126 ARM11_REGISTER_RDTR,
127 };
128
129
130 typedef struct arm11_reg_defs_s
131 {
132 char * name;
133 u32 num;
134 int gdb_num;
135 enum arm11_regtype type;
136 } arm11_reg_defs_t;
137
138 /* update arm11_regcache_ids when changing this */
139 static const arm11_reg_defs_t arm11_reg_defs[] =
140 {
141 {"r0", 0, 0, ARM11_REGISTER_CORE},
142 {"r1", 1, 1, ARM11_REGISTER_CORE},
143 {"r2", 2, 2, ARM11_REGISTER_CORE},
144 {"r3", 3, 3, ARM11_REGISTER_CORE},
145 {"r4", 4, 4, ARM11_REGISTER_CORE},
146 {"r5", 5, 5, ARM11_REGISTER_CORE},
147 {"r6", 6, 6, ARM11_REGISTER_CORE},
148 {"r7", 7, 7, ARM11_REGISTER_CORE},
149 {"r8", 8, 8, ARM11_REGISTER_CORE},
150 {"r9", 9, 9, ARM11_REGISTER_CORE},
151 {"r10", 10, 10, ARM11_REGISTER_CORE},
152 {"r11", 11, 11, ARM11_REGISTER_CORE},
153 {"r12", 12, 12, ARM11_REGISTER_CORE},
154 {"sp", 13, 13, ARM11_REGISTER_CORE},
155 {"lr", 14, 14, ARM11_REGISTER_CORE},
156 {"pc", 15, 15, ARM11_REGISTER_CORE},
157
158 #if ARM11_REGCACHE_FREGS
159 {"f0", 0, 16, ARM11_REGISTER_FX},
160 {"f1", 1, 17, ARM11_REGISTER_FX},
161 {"f2", 2, 18, ARM11_REGISTER_FX},
162 {"f3", 3, 19, ARM11_REGISTER_FX},
163 {"f4", 4, 20, ARM11_REGISTER_FX},
164 {"f5", 5, 21, ARM11_REGISTER_FX},
165 {"f6", 6, 22, ARM11_REGISTER_FX},
166 {"f7", 7, 23, ARM11_REGISTER_FX},
167 {"fps", 0, 24, ARM11_REGISTER_FPS},
168 #endif
169
170 {"cpsr", 0, 25, ARM11_REGISTER_CPSR},
171
172 #if ARM11_REGCACHE_MODEREGS
173 {"r8_fiq", 8, -1, ARM11_REGISTER_FIQ},
174 {"r9_fiq", 9, -1, ARM11_REGISTER_FIQ},
175 {"r10_fiq", 10, -1, ARM11_REGISTER_FIQ},
176 {"r11_fiq", 11, -1, ARM11_REGISTER_FIQ},
177 {"r12_fiq", 12, -1, ARM11_REGISTER_FIQ},
178 {"r13_fiq", 13, -1, ARM11_REGISTER_FIQ},
179 {"r14_fiq", 14, -1, ARM11_REGISTER_FIQ},
180 {"spsr_fiq", 0, -1, ARM11_REGISTER_SPSR_FIQ},
181
182 {"r13_svc", 13, -1, ARM11_REGISTER_SVC},
183 {"r14_svc", 14, -1, ARM11_REGISTER_SVC},
184 {"spsr_svc", 0, -1, ARM11_REGISTER_SPSR_SVC},
185
186 {"r13_abt", 13, -1, ARM11_REGISTER_ABT},
187 {"r14_abt", 14, -1, ARM11_REGISTER_ABT},
188 {"spsr_abt", 0, -1, ARM11_REGISTER_SPSR_ABT},
189
190 {"r13_irq", 13, -1, ARM11_REGISTER_IRQ},
191 {"r14_irq", 14, -1, ARM11_REGISTER_IRQ},
192 {"spsr_irq", 0, -1, ARM11_REGISTER_SPSR_IRQ},
193
194 {"r13_und", 13, -1, ARM11_REGISTER_UND},
195 {"r14_und", 14, -1, ARM11_REGISTER_UND},
196 {"spsr_und", 0, -1, ARM11_REGISTER_SPSR_UND},
197
198 /* ARM1176 only */
199 {"r13_mon", 13, -1, ARM11_REGISTER_MON},
200 {"r14_mon", 14, -1, ARM11_REGISTER_MON},
201 {"spsr_mon", 0, -1, ARM11_REGISTER_SPSR_MON},
202 #endif
203
204 /* Debug Registers */
205 {"dscr", 0, -1, ARM11_REGISTER_DSCR},
206 {"wdtr", 0, -1, ARM11_REGISTER_WDTR},
207 {"rdtr", 0, -1, ARM11_REGISTER_RDTR},
208 };
209
210 enum arm11_regcache_ids
211 {
212 ARM11_RC_R0,
213 ARM11_RC_RX = ARM11_RC_R0,
214
215 ARM11_RC_R1,
216 ARM11_RC_R2,
217 ARM11_RC_R3,
218 ARM11_RC_R4,
219 ARM11_RC_R5,
220 ARM11_RC_R6,
221 ARM11_RC_R7,
222 ARM11_RC_R8,
223 ARM11_RC_R9,
224 ARM11_RC_R10,
225 ARM11_RC_R11,
226 ARM11_RC_R12,
227 ARM11_RC_R13,
228 ARM11_RC_SP = ARM11_RC_R13,
229 ARM11_RC_R14,
230 ARM11_RC_LR = ARM11_RC_R14,
231 ARM11_RC_R15,
232 ARM11_RC_PC = ARM11_RC_R15,
233
234 #if ARM11_REGCACHE_FREGS
235 ARM11_RC_F0,
236 ARM11_RC_FX = ARM11_RC_F0,
237 ARM11_RC_F1,
238 ARM11_RC_F2,
239 ARM11_RC_F3,
240 ARM11_RC_F4,
241 ARM11_RC_F5,
242 ARM11_RC_F6,
243 ARM11_RC_F7,
244 ARM11_RC_FPS,
245 #endif
246
247 ARM11_RC_CPSR,
248
249 #if ARM11_REGCACHE_MODEREGS
250 ARM11_RC_R8_FIQ,
251 ARM11_RC_R9_FIQ,
252 ARM11_RC_R10_FIQ,
253 ARM11_RC_R11_FIQ,
254 ARM11_RC_R12_FIQ,
255 ARM11_RC_R13_FIQ,
256 ARM11_RC_R14_FIQ,
257 ARM11_RC_SPSR_FIQ,
258
259 ARM11_RC_R13_SVC,
260 ARM11_RC_R14_SVC,
261 ARM11_RC_SPSR_SVC,
262
263 ARM11_RC_R13_ABT,
264 ARM11_RC_R14_ABT,
265 ARM11_RC_SPSR_ABT,
266
267 ARM11_RC_R13_IRQ,
268 ARM11_RC_R14_IRQ,
269 ARM11_RC_SPSR_IRQ,
270
271 ARM11_RC_R13_UND,
272 ARM11_RC_R14_UND,
273 ARM11_RC_SPSR_UND,
274
275 ARM11_RC_R13_MON,
276 ARM11_RC_R14_MON,
277 ARM11_RC_SPSR_MON,
278 #endif
279
280 ARM11_RC_DSCR,
281 ARM11_RC_WDTR,
282 ARM11_RC_RDTR,
283
284 ARM11_RC_MAX,
285 };
286
287 #define ARM11_GDB_REGISTER_COUNT 26
288
289 u8 arm11_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
290
291 reg_t arm11_gdb_dummy_fp_reg =
292 {
293 "GDB dummy floating-point register", arm11_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0
294 };
295
296 u8 arm11_gdb_dummy_fps_value[] = {0, 0, 0, 0};
297
298 reg_t arm11_gdb_dummy_fps_reg =
299 {
300 "GDB dummy floating-point status register", arm11_gdb_dummy_fps_value, 0, 1, 32, NULL, 0, NULL, 0
301 };
302
303
304
305 /** Check and if necessary take control of the system
306 *
307 * \param arm11 Target state variable.
308 * \param dscr If the current DSCR content is
309 * available a pointer to a word holding the
310 * DSCR can be passed. Otherwise use NULL.
311 */
312 int arm11_check_init(arm11_common_t * arm11, u32 * dscr)
313 {
314 FNC_INFO;
315
316 u32 dscr_local_tmp_copy;
317
318 if (!dscr)
319 {
320 dscr = &dscr_local_tmp_copy;
321
322 CHECK_RETVAL(arm11_read_DSCR(arm11, dscr));
323 }
324
325 if (!(*dscr & ARM11_DSCR_MODE_SELECT))
326 {
327 LOG_DEBUG("Bringing target into debug mode");
328
329 *dscr |= ARM11_DSCR_MODE_SELECT; /* Halt debug-mode */
330 arm11_write_DSCR(arm11, *dscr);
331
332 /* add further reset initialization here */
333
334 arm11->simulate_reset_on_next_halt = true;
335
336 if (*dscr & ARM11_DSCR_CORE_HALTED)
337 {
338 /** \todo TODO: this needs further scrutiny because
339 * arm11_on_enter_debug_state() never gets properly called
340 */
341
342 arm11->target->state = TARGET_HALTED;
343 arm11->target->debug_reason = arm11_get_DSCR_debug_reason(*dscr);
344 }
345 else
346 {
347 arm11->target->state = TARGET_RUNNING;
348 arm11->target->debug_reason = DBG_REASON_NOTHALTED;
349 }
350
351 arm11_sc7_clear_vbw(arm11);
352 }
353
354 return ERROR_OK;
355 }
356
357
358
359 #define R(x) \
360 (arm11->reg_values[ARM11_RC_##x])
361
362 /** Save processor state.
363 *
364 * This is called when the HALT instruction has succeeded
365 * or on other occasions that stop the processor.
366 *
367 */
368 static int arm11_on_enter_debug_state(arm11_common_t * arm11)
369 {
370 FNC_INFO;
371
372 for (size_t i = 0; i < asizeof(arm11->reg_values); i++)
373 {
374 arm11->reg_list[i].valid = 1;
375 arm11->reg_list[i].dirty = 0;
376 }
377
378 /* Save DSCR */
379 CHECK_RETVAL(arm11_read_DSCR(arm11, &R(DSCR)));
380
381 /* Save wDTR */
382
383 if (R(DSCR) & ARM11_DSCR_WDTR_FULL)
384 {
385 arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
386
387 arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
388
389 scan_field_t chain5_fields[3];
390
391 arm11_setup_field(arm11, 32, NULL, &R(WDTR), chain5_fields + 0);
392 arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 1);
393 arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 2);
394
395 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
396 }
397 else
398 {
399 arm11->reg_list[ARM11_RC_WDTR].valid = 0;
400 }
401
402
403 /* DSCR: set ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE */
404 /* ARM1176 spec says this is needed only for wDTR/rDTR's "ITR mode", but not to issue ITRs
405 ARM1136 seems to require this to issue ITR's as well */
406
407 u32 new_dscr = R(DSCR) | ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE;
408
409 /* this executes JTAG queue: */
410
411 arm11_write_DSCR(arm11, new_dscr);
412
413
414 /* From the spec:
415 Before executing any instruction in debug state you have to drain the write buffer.
416 This ensures that no imprecise Data Aborts can return at a later point:*/
417
418 /** \todo TODO: Test drain write buffer. */
419
420 #if 0
421 while (1)
422 {
423 /* MRC p14,0,R0,c5,c10,0 */
424 // arm11_run_instr_no_data1(arm11, /*0xee150e1a*/0xe320f000);
425
426 /* mcr 15, 0, r0, cr7, cr10, {4} */
427 arm11_run_instr_no_data1(arm11, 0xee070f9a);
428
429 u32 dscr = arm11_read_DSCR(arm11);
430
431 LOG_DEBUG("DRAIN, DSCR %08x", dscr);
432
433 if (dscr & ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT)
434 {
435 arm11_run_instr_no_data1(arm11, 0xe320f000);
436
437 dscr = arm11_read_DSCR(arm11);
438
439 LOG_DEBUG("DRAIN, DSCR %08x (DONE)", dscr);
440
441 break;
442 }
443 }
444 #endif
445
446 arm11_run_instr_data_prepare(arm11);
447
448 /* save r0 - r14 */
449
450 /** \todo TODO: handle other mode registers */
451
452 for (size_t i = 0; i < 15; i++)
453 {
454 /* MCR p14,0,R?,c0,c5,0 */
455 arm11_run_instr_data_from_core(arm11, 0xEE000E15 | (i << 12), &R(RX + i), 1);
456 }
457
458 /* save rDTR */
459
460 /* check rDTRfull in DSCR */
461
462 if (R(DSCR) & ARM11_DSCR_RDTR_FULL)
463 {
464 /* MRC p14,0,R0,c0,c5,0 (move rDTR -> r0 (-> wDTR -> local var)) */
465 arm11_run_instr_data_from_core_via_r0(arm11, 0xEE100E15, &R(RDTR));
466 }
467 else
468 {
469 arm11->reg_list[ARM11_RC_RDTR].valid = 0;
470 }
471
472 /* save CPSR */
473
474 /* MRS r0,CPSR (move CPSR -> r0 (-> wDTR -> local var)) */
475 arm11_run_instr_data_from_core_via_r0(arm11, 0xE10F0000, &R(CPSR));
476
477 /* save PC */
478
479 /* MOV R0,PC (move PC -> r0 (-> wDTR -> local var)) */
480 arm11_run_instr_data_from_core_via_r0(arm11, 0xE1A0000F, &R(PC));
481
482 /* adjust PC depending on ARM state */
483
484 if (R(CPSR) & ARM11_CPSR_J) /* Java state */
485 {
486 arm11->reg_values[ARM11_RC_PC] -= 0;
487 }
488 else if (R(CPSR) & ARM11_CPSR_T) /* Thumb state */
489 {
490 arm11->reg_values[ARM11_RC_PC] -= 4;
491 }
492 else /* ARM state */
493 {
494 arm11->reg_values[ARM11_RC_PC] -= 8;
495 }
496
497 if (arm11->simulate_reset_on_next_halt)
498 {
499 arm11->simulate_reset_on_next_halt = false;
500
501 LOG_DEBUG("Reset c1 Control Register");
502
503 /* Write 0 (reset value) to Control register 0 to disable MMU/Cache etc. */
504
505 /* MCR p15,0,R0,c1,c0,0 */
506 arm11_run_instr_data_to_core_via_r0(arm11, 0xee010f10, 0);
507
508 }
509
510 arm11_run_instr_data_finish(arm11);
511
512 arm11_dump_reg_changes(arm11);
513
514 return ERROR_OK;
515 }
516
517 void arm11_dump_reg_changes(arm11_common_t * arm11)
518 {
519
520 if (!(debug_level >= LOG_LVL_DEBUG))
521 {
522 return;
523 }
524
525 for (size_t i = 0; i < ARM11_REGCACHE_COUNT; i++)
526 {
527 if (!arm11->reg_list[i].valid)
528 {
529 if (arm11->reg_history[i].valid)
530 LOG_DEBUG("%8s INVALID (%08x)", arm11_reg_defs[i].name, arm11->reg_history[i].value);
531 }
532 else
533 {
534 if (arm11->reg_history[i].valid)
535 {
536 if (arm11->reg_history[i].value != arm11->reg_values[i])
537 LOG_DEBUG("%8s %08x (%08x)", arm11_reg_defs[i].name, arm11->reg_values[i], arm11->reg_history[i].value);
538 }
539 else
540 {
541 LOG_DEBUG("%8s %08x (INVALID)", arm11_reg_defs[i].name, arm11->reg_values[i]);
542 }
543 }
544 }
545 }
546
547 /** Restore processor state
548 *
549 * This is called in preparation for the RESTART function.
550 *
551 */
552 int arm11_leave_debug_state(arm11_common_t * arm11)
553 {
554 FNC_INFO;
555
556 arm11_run_instr_data_prepare(arm11);
557
558 /** \todo TODO: handle other mode registers */
559
560 /* restore R1 - R14 */
561
562 for (size_t i = 1; i < 15; i++)
563 {
564 if (!arm11->reg_list[ARM11_RC_RX + i].dirty)
565 continue;
566
567 /* MRC p14,0,r?,c0,c5,0 */
568 arm11_run_instr_data_to_core1(arm11, 0xee100e15 | (i << 12), R(RX + i));
569
570 // LOG_DEBUG("RESTORE R" ZU " %08x", i, R(RX + i));
571 }
572
573 arm11_run_instr_data_finish(arm11);
574
575 /* spec says clear wDTR and rDTR; we assume they are clear as
576 otherwise our programming would be sloppy */
577 {
578 u32 DSCR;
579
580 CHECK_RETVAL(arm11_read_DSCR(arm11, &DSCR));
581
582 if (DSCR & (ARM11_DSCR_RDTR_FULL | ARM11_DSCR_WDTR_FULL))
583 {
584 LOG_ERROR("wDTR/rDTR inconsistent (DSCR %08x)", DSCR);
585 }
586 }
587
588 arm11_run_instr_data_prepare(arm11);
589
590 /* restore original wDTR */
591
592 if ((R(DSCR) & ARM11_DSCR_WDTR_FULL) || arm11->reg_list[ARM11_RC_WDTR].dirty)
593 {
594 /* MCR p14,0,R0,c0,c5,0 */
595 arm11_run_instr_data_to_core_via_r0(arm11, 0xee000e15, R(WDTR));
596 }
597
598 /* restore CPSR */
599
600 /* MSR CPSR,R0*/
601 arm11_run_instr_data_to_core_via_r0(arm11, 0xe129f000, R(CPSR));
602
603 /* restore PC */
604
605 /* MOV PC,R0 */
606 arm11_run_instr_data_to_core_via_r0(arm11, 0xe1a0f000, R(PC));
607
608 /* restore R0 */
609
610 /* MRC p14,0,r0,c0,c5,0 */
611 arm11_run_instr_data_to_core1(arm11, 0xee100e15, R(R0));
612
613 arm11_run_instr_data_finish(arm11);
614
615 /* restore DSCR */
616
617 arm11_write_DSCR(arm11, R(DSCR));
618
619 /* restore rDTR */
620
621 if (R(DSCR) & ARM11_DSCR_RDTR_FULL || arm11->reg_list[ARM11_RC_RDTR].dirty)
622 {
623 arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
624
625 arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT);
626
627 scan_field_t chain5_fields[3];
628
629 u8 Ready = 0; /* ignored */
630 u8 Valid = 0; /* ignored */
631
632 arm11_setup_field(arm11, 32, &R(RDTR), NULL, chain5_fields + 0);
633 arm11_setup_field(arm11, 1, &Ready, NULL, chain5_fields + 1);
634 arm11_setup_field(arm11, 1, &Valid, NULL, chain5_fields + 2);
635
636 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
637 }
638
639 arm11_record_register_history(arm11);
640
641 return ERROR_OK;
642 }
643
644 void arm11_record_register_history(arm11_common_t * arm11)
645 {
646 for (size_t i = 0; i < ARM11_REGCACHE_COUNT; i++)
647 {
648 arm11->reg_history[i].value = arm11->reg_values[i];
649 arm11->reg_history[i].valid = arm11->reg_list[i].valid;
650
651 arm11->reg_list[i].valid = 0;
652 arm11->reg_list[i].dirty = 0;
653 }
654 }
655
656
657 /* poll current target status */
658 int arm11_poll(struct target_s *target)
659 {
660 FNC_INFO;
661
662 arm11_common_t * arm11 = target->arch_info;
663
664 if (arm11->trst_active)
665 return ERROR_OK;
666
667 u32 dscr;
668
669 CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
670
671 LOG_DEBUG("DSCR %08x", dscr);
672
673 CHECK_RETVAL(arm11_check_init(arm11, &dscr));
674
675 if (dscr & ARM11_DSCR_CORE_HALTED)
676 {
677 if (target->state != TARGET_HALTED)
678 {
679 enum target_state old_state = target->state;
680
681 LOG_DEBUG("enter TARGET_HALTED");
682 target->state = TARGET_HALTED;
683 target->debug_reason = arm11_get_DSCR_debug_reason(dscr);
684 arm11_on_enter_debug_state(arm11);
685
686 target_call_event_callbacks(target,
687 old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED);
688 }
689 }
690 else
691 {
692 if (target->state != TARGET_RUNNING && target->state != TARGET_DEBUG_RUNNING)
693 {
694 LOG_DEBUG("enter TARGET_RUNNING");
695 target->state = TARGET_RUNNING;
696 target->debug_reason = DBG_REASON_NOTHALTED;
697 }
698 }
699
700 return ERROR_OK;
701 }
702 /* architecture specific status reply */
703 int arm11_arch_state(struct target_s *target)
704 {
705 arm11_common_t * arm11 = target->arch_info;
706
707 LOG_USER("target halted due to %s\ncpsr: 0x%8.8x pc: 0x%8.8x",
708 Jim_Nvp_value2name_simple( nvp_target_debug_reason, target->debug_reason )->name,
709 R(CPSR),
710 R(PC));
711
712 return ERROR_OK;
713 }
714
715 /* target request support */
716 int arm11_target_request_data(struct target_s *target, u32 size, u8 *buffer)
717 {
718 FNC_INFO_NOTIMPLEMENTED;
719
720 return ERROR_OK;
721 }
722
723 /* target execution control */
724 int arm11_halt(struct target_s *target)
725 {
726 FNC_INFO;
727
728 arm11_common_t * arm11 = target->arch_info;
729
730 LOG_DEBUG("target->state: %s",
731 Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name );
732
733 if (target->state == TARGET_UNKNOWN)
734 {
735 arm11->simulate_reset_on_next_halt = true;
736 }
737
738 if (target->state == TARGET_HALTED)
739 {
740 LOG_DEBUG("target was already halted");
741 return ERROR_OK;
742 }
743
744 if (arm11->trst_active)
745 {
746 arm11->halt_requested = true;
747 return ERROR_OK;
748 }
749
750 arm11_add_IR(arm11, ARM11_HALT, TAP_IDLE);
751
752 CHECK_RETVAL(jtag_execute_queue());
753
754 u32 dscr;
755
756 while (1)
757 {
758 CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
759
760 if (dscr & ARM11_DSCR_CORE_HALTED)
761 break;
762 }
763
764 arm11_on_enter_debug_state(arm11);
765
766 enum target_state old_state = target->state;
767
768 target->state = TARGET_HALTED;
769 target->debug_reason = arm11_get_DSCR_debug_reason(dscr);
770
771 CHECK_RETVAL(
772 target_call_event_callbacks(target,
773 old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED));
774
775 return ERROR_OK;
776 }
777
778 int arm11_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution)
779 {
780 FNC_INFO;
781
782 // LOG_DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d",
783 // current, address, handle_breakpoints, debug_execution);
784
785 arm11_common_t * arm11 = target->arch_info;
786
787 LOG_DEBUG("target->state: %s",
788 Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name );
789
790
791 if (target->state != TARGET_HALTED)
792 {
793 LOG_ERROR("Target not halted");
794 return ERROR_TARGET_NOT_HALTED;
795 }
796
797 if (!current)
798 R(PC) = address;
799
800 LOG_DEBUG("RESUME PC %08x%s", R(PC), !current ? "!" : "");
801
802 /* clear breakpoints/watchpoints and VCR*/
803 arm11_sc7_clear_vbw(arm11);
804
805 /* Set up breakpoints */
806 if (!debug_execution)
807 {
808 /* check if one matches PC and step over it if necessary */
809
810 breakpoint_t * bp;
811
812 for (bp = target->breakpoints; bp; bp = bp->next)
813 {
814 if (bp->address == R(PC))
815 {
816 LOG_DEBUG("must step over %08x", bp->address);
817 arm11_step(target, 1, 0, 0);
818 break;
819 }
820 }
821
822 /* set all breakpoints */
823
824 size_t brp_num = 0;
825
826 for (bp = target->breakpoints; bp; bp = bp->next)
827 {
828 arm11_sc7_action_t brp[2];
829
830 brp[0].write = 1;
831 brp[0].address = ARM11_SC7_BVR0 + brp_num;
832 brp[0].value = bp->address;
833 brp[1].write = 1;
834 brp[1].address = ARM11_SC7_BCR0 + brp_num;
835 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
836
837 arm11_sc7_run(arm11, brp, asizeof(brp));
838
839 LOG_DEBUG("Add BP " ZU " at %08x", brp_num, bp->address);
840
841 brp_num++;
842 }
843
844 arm11_sc7_set_vcr(arm11, arm11_vcr);
845 }
846
847 arm11_leave_debug_state(arm11);
848
849 arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
850
851 CHECK_RETVAL(jtag_execute_queue());
852
853 while (1)
854 {
855 u32 dscr;
856
857 CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
858
859 LOG_DEBUG("DSCR %08x", dscr);
860
861 if (dscr & ARM11_DSCR_CORE_RESTARTED)
862 break;
863 }
864
865 if (!debug_execution)
866 {
867 target->state = TARGET_RUNNING;
868 target->debug_reason = DBG_REASON_NOTHALTED;
869
870 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
871 }
872 else
873 {
874 target->state = TARGET_DEBUG_RUNNING;
875 target->debug_reason = DBG_REASON_NOTHALTED;
876
877 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
878 }
879
880 return ERROR_OK;
881 }
882
883 int arm11_step(struct target_s *target, int current, u32 address, int handle_breakpoints)
884 {
885 FNC_INFO;
886
887 LOG_DEBUG("target->state: %s",
888 Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name );
889
890 if (target->state != TARGET_HALTED)
891 {
892 LOG_WARNING("target was not halted");
893 return ERROR_TARGET_NOT_HALTED;
894 }
895
896 arm11_common_t * arm11 = target->arch_info;
897
898 if (!current)
899 R(PC) = address;
900
901 LOG_DEBUG("STEP PC %08x%s", R(PC), !current ? "!" : "");
902
903 /** \todo TODO: Thumb not supported here */
904
905 u32 next_instruction;
906
907 CHECK_RETVAL(arm11_read_memory_word(arm11, R(PC), &next_instruction));
908
909 /* skip over BKPT */
910 if ((next_instruction & 0xFFF00070) == 0xe1200070)
911 {
912 R(PC) += 4;
913 arm11->reg_list[ARM11_RC_PC].valid = 1;
914 arm11->reg_list[ARM11_RC_PC].dirty = 0;
915 LOG_DEBUG("Skipping BKPT");
916 }
917 /* skip over Wait for interrupt / Standby */
918 /* mcr 15, 0, r?, cr7, cr0, {4} */
919 else if ((next_instruction & 0xFFFF0FFF) == 0xee070f90)
920 {
921 R(PC) += 4;
922 arm11->reg_list[ARM11_RC_PC].valid = 1;
923 arm11->reg_list[ARM11_RC_PC].dirty = 0;
924 LOG_DEBUG("Skipping WFI");
925 }
926 /* ignore B to self */
927 else if ((next_instruction & 0xFEFFFFFF) == 0xeafffffe)
928 {
929 LOG_DEBUG("Not stepping jump to self");
930 }
931 else
932 {
933 /** \todo TODO: check if break-/watchpoints make any sense at all in combination
934 * with this. */
935
936 /** \todo TODO: check if disabling IRQs might be a good idea here. Alternatively
937 * the VCR might be something worth looking into. */
938
939
940 /* Set up breakpoint for stepping */
941
942 arm11_sc7_action_t brp[2];
943
944 brp[0].write = 1;
945 brp[0].address = ARM11_SC7_BVR0;
946 brp[0].value = R(PC);
947 brp[1].write = 1;
948 brp[1].address = ARM11_SC7_BCR0;
949 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (2 << 21);
950
951 CHECK_RETVAL(arm11_sc7_run(arm11, brp, asizeof(brp)));
952
953 /* resume */
954
955
956 if (arm11_config_step_irq_enable)
957 R(DSCR) &= ~ARM11_DSCR_INTERRUPTS_DISABLE; /* should be redundant */
958 else
959 R(DSCR) |= ARM11_DSCR_INTERRUPTS_DISABLE;
960
961
962 CHECK_RETVAL(arm11_leave_debug_state(arm11));
963
964 arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
965
966 CHECK_RETVAL(jtag_execute_queue());
967
968 /** \todo TODO: add a timeout */
969
970 /* wait for halt */
971
972 while (1)
973 {
974 u32 dscr;
975
976 CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
977
978 LOG_DEBUG("DSCR %08x", dscr);
979
980 if ((dscr & (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED)) ==
981 (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED))
982 break;
983 }
984
985 /* clear breakpoint */
986 arm11_sc7_clear_vbw(arm11);
987
988 /* save state */
989 CHECK_RETVAL(arm11_on_enter_debug_state(arm11));
990
991 /* restore default state */
992 R(DSCR) &= ~ARM11_DSCR_INTERRUPTS_DISABLE;
993
994 }
995
996 // target->state = TARGET_HALTED;
997 target->debug_reason = DBG_REASON_SINGLESTEP;
998
999 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_HALTED));
1000
1001 return ERROR_OK;
1002 }
1003
1004 /* target reset control */
1005 int arm11_assert_reset(struct target_s *target)
1006 {
1007 FNC_INFO;
1008
1009 #if 0
1010 /* assert reset lines */
1011 /* resets only the DBGTAP, not the ARM */
1012
1013 jtag_add_reset(1, 0);
1014 jtag_add_sleep(5000);
1015
1016 arm11_common_t * arm11 = target->arch_info;
1017 arm11->trst_active = true;
1018 #endif
1019
1020 if (target->reset_halt)
1021 {
1022 CHECK_RETVAL(target_halt(target));
1023 }
1024
1025 return ERROR_OK;
1026 }
1027
1028 int arm11_deassert_reset(struct target_s *target)
1029 {
1030 FNC_INFO;
1031
1032 #if 0
1033 LOG_DEBUG("target->state: %s",
1034 Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name );
1035
1036
1037 /* deassert reset lines */
1038 jtag_add_reset(0, 0);
1039
1040 arm11_common_t * arm11 = target->arch_info;
1041 arm11->trst_active = false;
1042
1043 if (arm11->halt_requested)
1044 return arm11_halt(target);
1045 #endif
1046
1047 return ERROR_OK;
1048 }
1049
1050 int arm11_soft_reset_halt(struct target_s *target)
1051 {
1052 FNC_INFO_NOTIMPLEMENTED;
1053
1054 return ERROR_OK;
1055 }
1056
1057 /* target register access for gdb */
1058 int arm11_get_gdb_reg_list(struct target_s *target, struct reg_s **reg_list[], int *reg_list_size)
1059 {
1060 FNC_INFO;
1061
1062 arm11_common_t * arm11 = target->arch_info;
1063
1064 *reg_list_size = ARM11_GDB_REGISTER_COUNT;
1065 *reg_list = malloc(sizeof(reg_t*) * ARM11_GDB_REGISTER_COUNT);
1066
1067 for (size_t i = 16; i < 24; i++)
1068 {
1069 (*reg_list)[i] = &arm11_gdb_dummy_fp_reg;
1070 }
1071
1072 (*reg_list)[24] = &arm11_gdb_dummy_fps_reg;
1073
1074 for (size_t i = 0; i < ARM11_REGCACHE_COUNT; i++)
1075 {
1076 if (arm11_reg_defs[i].gdb_num == -1)
1077 continue;
1078
1079 (*reg_list)[arm11_reg_defs[i].gdb_num] = arm11->reg_list + i;
1080 }
1081
1082 return ERROR_OK;
1083 }
1084
1085 /* target memory access
1086 * size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
1087 * count: number of items of <size>
1088 */
1089 int arm11_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1090 {
1091 /** \todo TODO: check if buffer cast to u32* and u16* might cause alignment problems */
1092
1093 FNC_INFO;
1094
1095 if (target->state != TARGET_HALTED)
1096 {
1097 LOG_WARNING("target was not halted");
1098 return ERROR_TARGET_NOT_HALTED;
1099 }
1100
1101 LOG_DEBUG("ADDR %08x SIZE %08x COUNT %08x", address, size, count);
1102
1103 arm11_common_t * arm11 = target->arch_info;
1104
1105 arm11_run_instr_data_prepare(arm11);
1106
1107 /* MRC p14,0,r0,c0,c5,0 */
1108 arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
1109
1110 switch (size)
1111 {
1112 case 1:
1113 /** \todo TODO: check if dirty is the right choice to force a rewrite on arm11_resume() */
1114 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1115
1116 for (size_t i = 0; i < count; i++)
1117 {
1118 /* ldrb r1, [r0], #1 */
1119 /* ldrb r1, [r0] */
1120 arm11_run_instr_no_data1(arm11,
1121 !arm11_config_memrw_no_increment ? 0xe4d01001 : 0xe5d01000);
1122
1123 u32 res;
1124 /* MCR p14,0,R1,c0,c5,0 */
1125 arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
1126
1127 *buffer++ = res;
1128 }
1129
1130 break;
1131
1132 case 2:
1133 {
1134 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1135
1136 for (size_t i = 0; i < count; i++)
1137 {
1138 /* ldrh r1, [r0], #2 */
1139 arm11_run_instr_no_data1(arm11,
1140 !arm11_config_memrw_no_increment ? 0xe0d010b2 : 0xe1d010b0);
1141
1142 u32 res;
1143
1144 /* MCR p14,0,R1,c0,c5,0 */
1145 arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
1146
1147 u16 svalue = res;
1148 memcpy(buffer + count * sizeof(u16), &svalue, sizeof(u16));
1149 }
1150
1151 break;
1152 }
1153
1154 case 4:
1155 {
1156 u32 instr = !arm11_config_memrw_no_increment ? 0xecb05e01 : 0xed905e00;
1157 /** \todo TODO: buffer cast to u32* causes alignment warnings */
1158 u32 *words = (u32 *)buffer;
1159
1160 /* LDC p14,c5,[R0],#4 */
1161 /* LDC p14,c5,[R0] */
1162 arm11_run_instr_data_from_core(arm11, instr, words, count);
1163 break;
1164 }
1165 }
1166
1167 arm11_run_instr_data_finish(arm11);
1168
1169 return ERROR_OK;
1170 }
1171
1172 int arm11_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1173 {
1174 FNC_INFO;
1175
1176 if (target->state != TARGET_HALTED)
1177 {
1178 LOG_WARNING("target was not halted");
1179 return ERROR_TARGET_NOT_HALTED;
1180 }
1181
1182 LOG_DEBUG("ADDR %08x SIZE %08x COUNT %08x", address, size, count);
1183
1184 arm11_common_t * arm11 = target->arch_info;
1185
1186 arm11_run_instr_data_prepare(arm11);
1187
1188 /* MRC p14,0,r0,c0,c5,0 */
1189 arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
1190
1191 switch (size)
1192 {
1193 case 1:
1194 {
1195 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1196
1197 for (size_t i = 0; i < count; i++)
1198 {
1199 /* MRC p14,0,r1,c0,c5,0 */
1200 arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buffer++);
1201
1202 /* strb r1, [r0], #1 */
1203 /* strb r1, [r0] */
1204 arm11_run_instr_no_data1(arm11,
1205 !arm11_config_memrw_no_increment ? 0xe4c01001 : 0xe5c01000);
1206 }
1207
1208 break;
1209 }
1210
1211 case 2:
1212 {
1213 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1214
1215 for (size_t i = 0; i < count; i++)
1216 {
1217 u16 value;
1218 memcpy(&value, buffer + count * sizeof(u16), sizeof(u16));
1219
1220 /* MRC p14,0,r1,c0,c5,0 */
1221 arm11_run_instr_data_to_core1(arm11, 0xee101e15, value);
1222
1223 /* strh r1, [r0], #2 */
1224 /* strh r1, [r0] */
1225 arm11_run_instr_no_data1(arm11,
1226 !arm11_config_memrw_no_increment ? 0xe0c010b2 : 0xe1c010b0);
1227 }
1228
1229 break;
1230 }
1231
1232 case 4: {
1233 u32 instr = !arm11_config_memrw_no_increment ? 0xeca05e01 : 0xed805e00;
1234
1235 /** \todo TODO: buffer cast to u32* causes alignment warnings */
1236 u32 *words = (u32*)buffer;
1237
1238 if (!arm11_config_memwrite_burst)
1239 {
1240 /* STC p14,c5,[R0],#4 */
1241 /* STC p14,c5,[R0]*/
1242 arm11_run_instr_data_to_core(arm11, instr, words, count);
1243 }
1244 else
1245 {
1246 /* STC p14,c5,[R0],#4 */
1247 /* STC p14,c5,[R0]*/
1248 arm11_run_instr_data_to_core_noack(arm11, instr, words, count);
1249 }
1250
1251 break;
1252 }
1253 }
1254
1255 #if 1
1256 /* r0 verification */
1257 if (!arm11_config_memrw_no_increment)
1258 {
1259 u32 r0;
1260
1261 /* MCR p14,0,R0,c0,c5,0 */
1262 arm11_run_instr_data_from_core(arm11, 0xEE000E15, &r0, 1);
1263
1264 if (address + size * count != r0)
1265 {
1266 LOG_ERROR("Data transfer failed. (%d)", (r0 - address) - size * count);
1267
1268 if (arm11_config_memwrite_burst)
1269 LOG_ERROR("use 'arm11 memwrite burst disable' to disable fast burst mode");
1270
1271 if (arm11_config_memwrite_error_fatal)
1272 return ERROR_FAIL;
1273 }
1274 }
1275 #endif
1276
1277 arm11_run_instr_data_finish(arm11);
1278
1279 return ERROR_OK;
1280 }
1281
1282
1283 /* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
1284 int arm11_bulk_write_memory(struct target_s *target, u32 address, u32 count, u8 *buffer)
1285 {
1286 FNC_INFO;
1287
1288 if (target->state != TARGET_HALTED)
1289 {
1290 LOG_WARNING("target was not halted");
1291 return ERROR_TARGET_NOT_HALTED;
1292 }
1293
1294 return arm11_write_memory(target, address, 4, count, buffer);
1295 }
1296
1297 /* here we have nothing target specific to contribute, so we fail and then the
1298 * fallback code will read data from the target and calculate the CRC on the
1299 * host.
1300 */
1301 int arm11_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum)
1302 {
1303 return ERROR_FAIL;
1304 }
1305
1306 /* target break-/watchpoint control
1307 * rw: 0 = write, 1 = read, 2 = access
1308 */
1309 int arm11_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
1310 {
1311 FNC_INFO;
1312
1313 arm11_common_t * arm11 = target->arch_info;
1314
1315 #if 0
1316 if (breakpoint->type == BKPT_SOFT)
1317 {
1318 LOG_INFO("sw breakpoint requested, but software breakpoints not enabled");
1319 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1320 }
1321 #endif
1322
1323 if (!arm11->free_brps)
1324 {
1325 LOG_DEBUG("no breakpoint unit available for hardware breakpoint");
1326 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1327 }
1328
1329 if (breakpoint->length != 4)
1330 {
1331 LOG_DEBUG("only breakpoints of four bytes length supported");
1332 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1333 }
1334
1335 arm11->free_brps--;
1336
1337 return ERROR_OK;
1338 }
1339
1340 int arm11_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
1341 {
1342 FNC_INFO;
1343
1344 arm11_common_t * arm11 = target->arch_info;
1345
1346 arm11->free_brps++;
1347
1348 return ERROR_OK;
1349 }
1350
1351 int arm11_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
1352 {
1353 FNC_INFO_NOTIMPLEMENTED;
1354
1355 return ERROR_OK;
1356 }
1357
1358 int arm11_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
1359 {
1360 FNC_INFO_NOTIMPLEMENTED;
1361
1362 return ERROR_OK;
1363 }
1364
1365 // HACKHACKHACK - FIXME mode/state
1366 /* target algorithm support */
1367 int arm11_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params,
1368 int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point,
1369 int timeout_ms, void *arch_info)
1370 {
1371 arm11_common_t *arm11 = target->arch_info;
1372 armv4_5_algorithm_t *arm11_algorithm_info = arch_info;
1373 // enum armv4_5_state core_state = arm11->core_state;
1374 // enum armv4_5_mode core_mode = arm11->core_mode;
1375 u32 context[16];
1376 u32 cpsr;
1377 int exit_breakpoint_size = 0;
1378 int retval = ERROR_OK;
1379 LOG_DEBUG("Running algorithm");
1380
1381 if (arm11_algorithm_info->common_magic != ARMV4_5_COMMON_MAGIC)
1382 {
1383 LOG_ERROR("current target isn't an ARMV4/5 target");
1384 return ERROR_TARGET_INVALID;
1385 }
1386
1387 if (target->state != TARGET_HALTED)
1388 {
1389 LOG_WARNING("target not halted");
1390 return ERROR_TARGET_NOT_HALTED;
1391 }
1392
1393 // FIXME
1394 // if (armv4_5_mode_to_number(arm11->core_mode)==-1)
1395 // return ERROR_FAIL;
1396
1397 // Save regs
1398 for (size_t i = 0; i < 16; i++)
1399 {
1400 context[i] = buf_get_u32((u8*)(&arm11->reg_values[i]),0,32);
1401 LOG_DEBUG("Save %zi: 0x%x",i,context[i]);
1402 }
1403
1404 cpsr = buf_get_u32((u8*)(arm11->reg_values+ARM11_RC_CPSR),0,32);
1405 LOG_DEBUG("Save CPSR: 0x%x", cpsr);
1406
1407 for (int i = 0; i < num_mem_params; i++)
1408 {
1409 target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
1410 }
1411
1412 // Set register parameters
1413 for (int i = 0; i < num_reg_params; i++)
1414 {
1415 reg_t *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0);
1416 if (!reg)
1417 {
1418 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
1419 exit(-1);
1420 }
1421
1422 if (reg->size != reg_params[i].size)
1423 {
1424 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
1425 exit(-1);
1426 }
1427 arm11_set_reg(reg,reg_params[i].value);
1428 // printf("%i: Set %s =%08x\n", i, reg_params[i].reg_name,val);
1429 }
1430
1431 exit_breakpoint_size = 4;
1432
1433 /* arm11->core_state = arm11_algorithm_info->core_state;
1434 if (arm11->core_state == ARMV4_5_STATE_ARM)
1435 exit_breakpoint_size = 4;
1436 else if (arm11->core_state == ARMV4_5_STATE_THUMB)
1437 exit_breakpoint_size = 2;
1438 else
1439 {
1440 LOG_ERROR("BUG: can't execute algorithms when not in ARM or Thumb state");
1441 exit(-1);
1442 }
1443 */
1444 if (arm11_algorithm_info->core_mode != ARMV4_5_MODE_ANY)
1445 {
1446 LOG_DEBUG("setting core_mode: 0x%2.2x", arm11_algorithm_info->core_mode);
1447 buf_set_u32(arm11->reg_list[ARM11_RC_CPSR].value, 0, 5, arm11_algorithm_info->core_mode);
1448 arm11->reg_list[ARM11_RC_CPSR].dirty = 1;
1449 arm11->reg_list[ARM11_RC_CPSR].valid = 1;
1450 }
1451
1452 if ((retval = breakpoint_add(target, exit_point, exit_breakpoint_size, BKPT_HARD)) != ERROR_OK)
1453 {
1454 LOG_ERROR("can't add breakpoint to finish algorithm execution");
1455 retval = ERROR_TARGET_FAILURE;
1456 goto restore;
1457 }
1458
1459 // no debug, otherwise breakpoint is not set
1460 CHECK_RETVAL(target_resume(target, 0, entry_point, 1, 0));
1461
1462 CHECK_RETVAL(target_wait_state(target, TARGET_HALTED, timeout_ms));
1463
1464 if (target->state != TARGET_HALTED)
1465 {
1466 CHECK_RETVAL(target_halt(target));
1467
1468 CHECK_RETVAL(target_wait_state(target, TARGET_HALTED, 500));
1469
1470 retval = ERROR_TARGET_TIMEOUT;
1471
1472 goto del_breakpoint;
1473 }
1474
1475 if (buf_get_u32(arm11->reg_list[15].value, 0, 32) != exit_point)
1476 {
1477 LOG_WARNING("target reentered debug state, but not at the desired exit point: 0x%4.4x",
1478 buf_get_u32(arm11->reg_list[15].value, 0, 32));
1479 retval = ERROR_TARGET_TIMEOUT;
1480 goto del_breakpoint;
1481 }
1482
1483 for (int i = 0; i < num_mem_params; i++)
1484 {
1485 if (mem_params[i].direction != PARAM_OUT)
1486 target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
1487 }
1488
1489 for (int i = 0; i < num_reg_params; i++)
1490 {
1491 if (reg_params[i].direction != PARAM_OUT)
1492 {
1493 reg_t *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0);
1494 if (!reg)
1495 {
1496 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
1497 exit(-1);
1498 }
1499
1500 if (reg->size != reg_params[i].size)
1501 {
1502 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
1503 exit(-1);
1504 }
1505
1506 buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
1507 }
1508 }
1509
1510 del_breakpoint:
1511 breakpoint_remove(target, exit_point);
1512
1513 restore:
1514 // Restore context
1515 for (size_t i = 0; i < 16; i++)
1516 {
1517 LOG_DEBUG("restoring register %s with value 0x%8.8x",
1518 arm11->reg_list[i].name, context[i]);
1519 arm11_set_reg(&arm11->reg_list[i], (u8*)&context[i]);
1520 }
1521 LOG_DEBUG("restoring CPSR with value 0x%8.8x", cpsr);
1522 arm11_set_reg(&arm11->reg_list[ARM11_RC_CPSR], (u8*)&cpsr);
1523
1524 // arm11->core_state = core_state;
1525 // arm11->core_mode = core_mode;
1526
1527 return retval;
1528 }
1529
1530 int arm11_target_create(struct target_s *target, Jim_Interp *interp)
1531 {
1532 FNC_INFO;
1533
1534 NEW(arm11_common_t, arm11, 1);
1535
1536 arm11->target = target;
1537
1538 /* prepare JTAG information for the new target */
1539 arm11->jtag_info.tap = target->tap;
1540 arm11->jtag_info.scann_size = 5;
1541
1542 CHECK_RETVAL(arm_jtag_setup_connection(&arm11->jtag_info));
1543
1544 if (target->tap==NULL)
1545 return ERROR_FAIL;
1546
1547 if (target->tap->ir_length != 5)
1548 {
1549 LOG_ERROR("'target arm11' expects IR LENGTH = 5");
1550 return ERROR_COMMAND_SYNTAX_ERROR;
1551 }
1552
1553 target->arch_info = arm11;
1554
1555 return ERROR_OK;
1556 }
1557
1558 int arm11_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
1559 {
1560 /* Initialize anything we can set up without talking to the target */
1561 return arm11_build_reg_cache(target);
1562 }
1563
1564 /* talk to the target and set things up */
1565 int arm11_examine(struct target_s *target)
1566 {
1567 FNC_INFO;
1568
1569 arm11_common_t * arm11 = target->arch_info;
1570
1571 /* check IDCODE */
1572
1573 arm11_add_IR(arm11, ARM11_IDCODE, ARM11_TAP_DEFAULT);
1574
1575 scan_field_t idcode_field;
1576
1577 arm11_setup_field(arm11, 32, NULL, &arm11->device_id, &idcode_field);
1578
1579 arm11_add_dr_scan_vc(1, &idcode_field, TAP_DRPAUSE);
1580
1581 /* check DIDR */
1582
1583 arm11_add_debug_SCAN_N(arm11, 0x00, ARM11_TAP_DEFAULT);
1584
1585 arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
1586
1587 scan_field_t chain0_fields[2];
1588
1589 arm11_setup_field(arm11, 32, NULL, &arm11->didr, chain0_fields + 0);
1590 arm11_setup_field(arm11, 8, NULL, &arm11->implementor, chain0_fields + 1);
1591
1592 arm11_add_dr_scan_vc(asizeof(chain0_fields), chain0_fields, TAP_IDLE);
1593
1594 CHECK_RETVAL(jtag_execute_queue());
1595
1596 switch (arm11->device_id & 0x0FFFF000)
1597 {
1598 case 0x07B36000: LOG_INFO("found ARM1136"); break;
1599 case 0x07B56000: LOG_INFO("found ARM1156"); break;
1600 case 0x07B76000: LOG_INFO("found ARM1176"); break;
1601 default:
1602 {
1603 LOG_ERROR("'target arm11' expects IDCODE 0x*7B*7****");
1604 return ERROR_FAIL;
1605 }
1606 }
1607
1608 arm11->debug_version = (arm11->didr >> 16) & 0x0F;
1609
1610 if (arm11->debug_version != ARM11_DEBUG_V6 &&
1611 arm11->debug_version != ARM11_DEBUG_V61)
1612 {
1613 LOG_ERROR("Only ARMv6 v6 and v6.1 architectures supported.");
1614 return ERROR_FAIL;
1615 }
1616
1617 arm11->brp = ((arm11->didr >> 24) & 0x0F) + 1;
1618 arm11->wrp = ((arm11->didr >> 28) & 0x0F) + 1;
1619
1620 /** \todo TODO: reserve one brp slot if we allow breakpoints during step */
1621 arm11->free_brps = arm11->brp;
1622 arm11->free_wrps = arm11->wrp;
1623
1624 LOG_DEBUG("IDCODE %08x IMPLEMENTOR %02x DIDR %08x",
1625 arm11->device_id,
1626 arm11->implementor,
1627 arm11->didr);
1628
1629 /* as a side-effect this reads DSCR and thus
1630 * clears the ARM11_DSCR_STICKY_PRECISE_DATA_ABORT / Sticky Precise Data Abort Flag
1631 * as suggested by the spec.
1632 */
1633
1634 arm11_check_init(arm11, NULL);
1635
1636 target->type->examined = 1;
1637
1638 return ERROR_OK;
1639 }
1640
1641 int arm11_quit(void)
1642 {
1643 FNC_INFO_NOTIMPLEMENTED;
1644
1645 return ERROR_OK;
1646 }
1647
1648 /** Load a register that is marked !valid in the register cache */
1649 int arm11_get_reg(reg_t *reg)
1650 {
1651 FNC_INFO;
1652
1653 target_t * target = ((arm11_reg_state_t *)reg->arch_info)->target;
1654
1655 if (target->state != TARGET_HALTED)
1656 {
1657 LOG_WARNING("target was not halted");
1658 return ERROR_TARGET_NOT_HALTED;
1659 }
1660
1661 /** \todo TODO: Check this. We assume that all registers are fetched at debug entry. */
1662
1663 #if 0
1664 arm11_common_t *arm11 = target->arch_info;
1665 const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index;
1666 #endif
1667
1668 return ERROR_OK;
1669 }
1670
1671 /** Change a value in the register cache */
1672 int arm11_set_reg(reg_t *reg, u8 *buf)
1673 {
1674 FNC_INFO;
1675
1676 target_t * target = ((arm11_reg_state_t *)reg->arch_info)->target;
1677 arm11_common_t *arm11 = target->arch_info;
1678 // const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index;
1679
1680 arm11->reg_values[((arm11_reg_state_t *)reg->arch_info)->def_index] = buf_get_u32(buf, 0, 32);
1681 reg->valid = 1;
1682 reg->dirty = 1;
1683
1684 return ERROR_OK;
1685 }
1686
1687 int arm11_build_reg_cache(target_t *target)
1688 {
1689 arm11_common_t *arm11 = target->arch_info;
1690
1691 NEW(reg_cache_t, cache, 1);
1692 NEW(reg_t, reg_list, ARM11_REGCACHE_COUNT);
1693 NEW(arm11_reg_state_t, arm11_reg_states, ARM11_REGCACHE_COUNT);
1694
1695 if (arm11_regs_arch_type == -1)
1696 arm11_regs_arch_type = register_reg_arch_type(arm11_get_reg, arm11_set_reg);
1697
1698 register_init_dummy(&arm11_gdb_dummy_fp_reg);
1699 register_init_dummy(&arm11_gdb_dummy_fps_reg);
1700
1701 arm11->reg_list = reg_list;
1702
1703 /* Build the process context cache */
1704 cache->name = "arm11 registers";
1705 cache->next = NULL;
1706 cache->reg_list = reg_list;
1707 cache->num_regs = ARM11_REGCACHE_COUNT;
1708
1709 reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
1710 (*cache_p) = cache;
1711
1712 arm11->core_cache = cache;
1713 // armv7m->process_context = cache;
1714
1715 size_t i;
1716
1717 /* Not very elegant assertion */
1718 if (ARM11_REGCACHE_COUNT != asizeof(arm11->reg_values) ||
1719 ARM11_REGCACHE_COUNT != asizeof(arm11_reg_defs) ||
1720 ARM11_REGCACHE_COUNT != ARM11_RC_MAX)
1721 {
1722 LOG_ERROR("BUG: arm11->reg_values inconsistent (%d " ZU " " ZU " %d)", ARM11_REGCACHE_COUNT, asizeof(arm11->reg_values), asizeof(arm11_reg_defs), ARM11_RC_MAX);
1723 exit(-1);
1724 }
1725
1726 for (i = 0; i < ARM11_REGCACHE_COUNT; i++)
1727 {
1728 reg_t * r = reg_list + i;
1729 const arm11_reg_defs_t * rd = arm11_reg_defs + i;
1730 arm11_reg_state_t * rs = arm11_reg_states + i;
1731
1732 r->name = rd->name;
1733 r->size = 32;
1734 r->value = (u8 *)(arm11->reg_values + i);
1735 r->dirty = 0;
1736 r->valid = 0;
1737 r->bitfield_desc = NULL;
1738 r->num_bitfields = 0;
1739 r->arch_type = arm11_regs_arch_type;
1740 r->arch_info = rs;
1741
1742 rs->def_index = i;
1743 rs->target = target;
1744 }
1745
1746 return ERROR_OK;
1747 }
1748
1749 int arm11_handle_bool(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, bool * var, char * name)
1750 {
1751 if (argc == 0)
1752 {
1753 LOG_INFO("%s is %s.", name, *var ? "enabled" : "disabled");
1754 return ERROR_OK;
1755 }
1756
1757 if (argc != 1)
1758 return ERROR_COMMAND_SYNTAX_ERROR;
1759
1760 switch (args[0][0])
1761 {
1762 case '0': /* 0 */
1763 case 'f': /* false */
1764 case 'F':
1765 case 'd': /* disable */
1766 case 'D':
1767 *var = false;
1768 break;
1769
1770 case '1': /* 1 */
1771 case 't': /* true */
1772 case 'T':
1773 case 'e': /* enable */
1774 case 'E':
1775 *var = true;
1776 break;
1777 }
1778
1779 LOG_INFO("%s %s.", *var ? "Enabled" : "Disabled", name);
1780
1781 return ERROR_OK;
1782 }
1783
1784 #define BOOL_WRAPPER(name, print_name) \
1785 int arm11_handle_bool_##name(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) \
1786 { \
1787 return arm11_handle_bool(cmd_ctx, cmd, args, argc, &arm11_config_##name, print_name); \
1788 }
1789
1790 #define RC_TOP(name, descr, more) \
1791 { \
1792 command_t * new_cmd = register_command(cmd_ctx, top_cmd, name, NULL, COMMAND_ANY, descr); \
1793 command_t * top_cmd = new_cmd; \
1794 more \
1795 }
1796
1797 #define RC_FINAL(name, descr, handler) \
1798 register_command(cmd_ctx, top_cmd, name, handler, COMMAND_ANY, descr);
1799
1800 #define RC_FINAL_BOOL(name, descr, var) \
1801 register_command(cmd_ctx, top_cmd, name, arm11_handle_bool_##var, COMMAND_ANY, descr);
1802
1803 BOOL_WRAPPER(memwrite_burst, "memory write burst mode")
1804 BOOL_WRAPPER(memwrite_error_fatal, "fatal error mode for memory writes")
1805 BOOL_WRAPPER(memrw_no_increment, "\"no increment\" mode for memory transfers")
1806 BOOL_WRAPPER(step_irq_enable, "IRQs while stepping")
1807
1808 int arm11_handle_vcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1809 {
1810 if (argc == 1)
1811 {
1812 arm11_vcr = strtoul(args[0], NULL, 0);
1813 }
1814 else if (argc != 0)
1815 {
1816 return ERROR_COMMAND_SYNTAX_ERROR;
1817 }
1818
1819 LOG_INFO("VCR 0x%08X", arm11_vcr);
1820 return ERROR_OK;
1821 }
1822
1823 const u32 arm11_coproc_instruction_limits[] =
1824 {
1825 15, /* coprocessor */
1826 7, /* opcode 1 */
1827 15, /* CRn */
1828 15, /* CRm */
1829 7, /* opcode 2 */
1830 0xFFFFFFFF, /* value */
1831 };
1832
1833 const char arm11_mrc_syntax[] = "Syntax: mrc <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2>. All parameters are numbers only.";
1834 const char arm11_mcr_syntax[] = "Syntax: mcr <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2> <32bit value to write>. All parameters are numbers only.";
1835
1836 arm11_common_t * arm11_find_target(const char * arg)
1837 {
1838 jtag_tap_t * tap;
1839 target_t * t;
1840
1841 tap = jtag_TapByString(arg);
1842
1843 if (!tap)
1844 return 0;
1845
1846 for (t = all_targets; t; t = t->next)
1847 {
1848 if (t->tap != tap)
1849 continue;
1850
1851 /* if (t->type == arm11_target) */
1852 if (0 == strcmp(t->type->name, "arm11"))
1853 return t->arch_info;
1854 }
1855
1856 return 0;
1857 }
1858
1859 int arm11_handle_mrc_mcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, bool read)
1860 {
1861 if (argc != (read ? 6 : 7))
1862 {
1863 LOG_ERROR("Invalid number of arguments. %s", read ? arm11_mrc_syntax : arm11_mcr_syntax);
1864 return -1;
1865 }
1866
1867 arm11_common_t * arm11 = arm11_find_target(args[0]);
1868
1869 if (!arm11)
1870 {
1871 LOG_ERROR("Parameter 1 is not a the JTAG chain position of an ARM11 device. %s",
1872 read ? arm11_mrc_syntax : arm11_mcr_syntax);
1873
1874 return -1;
1875 }
1876
1877 if (arm11->target->state != TARGET_HALTED)
1878 {
1879 LOG_WARNING("target was not halted");
1880 return ERROR_TARGET_NOT_HALTED;
1881 }
1882
1883 u32 values[6];
1884
1885 for (size_t i = 0; i < (read ? 5 : 6); i++)
1886 {
1887 values[i] = strtoul(args[i + 1], NULL, 0);
1888
1889 if (values[i] > arm11_coproc_instruction_limits[i])
1890 {
1891 LOG_ERROR("Parameter %ld out of bounds (%d max). %s",
1892 (long)(i + 2), arm11_coproc_instruction_limits[i],
1893 read ? arm11_mrc_syntax : arm11_mcr_syntax);
1894 return -1;
1895 }
1896 }
1897
1898 u32 instr = 0xEE000010 |
1899 (values[0] << 8) |
1900 (values[1] << 21) |
1901 (values[2] << 16) |
1902 (values[3] << 0) |
1903 (values[4] << 5);
1904
1905 if (read)
1906 instr |= 0x00100000;
1907
1908 arm11_run_instr_data_prepare(arm11);
1909
1910 if (read)
1911 {
1912 u32 result;
1913 arm11_run_instr_data_from_core_via_r0(arm11, instr, &result);
1914
1915 LOG_INFO("MRC p%d, %d, R0, c%d, c%d, %d = 0x%08x (%d)",
1916 values[0], values[1], values[2], values[3], values[4], result, result);
1917 }
1918 else
1919 {
1920 arm11_run_instr_data_to_core_via_r0(arm11, instr, values[5]);
1921
1922 LOG_INFO("MRC p%d, %d, R0 (#0x%08x), c%d, c%d, %d",
1923 values[0], values[1],
1924 values[5],
1925 values[2], values[3], values[4]);
1926 }
1927
1928 arm11_run_instr_data_finish(arm11);
1929
1930
1931 return ERROR_OK;
1932 }
1933
1934 int arm11_handle_mrc(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1935 {
1936 return arm11_handle_mrc_mcr(cmd_ctx, cmd, args, argc, true);
1937 }
1938
1939 int arm11_handle_mcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1940 {
1941 return arm11_handle_mrc_mcr(cmd_ctx, cmd, args, argc, false);
1942 }
1943
1944 int arm11_register_commands(struct command_context_s *cmd_ctx)
1945 {
1946 FNC_INFO;
1947
1948 command_t * top_cmd = NULL;
1949
1950 RC_TOP( "arm11", "arm11 specific commands",
1951
1952 RC_TOP( "memwrite", "Control memory write transfer mode",
1953
1954 RC_FINAL_BOOL( "burst", "Enable/Disable non-standard but fast burst mode (default: enabled)",
1955 memwrite_burst)
1956
1957 RC_FINAL_BOOL( "error_fatal", "Terminate program if transfer error was found (default: enabled)",
1958 memwrite_error_fatal)
1959 )
1960
1961 RC_FINAL_BOOL( "no_increment", "Don't increment address on multi-read/-write (default: disabled)",
1962 memrw_no_increment)
1963
1964 RC_FINAL_BOOL( "step_irq_enable", "Enable interrupts while stepping (default: disabled)",
1965 step_irq_enable)
1966
1967 RC_FINAL( "vcr", "Control (Interrupt) Vector Catch Register",
1968 arm11_handle_vcr)
1969
1970 RC_FINAL( "mrc", "Read Coprocessor register",
1971 arm11_handle_mrc)
1972
1973 RC_FINAL( "mcr", "Write Coprocessor register",
1974 arm11_handle_mcr)
1975 )
1976
1977 return ERROR_OK;
1978 }
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