1 /***************************************************************************
2 * Copyright (C) 2008 digenius technology GmbH. *
5 * Copyright (C) 2008,2009 Oyvind Harboe oyvind.harboe@zylin.com *
7 * Copyright (C) 2008 Georg Acher <acher@in.tum.de> *
9 * This program is free software; you can redistribute it and/or modify *
10 * it under the terms of the GNU General Public License as published by *
11 * the Free Software Foundation; either version 2 of the License, or *
12 * (at your option) any later version. *
14 * This program is distributed in the hope that it will be useful, *
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
17 * GNU General Public License for more details. *
19 * You should have received a copy of the GNU General Public License *
20 * along with this program; if not, write to the *
21 * Free Software Foundation, Inc., *
22 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
23 ***************************************************************************/
31 #include "arm_simulator.h"
32 #include "target_type.h"
36 #define _DEBUG_INSTRUCTION_EXECUTION_
40 #define FNC_INFO LOG_DEBUG("-")
46 #define FNC_INFO_NOTIMPLEMENTED do { LOG_DEBUG("NOT IMPLEMENTED"); /*exit(-1);*/ } while (0)
48 #define FNC_INFO_NOTIMPLEMENTED
51 static int arm11_on_enter_debug_state(arm11_common_t
* arm11
);
53 bool arm11_config_memwrite_burst
= true;
54 bool arm11_config_memwrite_error_fatal
= true;
55 uint32_t arm11_vcr
= 0;
56 bool arm11_config_memrw_no_increment
= false;
57 bool arm11_config_step_irq_enable
= false;
58 bool arm11_config_hardware_step
= false;
60 #define ARM11_HANDLER(x) \
63 target_type_t arm11_target
=
68 ARM11_HANDLER(arch_state
),
70 ARM11_HANDLER(target_request_data
),
73 ARM11_HANDLER(resume
),
76 ARM11_HANDLER(assert_reset
),
77 ARM11_HANDLER(deassert_reset
),
78 ARM11_HANDLER(soft_reset_halt
),
80 ARM11_HANDLER(get_gdb_reg_list
),
82 ARM11_HANDLER(read_memory
),
83 ARM11_HANDLER(write_memory
),
85 ARM11_HANDLER(bulk_write_memory
),
87 ARM11_HANDLER(checksum_memory
),
89 ARM11_HANDLER(add_breakpoint
),
90 ARM11_HANDLER(remove_breakpoint
),
91 ARM11_HANDLER(add_watchpoint
),
92 ARM11_HANDLER(remove_watchpoint
),
94 ARM11_HANDLER(run_algorithm
),
96 ARM11_HANDLER(register_commands
),
97 ARM11_HANDLER(target_create
),
98 ARM11_HANDLER(init_target
),
99 ARM11_HANDLER(examine
),
103 int arm11_regs_arch_type
= -1;
121 ARM11_REGISTER_SPSR_FIQ
,
122 ARM11_REGISTER_SPSR_SVC
,
123 ARM11_REGISTER_SPSR_ABT
,
124 ARM11_REGISTER_SPSR_IRQ
,
125 ARM11_REGISTER_SPSR_UND
,
126 ARM11_REGISTER_SPSR_MON
,
135 typedef struct arm11_reg_defs_s
140 enum arm11_regtype type
;
143 /* update arm11_regcache_ids when changing this */
144 static const arm11_reg_defs_t arm11_reg_defs
[] =
146 {"r0", 0, 0, ARM11_REGISTER_CORE
},
147 {"r1", 1, 1, ARM11_REGISTER_CORE
},
148 {"r2", 2, 2, ARM11_REGISTER_CORE
},
149 {"r3", 3, 3, ARM11_REGISTER_CORE
},
150 {"r4", 4, 4, ARM11_REGISTER_CORE
},
151 {"r5", 5, 5, ARM11_REGISTER_CORE
},
152 {"r6", 6, 6, ARM11_REGISTER_CORE
},
153 {"r7", 7, 7, ARM11_REGISTER_CORE
},
154 {"r8", 8, 8, ARM11_REGISTER_CORE
},
155 {"r9", 9, 9, ARM11_REGISTER_CORE
},
156 {"r10", 10, 10, ARM11_REGISTER_CORE
},
157 {"r11", 11, 11, ARM11_REGISTER_CORE
},
158 {"r12", 12, 12, ARM11_REGISTER_CORE
},
159 {"sp", 13, 13, ARM11_REGISTER_CORE
},
160 {"lr", 14, 14, ARM11_REGISTER_CORE
},
161 {"pc", 15, 15, ARM11_REGISTER_CORE
},
163 #if ARM11_REGCACHE_FREGS
164 {"f0", 0, 16, ARM11_REGISTER_FX
},
165 {"f1", 1, 17, ARM11_REGISTER_FX
},
166 {"f2", 2, 18, ARM11_REGISTER_FX
},
167 {"f3", 3, 19, ARM11_REGISTER_FX
},
168 {"f4", 4, 20, ARM11_REGISTER_FX
},
169 {"f5", 5, 21, ARM11_REGISTER_FX
},
170 {"f6", 6, 22, ARM11_REGISTER_FX
},
171 {"f7", 7, 23, ARM11_REGISTER_FX
},
172 {"fps", 0, 24, ARM11_REGISTER_FPS
},
175 {"cpsr", 0, 25, ARM11_REGISTER_CPSR
},
177 #if ARM11_REGCACHE_MODEREGS
178 {"r8_fiq", 8, -1, ARM11_REGISTER_FIQ
},
179 {"r9_fiq", 9, -1, ARM11_REGISTER_FIQ
},
180 {"r10_fiq", 10, -1, ARM11_REGISTER_FIQ
},
181 {"r11_fiq", 11, -1, ARM11_REGISTER_FIQ
},
182 {"r12_fiq", 12, -1, ARM11_REGISTER_FIQ
},
183 {"r13_fiq", 13, -1, ARM11_REGISTER_FIQ
},
184 {"r14_fiq", 14, -1, ARM11_REGISTER_FIQ
},
185 {"spsr_fiq", 0, -1, ARM11_REGISTER_SPSR_FIQ
},
187 {"r13_svc", 13, -1, ARM11_REGISTER_SVC
},
188 {"r14_svc", 14, -1, ARM11_REGISTER_SVC
},
189 {"spsr_svc", 0, -1, ARM11_REGISTER_SPSR_SVC
},
191 {"r13_abt", 13, -1, ARM11_REGISTER_ABT
},
192 {"r14_abt", 14, -1, ARM11_REGISTER_ABT
},
193 {"spsr_abt", 0, -1, ARM11_REGISTER_SPSR_ABT
},
195 {"r13_irq", 13, -1, ARM11_REGISTER_IRQ
},
196 {"r14_irq", 14, -1, ARM11_REGISTER_IRQ
},
197 {"spsr_irq", 0, -1, ARM11_REGISTER_SPSR_IRQ
},
199 {"r13_und", 13, -1, ARM11_REGISTER_UND
},
200 {"r14_und", 14, -1, ARM11_REGISTER_UND
},
201 {"spsr_und", 0, -1, ARM11_REGISTER_SPSR_UND
},
204 {"r13_mon", 13, -1, ARM11_REGISTER_MON
},
205 {"r14_mon", 14, -1, ARM11_REGISTER_MON
},
206 {"spsr_mon", 0, -1, ARM11_REGISTER_SPSR_MON
},
209 /* Debug Registers */
210 {"dscr", 0, -1, ARM11_REGISTER_DSCR
},
211 {"wdtr", 0, -1, ARM11_REGISTER_WDTR
},
212 {"rdtr", 0, -1, ARM11_REGISTER_RDTR
},
215 enum arm11_regcache_ids
218 ARM11_RC_RX
= ARM11_RC_R0
,
233 ARM11_RC_SP
= ARM11_RC_R13
,
235 ARM11_RC_LR
= ARM11_RC_R14
,
237 ARM11_RC_PC
= ARM11_RC_R15
,
239 #if ARM11_REGCACHE_FREGS
241 ARM11_RC_FX
= ARM11_RC_F0
,
254 #if ARM11_REGCACHE_MODEREGS
292 #define ARM11_GDB_REGISTER_COUNT 26
294 uint8_t arm11_gdb_dummy_fp_value
[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
296 reg_t arm11_gdb_dummy_fp_reg
=
298 "GDB dummy floating-point register", arm11_gdb_dummy_fp_value
, 0, 1, 96, NULL
, 0, NULL
, 0
301 uint8_t arm11_gdb_dummy_fps_value
[] = {0, 0, 0, 0};
303 reg_t arm11_gdb_dummy_fps_reg
=
305 "GDB dummy floating-point status register", arm11_gdb_dummy_fps_value
, 0, 1, 32, NULL
, 0, NULL
, 0
310 /** Check and if necessary take control of the system
312 * \param arm11 Target state variable.
313 * \param dscr If the current DSCR content is
314 * available a pointer to a word holding the
315 * DSCR can be passed. Otherwise use NULL.
317 int arm11_check_init(arm11_common_t
* arm11
, uint32_t * dscr
)
321 uint32_t dscr_local_tmp_copy
;
325 dscr
= &dscr_local_tmp_copy
;
327 CHECK_RETVAL(arm11_read_DSCR(arm11
, dscr
));
330 if (!(*dscr
& ARM11_DSCR_MODE_SELECT
))
332 LOG_DEBUG("Bringing target into debug mode");
334 *dscr
|= ARM11_DSCR_MODE_SELECT
; /* Halt debug-mode */
335 arm11_write_DSCR(arm11
, *dscr
);
337 /* add further reset initialization here */
339 arm11
->simulate_reset_on_next_halt
= true;
341 if (*dscr
& ARM11_DSCR_CORE_HALTED
)
343 /** \todo TODO: this needs further scrutiny because
344 * arm11_on_enter_debug_state() never gets properly called.
345 * As a result we don't read the actual register states from
349 arm11
->target
->state
= TARGET_HALTED
;
350 arm11
->target
->debug_reason
= arm11_get_DSCR_debug_reason(*dscr
);
354 arm11
->target
->state
= TARGET_RUNNING
;
355 arm11
->target
->debug_reason
= DBG_REASON_NOTHALTED
;
358 arm11_sc7_clear_vbw(arm11
);
367 (arm11->reg_values[ARM11_RC_##x])
369 /** Save processor state.
371 * This is called when the HALT instruction has succeeded
372 * or on other occasions that stop the processor.
375 static int arm11_on_enter_debug_state(arm11_common_t
* arm11
)
380 for (size_t i
= 0; i
< asizeof(arm11
->reg_values
); i
++)
382 arm11
->reg_list
[i
].valid
= 1;
383 arm11
->reg_list
[i
].dirty
= 0;
387 CHECK_RETVAL(arm11_read_DSCR(arm11
, &R(DSCR
)));
391 if (R(DSCR
) & ARM11_DSCR_WDTR_FULL
)
393 arm11_add_debug_SCAN_N(arm11
, 0x05, ARM11_TAP_DEFAULT
);
395 arm11_add_IR(arm11
, ARM11_INTEST
, ARM11_TAP_DEFAULT
);
397 scan_field_t chain5_fields
[3];
399 arm11_setup_field(arm11
, 32, NULL
, &R(WDTR
), chain5_fields
+ 0);
400 arm11_setup_field(arm11
, 1, NULL
, NULL
, chain5_fields
+ 1);
401 arm11_setup_field(arm11
, 1, NULL
, NULL
, chain5_fields
+ 2);
403 arm11_add_dr_scan_vc(asizeof(chain5_fields
), chain5_fields
, TAP_DRPAUSE
);
407 arm11
->reg_list
[ARM11_RC_WDTR
].valid
= 0;
411 /* DSCR: set ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE */
412 /* ARM1176 spec says this is needed only for wDTR/rDTR's "ITR mode", but not to issue ITRs
413 ARM1136 seems to require this to issue ITR's as well */
415 uint32_t new_dscr
= R(DSCR
) | ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE
;
417 /* this executes JTAG queue: */
419 arm11_write_DSCR(arm11
, new_dscr
);
423 Before executing any instruction in debug state you have to drain the write buffer.
424 This ensures that no imprecise Data Aborts can return at a later point:*/
426 /** \todo TODO: Test drain write buffer. */
431 /* MRC p14,0,R0,c5,c10,0 */
432 // arm11_run_instr_no_data1(arm11, /*0xee150e1a*/0xe320f000);
434 /* mcr 15, 0, r0, cr7, cr10, {4} */
435 arm11_run_instr_no_data1(arm11
, 0xee070f9a);
437 uint32_t dscr
= arm11_read_DSCR(arm11
);
439 LOG_DEBUG("DRAIN, DSCR %08x", dscr
);
441 if (dscr
& ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT
)
443 arm11_run_instr_no_data1(arm11
, 0xe320f000);
445 dscr
= arm11_read_DSCR(arm11
);
447 LOG_DEBUG("DRAIN, DSCR %08x (DONE)", dscr
);
454 arm11_run_instr_data_prepare(arm11
);
458 /** \todo TODO: handle other mode registers */
460 for (size_t i
= 0; i
< 15; i
++)
462 /* MCR p14,0,R?,c0,c5,0 */
463 retval
= arm11_run_instr_data_from_core(arm11
, 0xEE000E15 | (i
<< 12), &R(RX
+ i
), 1);
464 if (retval
!= ERROR_OK
)
470 /* check rDTRfull in DSCR */
472 if (R(DSCR
) & ARM11_DSCR_RDTR_FULL
)
474 /* MRC p14,0,R0,c0,c5,0 (move rDTR -> r0 (-> wDTR -> local var)) */
475 arm11_run_instr_data_from_core_via_r0(arm11
, 0xEE100E15, &R(RDTR
));
479 arm11
->reg_list
[ARM11_RC_RDTR
].valid
= 0;
484 /* MRS r0,CPSR (move CPSR -> r0 (-> wDTR -> local var)) */
485 arm11_run_instr_data_from_core_via_r0(arm11
, 0xE10F0000, &R(CPSR
));
489 /* MOV R0,PC (move PC -> r0 (-> wDTR -> local var)) */
490 retval
= arm11_run_instr_data_from_core_via_r0(arm11
, 0xE1A0000F, &R(PC
));
491 if (retval
!= ERROR_OK
)
494 /* adjust PC depending on ARM state */
496 if (R(CPSR
) & ARM11_CPSR_J
) /* Java state */
498 arm11
->reg_values
[ARM11_RC_PC
] -= 0;
500 else if (R(CPSR
) & ARM11_CPSR_T
) /* Thumb state */
502 arm11
->reg_values
[ARM11_RC_PC
] -= 4;
506 arm11
->reg_values
[ARM11_RC_PC
] -= 8;
509 if (arm11
->simulate_reset_on_next_halt
)
511 arm11
->simulate_reset_on_next_halt
= false;
513 LOG_DEBUG("Reset c1 Control Register");
515 /* Write 0 (reset value) to Control register 0 to disable MMU/Cache etc. */
517 /* MCR p15,0,R0,c1,c0,0 */
518 arm11_run_instr_data_to_core_via_r0(arm11
, 0xee010f10, 0);
522 arm11_run_instr_data_finish(arm11
);
524 arm11_dump_reg_changes(arm11
);
529 void arm11_dump_reg_changes(arm11_common_t
* arm11
)
532 if (!(debug_level
>= LOG_LVL_DEBUG
))
537 for (size_t i
= 0; i
< ARM11_REGCACHE_COUNT
; i
++)
539 if (!arm11
->reg_list
[i
].valid
)
541 if (arm11
->reg_history
[i
].valid
)
542 LOG_DEBUG("%8s INVALID (%08" PRIx32
")", arm11_reg_defs
[i
].name
, arm11
->reg_history
[i
].value
);
546 if (arm11
->reg_history
[i
].valid
)
548 if (arm11
->reg_history
[i
].value
!= arm11
->reg_values
[i
])
549 LOG_DEBUG("%8s %08" PRIx32
" (%08" PRIx32
")", arm11_reg_defs
[i
].name
, arm11
->reg_values
[i
], arm11
->reg_history
[i
].value
);
553 LOG_DEBUG("%8s %08" PRIx32
" (INVALID)", arm11_reg_defs
[i
].name
, arm11
->reg_values
[i
]);
559 /** Restore processor state
561 * This is called in preparation for the RESTART function.
564 int arm11_leave_debug_state(arm11_common_t
* arm11
)
568 arm11_run_instr_data_prepare(arm11
);
570 /** \todo TODO: handle other mode registers */
572 /* restore R1 - R14 */
574 for (size_t i
= 1; i
< 15; i
++)
576 if (!arm11
->reg_list
[ARM11_RC_RX
+ i
].dirty
)
579 /* MRC p14,0,r?,c0,c5,0 */
580 arm11_run_instr_data_to_core1(arm11
, 0xee100e15 | (i
<< 12), R(RX
+ i
));
582 // LOG_DEBUG("RESTORE R" ZU " %08x", i, R(RX + i));
585 arm11_run_instr_data_finish(arm11
);
587 /* spec says clear wDTR and rDTR; we assume they are clear as
588 otherwise our programming would be sloppy */
592 CHECK_RETVAL(arm11_read_DSCR(arm11
, &DSCR
));
594 if (DSCR
& (ARM11_DSCR_RDTR_FULL
| ARM11_DSCR_WDTR_FULL
))
596 LOG_ERROR("wDTR/rDTR inconsistent (DSCR %08" PRIx32
")", DSCR
);
600 arm11_run_instr_data_prepare(arm11
);
602 /* restore original wDTR */
604 if ((R(DSCR
) & ARM11_DSCR_WDTR_FULL
) || arm11
->reg_list
[ARM11_RC_WDTR
].dirty
)
606 /* MCR p14,0,R0,c0,c5,0 */
607 arm11_run_instr_data_to_core_via_r0(arm11
, 0xee000e15, R(WDTR
));
613 arm11_run_instr_data_to_core_via_r0(arm11
, 0xe129f000, R(CPSR
));
618 arm11_run_instr_data_to_core_via_r0(arm11
, 0xe1a0f000, R(PC
));
622 /* MRC p14,0,r0,c0,c5,0 */
623 arm11_run_instr_data_to_core1(arm11
, 0xee100e15, R(R0
));
625 arm11_run_instr_data_finish(arm11
);
629 arm11_write_DSCR(arm11
, R(DSCR
));
633 if (R(DSCR
) & ARM11_DSCR_RDTR_FULL
|| arm11
->reg_list
[ARM11_RC_RDTR
].dirty
)
635 arm11_add_debug_SCAN_N(arm11
, 0x05, ARM11_TAP_DEFAULT
);
637 arm11_add_IR(arm11
, ARM11_EXTEST
, ARM11_TAP_DEFAULT
);
639 scan_field_t chain5_fields
[3];
641 uint8_t Ready
= 0; /* ignored */
642 uint8_t Valid
= 0; /* ignored */
644 arm11_setup_field(arm11
, 32, &R(RDTR
), NULL
, chain5_fields
+ 0);
645 arm11_setup_field(arm11
, 1, &Ready
, NULL
, chain5_fields
+ 1);
646 arm11_setup_field(arm11
, 1, &Valid
, NULL
, chain5_fields
+ 2);
648 arm11_add_dr_scan_vc(asizeof(chain5_fields
), chain5_fields
, TAP_DRPAUSE
);
651 arm11_record_register_history(arm11
);
656 void arm11_record_register_history(arm11_common_t
* arm11
)
658 for (size_t i
= 0; i
< ARM11_REGCACHE_COUNT
; i
++)
660 arm11
->reg_history
[i
].value
= arm11
->reg_values
[i
];
661 arm11
->reg_history
[i
].valid
= arm11
->reg_list
[i
].valid
;
663 arm11
->reg_list
[i
].valid
= 0;
664 arm11
->reg_list
[i
].dirty
= 0;
669 /* poll current target status */
670 int arm11_poll(struct target_s
*target
)
675 arm11_common_t
* arm11
= target
->arch_info
;
677 if (arm11
->trst_active
)
682 CHECK_RETVAL(arm11_read_DSCR(arm11
, &dscr
));
684 LOG_DEBUG("DSCR %08" PRIx32
"", dscr
);
686 CHECK_RETVAL(arm11_check_init(arm11
, &dscr
));
688 if (dscr
& ARM11_DSCR_CORE_HALTED
)
690 if (target
->state
!= TARGET_HALTED
)
692 enum target_state old_state
= target
->state
;
694 LOG_DEBUG("enter TARGET_HALTED");
695 target
->state
= TARGET_HALTED
;
696 target
->debug_reason
= arm11_get_DSCR_debug_reason(dscr
);
697 retval
= arm11_on_enter_debug_state(arm11
);
698 if (retval
!= ERROR_OK
)
701 target_call_event_callbacks(target
,
702 old_state
== TARGET_DEBUG_RUNNING
? TARGET_EVENT_DEBUG_HALTED
: TARGET_EVENT_HALTED
);
707 if (target
->state
!= TARGET_RUNNING
&& target
->state
!= TARGET_DEBUG_RUNNING
)
709 LOG_DEBUG("enter TARGET_RUNNING");
710 target
->state
= TARGET_RUNNING
;
711 target
->debug_reason
= DBG_REASON_NOTHALTED
;
717 /* architecture specific status reply */
718 int arm11_arch_state(struct target_s
*target
)
720 arm11_common_t
* arm11
= target
->arch_info
;
722 LOG_USER("target halted due to %s\ncpsr: 0x%8.8" PRIx32
" pc: 0x%8.8" PRIx32
"",
723 Jim_Nvp_value2name_simple(nvp_target_debug_reason
, target
->debug_reason
)->name
,
730 /* target request support */
731 int arm11_target_request_data(struct target_s
*target
, uint32_t size
, uint8_t *buffer
)
733 FNC_INFO_NOTIMPLEMENTED
;
738 /* target execution control */
739 int arm11_halt(struct target_s
*target
)
743 arm11_common_t
* arm11
= target
->arch_info
;
745 LOG_DEBUG("target->state: %s",
746 target_state_name(target
));
748 if (target
->state
== TARGET_UNKNOWN
)
750 arm11
->simulate_reset_on_next_halt
= true;
753 if (target
->state
== TARGET_HALTED
)
755 LOG_DEBUG("target was already halted");
759 if (arm11
->trst_active
)
761 arm11
->halt_requested
= true;
765 arm11_add_IR(arm11
, ARM11_HALT
, TAP_IDLE
);
767 CHECK_RETVAL(jtag_execute_queue());
773 CHECK_RETVAL(arm11_read_DSCR(arm11
, &dscr
));
775 if (dscr
& ARM11_DSCR_CORE_HALTED
)
779 arm11_on_enter_debug_state(arm11
);
781 enum target_state old_state
= target
->state
;
783 target
->state
= TARGET_HALTED
;
784 target
->debug_reason
= arm11_get_DSCR_debug_reason(dscr
);
787 target_call_event_callbacks(target
,
788 old_state
== TARGET_DEBUG_RUNNING
? TARGET_EVENT_DEBUG_HALTED
: TARGET_EVENT_HALTED
));
793 int arm11_resume(struct target_s
*target
, int current
, uint32_t address
, int handle_breakpoints
, int debug_execution
)
797 // LOG_DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d",
798 // current, address, handle_breakpoints, debug_execution);
800 arm11_common_t
* arm11
= target
->arch_info
;
802 LOG_DEBUG("target->state: %s",
803 target_state_name(target
));
806 if (target
->state
!= TARGET_HALTED
)
808 LOG_ERROR("Target not halted");
809 return ERROR_TARGET_NOT_HALTED
;
815 LOG_DEBUG("RESUME PC %08" PRIx32
"%s", R(PC
), !current
? "!" : "");
817 /* clear breakpoints/watchpoints and VCR*/
818 arm11_sc7_clear_vbw(arm11
);
820 /* Set up breakpoints */
821 if (!debug_execution
)
823 /* check if one matches PC and step over it if necessary */
827 for (bp
= target
->breakpoints
; bp
; bp
= bp
->next
)
829 if (bp
->address
== R(PC
))
831 LOG_DEBUG("must step over %08" PRIx32
"", bp
->address
);
832 arm11_step(target
, 1, 0, 0);
837 /* set all breakpoints */
841 for (bp
= target
->breakpoints
; bp
; bp
= bp
->next
)
843 arm11_sc7_action_t brp
[2];
846 brp
[0].address
= ARM11_SC7_BVR0
+ brp_num
;
847 brp
[0].value
= bp
->address
;
849 brp
[1].address
= ARM11_SC7_BCR0
+ brp_num
;
850 brp
[1].value
= 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
852 arm11_sc7_run(arm11
, brp
, asizeof(brp
));
854 LOG_DEBUG("Add BP " ZU
" at %08" PRIx32
"", brp_num
, bp
->address
);
859 arm11_sc7_set_vcr(arm11
, arm11_vcr
);
862 arm11_leave_debug_state(arm11
);
864 arm11_add_IR(arm11
, ARM11_RESTART
, TAP_IDLE
);
866 CHECK_RETVAL(jtag_execute_queue());
872 CHECK_RETVAL(arm11_read_DSCR(arm11
, &dscr
));
874 LOG_DEBUG("DSCR %08" PRIx32
"", dscr
);
876 if (dscr
& ARM11_DSCR_CORE_RESTARTED
)
880 if (!debug_execution
)
882 target
->state
= TARGET_RUNNING
;
883 target
->debug_reason
= DBG_REASON_NOTHALTED
;
885 CHECK_RETVAL(target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
));
889 target
->state
= TARGET_DEBUG_RUNNING
;
890 target
->debug_reason
= DBG_REASON_NOTHALTED
;
892 CHECK_RETVAL(target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
));
899 static int armv4_5_to_arm11(int reg
)
906 return ARM11_RC_CPSR
;
908 /* FIX!!! handle thumb better! */
909 return ARM11_RC_CPSR
;
911 LOG_ERROR("BUG: register translation from armv4_5 to arm11 not supported %d", reg
);
917 static uint32_t arm11_sim_get_reg(struct arm_sim_interface
*sim
, int reg
)
919 arm11_common_t
* arm11
= (arm11_common_t
*)sim
->user_data
;
921 reg
=armv4_5_to_arm11(reg
);
923 return buf_get_u32(arm11
->reg_list
[reg
].value
, 0, 32);
926 static void arm11_sim_set_reg(struct arm_sim_interface
*sim
, int reg
, uint32_t value
)
928 arm11_common_t
* arm11
= (arm11_common_t
*)sim
->user_data
;
930 reg
=armv4_5_to_arm11(reg
);
932 buf_set_u32(arm11
->reg_list
[reg
].value
, 0, 32, value
);
935 static uint32_t arm11_sim_get_cpsr(struct arm_sim_interface
*sim
, int pos
, int bits
)
937 arm11_common_t
* arm11
= (arm11_common_t
*)sim
->user_data
;
939 return buf_get_u32(arm11
->reg_list
[ARM11_RC_CPSR
].value
, pos
, bits
);
942 static enum armv4_5_state
arm11_sim_get_state(struct arm_sim_interface
*sim
)
944 // arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
946 /* FIX!!!! we should implement thumb for arm11 */
947 return ARMV4_5_STATE_ARM
;
950 static void arm11_sim_set_state(struct arm_sim_interface
*sim
, enum armv4_5_state mode
)
952 // arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
954 /* FIX!!!! we should implement thumb for arm11 */
955 LOG_ERROR("Not implemetned!");
959 static enum armv4_5_mode
arm11_sim_get_mode(struct arm_sim_interface
*sim
)
961 //arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
963 /* FIX!!!! we should implement something that returns the current mode here!!! */
964 return ARMV4_5_MODE_USR
;
967 static int arm11_simulate_step(target_t
*target
, uint32_t *dry_run_pc
)
969 struct arm_sim_interface sim
;
971 sim
.user_data
=target
->arch_info
;
972 sim
.get_reg
=&arm11_sim_get_reg
;
973 sim
.set_reg
=&arm11_sim_set_reg
;
974 sim
.get_reg_mode
=&arm11_sim_get_reg
;
975 sim
.set_reg_mode
=&arm11_sim_set_reg
;
976 sim
.get_cpsr
=&arm11_sim_get_cpsr
;
977 sim
.get_mode
=&arm11_sim_get_mode
;
978 sim
.get_state
=&arm11_sim_get_state
;
979 sim
.set_state
=&arm11_sim_set_state
;
981 return arm_simulate_step_core(target
, dry_run_pc
, &sim
);
985 int arm11_step(struct target_s
*target
, int current
, uint32_t address
, int handle_breakpoints
)
989 LOG_DEBUG("target->state: %s",
990 target_state_name(target
));
992 if (target
->state
!= TARGET_HALTED
)
994 LOG_WARNING("target was not halted");
995 return ERROR_TARGET_NOT_HALTED
;
998 arm11_common_t
* arm11
= target
->arch_info
;
1003 LOG_DEBUG("STEP PC %08" PRIx32
"%s", R(PC
), !current
? "!" : "");
1006 /** \todo TODO: Thumb not supported here */
1008 uint32_t next_instruction
;
1010 CHECK_RETVAL(arm11_read_memory_word(arm11
, R(PC
), &next_instruction
));
1012 /* skip over BKPT */
1013 if ((next_instruction
& 0xFFF00070) == 0xe1200070)
1016 arm11
->reg_list
[ARM11_RC_PC
].valid
= 1;
1017 arm11
->reg_list
[ARM11_RC_PC
].dirty
= 0;
1018 LOG_DEBUG("Skipping BKPT");
1020 /* skip over Wait for interrupt / Standby */
1021 /* mcr 15, 0, r?, cr7, cr0, {4} */
1022 else if ((next_instruction
& 0xFFFF0FFF) == 0xee070f90)
1025 arm11
->reg_list
[ARM11_RC_PC
].valid
= 1;
1026 arm11
->reg_list
[ARM11_RC_PC
].dirty
= 0;
1027 LOG_DEBUG("Skipping WFI");
1029 /* ignore B to self */
1030 else if ((next_instruction
& 0xFEFFFFFF) == 0xeafffffe)
1032 LOG_DEBUG("Not stepping jump to self");
1036 /** \todo TODO: check if break-/watchpoints make any sense at all in combination
1039 /** \todo TODO: check if disabling IRQs might be a good idea here. Alternatively
1040 * the VCR might be something worth looking into. */
1043 /* Set up breakpoint for stepping */
1045 arm11_sc7_action_t brp
[2];
1048 brp
[0].address
= ARM11_SC7_BVR0
;
1050 brp
[1].address
= ARM11_SC7_BCR0
;
1052 if (arm11_config_hardware_step
)
1054 /* hardware single stepping be used if possible or is it better to
1055 * always use the same code path? Hardware single stepping is not supported
1058 brp
[0].value
= R(PC
);
1059 brp
[1].value
= 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (2 << 21);
1062 /* sets a breakpoint on the next PC(calculated by simulation),
1066 retval
= arm11_simulate_step(target
, &next_pc
);
1067 if (retval
!= ERROR_OK
)
1070 brp
[0].value
= next_pc
;
1071 brp
[1].value
= 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
1074 CHECK_RETVAL(arm11_sc7_run(arm11
, brp
, asizeof(brp
)));
1079 if (arm11_config_step_irq_enable
)
1080 R(DSCR
) &= ~ARM11_DSCR_INTERRUPTS_DISABLE
; /* should be redundant */
1082 R(DSCR
) |= ARM11_DSCR_INTERRUPTS_DISABLE
;
1085 CHECK_RETVAL(arm11_leave_debug_state(arm11
));
1087 arm11_add_IR(arm11
, ARM11_RESTART
, TAP_IDLE
);
1089 CHECK_RETVAL(jtag_execute_queue());
1091 /** \todo TODO: add a timeout */
1099 CHECK_RETVAL(arm11_read_DSCR(arm11
, &dscr
));
1101 LOG_DEBUG("DSCR %08" PRIx32
"e", dscr
);
1103 if ((dscr
& (ARM11_DSCR_CORE_RESTARTED
| ARM11_DSCR_CORE_HALTED
)) ==
1104 (ARM11_DSCR_CORE_RESTARTED
| ARM11_DSCR_CORE_HALTED
))
1108 /* clear breakpoint */
1109 arm11_sc7_clear_vbw(arm11
);
1112 CHECK_RETVAL(arm11_on_enter_debug_state(arm11
));
1114 /* restore default state */
1115 R(DSCR
) &= ~ARM11_DSCR_INTERRUPTS_DISABLE
;
1119 // target->state = TARGET_HALTED;
1120 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
1122 CHECK_RETVAL(target_call_event_callbacks(target
, TARGET_EVENT_HALTED
));
1127 /* target reset control */
1128 int arm11_assert_reset(struct target_s
*target
)
1133 /* assert reset lines */
1134 /* resets only the DBGTAP, not the ARM */
1136 jtag_add_reset(1, 0);
1137 jtag_add_sleep(5000);
1139 arm11_common_t
* arm11
= target
->arch_info
;
1140 arm11
->trst_active
= true;
1143 if (target
->reset_halt
)
1145 CHECK_RETVAL(target_halt(target
));
1151 int arm11_deassert_reset(struct target_s
*target
)
1156 LOG_DEBUG("target->state: %s",
1157 target_state_name(target
));
1160 /* deassert reset lines */
1161 jtag_add_reset(0, 0);
1163 arm11_common_t
* arm11
= target
->arch_info
;
1164 arm11
->trst_active
= false;
1166 if (arm11
->halt_requested
)
1167 return arm11_halt(target
);
1173 int arm11_soft_reset_halt(struct target_s
*target
)
1175 FNC_INFO_NOTIMPLEMENTED
;
1180 /* target register access for gdb */
1181 int arm11_get_gdb_reg_list(struct target_s
*target
, struct reg_s
**reg_list
[], int *reg_list_size
)
1185 arm11_common_t
* arm11
= target
->arch_info
;
1187 *reg_list_size
= ARM11_GDB_REGISTER_COUNT
;
1188 *reg_list
= malloc(sizeof(reg_t
*) * ARM11_GDB_REGISTER_COUNT
);
1190 for (size_t i
= 16; i
< 24; i
++)
1192 (*reg_list
)[i
] = &arm11_gdb_dummy_fp_reg
;
1195 (*reg_list
)[24] = &arm11_gdb_dummy_fps_reg
;
1197 for (size_t i
= 0; i
< ARM11_REGCACHE_COUNT
; i
++)
1199 if (arm11_reg_defs
[i
].gdb_num
== -1)
1202 (*reg_list
)[arm11_reg_defs
[i
].gdb_num
] = arm11
->reg_list
+ i
;
1208 /* target memory access
1209 * size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
1210 * count: number of items of <size>
1212 int arm11_read_memory(struct target_s
*target
, uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
)
1214 /** \todo TODO: check if buffer cast to uint32_t* and uint16_t* might cause alignment problems */
1218 if (target
->state
!= TARGET_HALTED
)
1220 LOG_WARNING("target was not halted");
1221 return ERROR_TARGET_NOT_HALTED
;
1224 LOG_DEBUG("ADDR %08" PRIx32
" SIZE %08" PRIx32
" COUNT %08" PRIx32
"", address
, size
, count
);
1226 arm11_common_t
* arm11
= target
->arch_info
;
1228 arm11_run_instr_data_prepare(arm11
);
1230 /* MRC p14,0,r0,c0,c5,0 */
1231 arm11_run_instr_data_to_core1(arm11
, 0xee100e15, address
);
1236 /** \todo TODO: check if dirty is the right choice to force a rewrite on arm11_resume() */
1237 arm11
->reg_list
[ARM11_RC_R1
].dirty
= 1;
1239 for (size_t i
= 0; i
< count
; i
++)
1241 /* ldrb r1, [r0], #1 */
1243 arm11_run_instr_no_data1(arm11
,
1244 !arm11_config_memrw_no_increment
? 0xe4d01001 : 0xe5d01000);
1247 /* MCR p14,0,R1,c0,c5,0 */
1248 arm11_run_instr_data_from_core(arm11
, 0xEE001E15, &res
, 1);
1257 arm11
->reg_list
[ARM11_RC_R1
].dirty
= 1;
1259 for (size_t i
= 0; i
< count
; i
++)
1261 /* ldrh r1, [r0], #2 */
1262 arm11_run_instr_no_data1(arm11
,
1263 !arm11_config_memrw_no_increment
? 0xe0d010b2 : 0xe1d010b0);
1267 /* MCR p14,0,R1,c0,c5,0 */
1268 arm11_run_instr_data_from_core(arm11
, 0xEE001E15, &res
, 1);
1270 uint16_t svalue
= res
;
1271 memcpy(buffer
+ i
* sizeof(uint16_t), &svalue
, sizeof(uint16_t));
1279 uint32_t instr
= !arm11_config_memrw_no_increment
? 0xecb05e01 : 0xed905e00;
1280 /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
1281 uint32_t *words
= (uint32_t *)buffer
;
1283 /* LDC p14,c5,[R0],#4 */
1284 /* LDC p14,c5,[R0] */
1285 arm11_run_instr_data_from_core(arm11
, instr
, words
, count
);
1290 arm11_run_instr_data_finish(arm11
);
1295 int arm11_write_memory(struct target_s
*target
, uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
)
1299 if (target
->state
!= TARGET_HALTED
)
1301 LOG_WARNING("target was not halted");
1302 return ERROR_TARGET_NOT_HALTED
;
1305 LOG_DEBUG("ADDR %08" PRIx32
" SIZE %08" PRIx32
" COUNT %08" PRIx32
"", address
, size
, count
);
1307 arm11_common_t
* arm11
= target
->arch_info
;
1309 arm11_run_instr_data_prepare(arm11
);
1311 /* MRC p14,0,r0,c0,c5,0 */
1312 arm11_run_instr_data_to_core1(arm11
, 0xee100e15, address
);
1318 arm11
->reg_list
[ARM11_RC_R1
].dirty
= 1;
1320 for (size_t i
= 0; i
< count
; i
++)
1322 /* MRC p14,0,r1,c0,c5,0 */
1323 arm11_run_instr_data_to_core1(arm11
, 0xee101e15, *buffer
++);
1325 /* strb r1, [r0], #1 */
1327 arm11_run_instr_no_data1(arm11
,
1328 !arm11_config_memrw_no_increment
? 0xe4c01001 : 0xe5c01000);
1336 arm11
->reg_list
[ARM11_RC_R1
].dirty
= 1;
1338 for (size_t i
= 0; i
< count
; i
++)
1341 memcpy(&value
, buffer
+ i
* sizeof(uint16_t), sizeof(uint16_t));
1343 /* MRC p14,0,r1,c0,c5,0 */
1344 arm11_run_instr_data_to_core1(arm11
, 0xee101e15, value
);
1346 /* strh r1, [r0], #2 */
1348 arm11_run_instr_no_data1(arm11
,
1349 !arm11_config_memrw_no_increment
? 0xe0c010b2 : 0xe1c010b0);
1356 uint32_t instr
= !arm11_config_memrw_no_increment
? 0xeca05e01 : 0xed805e00;
1358 /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
1359 uint32_t *words
= (uint32_t*)buffer
;
1361 if (!arm11_config_memwrite_burst
)
1363 /* STC p14,c5,[R0],#4 */
1364 /* STC p14,c5,[R0]*/
1365 arm11_run_instr_data_to_core(arm11
, instr
, words
, count
);
1369 /* STC p14,c5,[R0],#4 */
1370 /* STC p14,c5,[R0]*/
1371 arm11_run_instr_data_to_core_noack(arm11
, instr
, words
, count
);
1379 /* r0 verification */
1380 if (!arm11_config_memrw_no_increment
)
1384 /* MCR p14,0,R0,c0,c5,0 */
1385 arm11_run_instr_data_from_core(arm11
, 0xEE000E15, &r0
, 1);
1387 if (address
+ size
* count
!= r0
)
1389 LOG_ERROR("Data transfer failed. (%d)", (int)((r0
- address
) - size
* count
));
1391 if (arm11_config_memwrite_burst
)
1392 LOG_ERROR("use 'arm11 memwrite burst disable' to disable fast burst mode");
1394 if (arm11_config_memwrite_error_fatal
)
1400 arm11_run_instr_data_finish(arm11
);
1406 /* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
1407 int arm11_bulk_write_memory(struct target_s
*target
, uint32_t address
, uint32_t count
, uint8_t *buffer
)
1411 if (target
->state
!= TARGET_HALTED
)
1413 LOG_WARNING("target was not halted");
1414 return ERROR_TARGET_NOT_HALTED
;
1417 return arm11_write_memory(target
, address
, 4, count
, buffer
);
1420 /* here we have nothing target specific to contribute, so we fail and then the
1421 * fallback code will read data from the target and calculate the CRC on the
1424 int arm11_checksum_memory(struct target_s
*target
, uint32_t address
, uint32_t count
, uint32_t* checksum
)
1429 /* target break-/watchpoint control
1430 * rw: 0 = write, 1 = read, 2 = access
1432 int arm11_add_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
)
1436 arm11_common_t
* arm11
= target
->arch_info
;
1439 if (breakpoint
->type
== BKPT_SOFT
)
1441 LOG_INFO("sw breakpoint requested, but software breakpoints not enabled");
1442 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1446 if (!arm11
->free_brps
)
1448 LOG_DEBUG("no breakpoint unit available for hardware breakpoint");
1449 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1452 if (breakpoint
->length
!= 4)
1454 LOG_DEBUG("only breakpoints of four bytes length supported");
1455 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1463 int arm11_remove_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
)
1467 arm11_common_t
* arm11
= target
->arch_info
;
1474 int arm11_add_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
)
1476 FNC_INFO_NOTIMPLEMENTED
;
1481 int arm11_remove_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
)
1483 FNC_INFO_NOTIMPLEMENTED
;
1488 // HACKHACKHACK - FIXME mode/state
1489 /* target algorithm support */
1490 int arm11_run_algorithm(struct target_s
*target
, int num_mem_params
, mem_param_t
*mem_params
,
1491 int num_reg_params
, reg_param_t
*reg_params
, uint32_t entry_point
, uint32_t exit_point
,
1492 int timeout_ms
, void *arch_info
)
1494 arm11_common_t
*arm11
= target
->arch_info
;
1495 // enum armv4_5_state core_state = arm11->core_state;
1496 // enum armv4_5_mode core_mode = arm11->core_mode;
1497 uint32_t context
[16];
1499 int exit_breakpoint_size
= 0;
1500 int retval
= ERROR_OK
;
1501 LOG_DEBUG("Running algorithm");
1504 if (target
->state
!= TARGET_HALTED
)
1506 LOG_WARNING("target not halted");
1507 return ERROR_TARGET_NOT_HALTED
;
1511 // if (armv4_5_mode_to_number(arm11->core_mode)==-1)
1512 // return ERROR_FAIL;
1515 for (size_t i
= 0; i
< 16; i
++)
1517 context
[i
] = buf_get_u32((uint8_t*)(&arm11
->reg_values
[i
]),0,32);
1518 LOG_DEBUG("Save %zi: 0x%" PRIx32
"",i
,context
[i
]);
1521 cpsr
= buf_get_u32((uint8_t*)(arm11
->reg_values
+ ARM11_RC_CPSR
),0,32);
1522 LOG_DEBUG("Save CPSR: 0x%" PRIx32
"", cpsr
);
1524 for (int i
= 0; i
< num_mem_params
; i
++)
1526 target_write_buffer(target
, mem_params
[i
].address
, mem_params
[i
].size
, mem_params
[i
].value
);
1529 // Set register parameters
1530 for (int i
= 0; i
< num_reg_params
; i
++)
1532 reg_t
*reg
= register_get_by_name(arm11
->core_cache
, reg_params
[i
].reg_name
, 0);
1535 LOG_ERROR("BUG: register '%s' not found", reg_params
[i
].reg_name
);
1539 if (reg
->size
!= reg_params
[i
].size
)
1541 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params
[i
].reg_name
);
1544 arm11_set_reg(reg
,reg_params
[i
].value
);
1545 // printf("%i: Set %s =%08x\n", i, reg_params[i].reg_name,val);
1548 exit_breakpoint_size
= 4;
1550 /* arm11->core_state = arm11_algorithm_info->core_state;
1551 if (arm11->core_state == ARMV4_5_STATE_ARM)
1552 exit_breakpoint_size = 4;
1553 else if (arm11->core_state == ARMV4_5_STATE_THUMB)
1554 exit_breakpoint_size = 2;
1557 LOG_ERROR("BUG: can't execute algorithms when not in ARM or Thumb state");
1563 /* arm11 at this point only supports ARM not THUMB mode
1564 however if this test needs to be reactivated the current state can be read back
1567 if (arm11_algorithm_info
->core_mode
!= ARMV4_5_MODE_ANY
)
1569 LOG_DEBUG("setting core_mode: 0x%2.2x", arm11_algorithm_info
->core_mode
);
1570 buf_set_u32(arm11
->reg_list
[ARM11_RC_CPSR
].value
, 0, 5, arm11_algorithm_info
->core_mode
);
1571 arm11
->reg_list
[ARM11_RC_CPSR
].dirty
= 1;
1572 arm11
->reg_list
[ARM11_RC_CPSR
].valid
= 1;
1576 if ((retval
= breakpoint_add(target
, exit_point
, exit_breakpoint_size
, BKPT_HARD
)) != ERROR_OK
)
1578 LOG_ERROR("can't add breakpoint to finish algorithm execution");
1579 retval
= ERROR_TARGET_FAILURE
;
1583 // no debug, otherwise breakpoint is not set
1584 CHECK_RETVAL(target_resume(target
, 0, entry_point
, 1, 0));
1586 CHECK_RETVAL(target_wait_state(target
, TARGET_HALTED
, timeout_ms
));
1588 if (target
->state
!= TARGET_HALTED
)
1590 CHECK_RETVAL(target_halt(target
));
1592 CHECK_RETVAL(target_wait_state(target
, TARGET_HALTED
, 500));
1594 retval
= ERROR_TARGET_TIMEOUT
;
1596 goto del_breakpoint
;
1599 if (buf_get_u32(arm11
->reg_list
[15].value
, 0, 32) != exit_point
)
1601 LOG_WARNING("target reentered debug state, but not at the desired exit point: 0x%4.4" PRIx32
"",
1602 buf_get_u32(arm11
->reg_list
[15].value
, 0, 32));
1603 retval
= ERROR_TARGET_TIMEOUT
;
1604 goto del_breakpoint
;
1607 for (int i
= 0; i
< num_mem_params
; i
++)
1609 if (mem_params
[i
].direction
!= PARAM_OUT
)
1610 target_read_buffer(target
, mem_params
[i
].address
, mem_params
[i
].size
, mem_params
[i
].value
);
1613 for (int i
= 0; i
< num_reg_params
; i
++)
1615 if (reg_params
[i
].direction
!= PARAM_OUT
)
1617 reg_t
*reg
= register_get_by_name(arm11
->core_cache
, reg_params
[i
].reg_name
, 0);
1620 LOG_ERROR("BUG: register '%s' not found", reg_params
[i
].reg_name
);
1624 if (reg
->size
!= reg_params
[i
].size
)
1626 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params
[i
].reg_name
);
1630 buf_set_u32(reg_params
[i
].value
, 0, 32, buf_get_u32(reg
->value
, 0, 32));
1635 breakpoint_remove(target
, exit_point
);
1639 for (size_t i
= 0; i
< 16; i
++)
1641 LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32
"",
1642 arm11
->reg_list
[i
].name
, context
[i
]);
1643 arm11_set_reg(&arm11
->reg_list
[i
], (uint8_t*)&context
[i
]);
1645 LOG_DEBUG("restoring CPSR with value 0x%8.8" PRIx32
"", cpsr
);
1646 arm11_set_reg(&arm11
->reg_list
[ARM11_RC_CPSR
], (uint8_t*)&cpsr
);
1648 // arm11->core_state = core_state;
1649 // arm11->core_mode = core_mode;
1654 int arm11_target_create(struct target_s
*target
, Jim_Interp
*interp
)
1658 NEW(arm11_common_t
, arm11
, 1);
1660 arm11
->target
= target
;
1662 if (target
->tap
== NULL
)
1665 if (target
->tap
->ir_length
!= 5)
1667 LOG_ERROR("'target arm11' expects IR LENGTH = 5");
1668 return ERROR_COMMAND_SYNTAX_ERROR
;
1671 target
->arch_info
= arm11
;
1676 int arm11_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
)
1678 /* Initialize anything we can set up without talking to the target */
1679 return arm11_build_reg_cache(target
);
1682 /* talk to the target and set things up */
1683 int arm11_examine(struct target_s
*target
)
1687 arm11_common_t
* arm11
= target
->arch_info
;
1691 arm11_add_IR(arm11
, ARM11_IDCODE
, ARM11_TAP_DEFAULT
);
1693 scan_field_t idcode_field
;
1695 arm11_setup_field(arm11
, 32, NULL
, &arm11
->device_id
, &idcode_field
);
1697 arm11_add_dr_scan_vc(1, &idcode_field
, TAP_DRPAUSE
);
1701 arm11_add_debug_SCAN_N(arm11
, 0x00, ARM11_TAP_DEFAULT
);
1703 arm11_add_IR(arm11
, ARM11_INTEST
, ARM11_TAP_DEFAULT
);
1705 scan_field_t chain0_fields
[2];
1707 arm11_setup_field(arm11
, 32, NULL
, &arm11
->didr
, chain0_fields
+ 0);
1708 arm11_setup_field(arm11
, 8, NULL
, &arm11
->implementor
, chain0_fields
+ 1);
1710 arm11_add_dr_scan_vc(asizeof(chain0_fields
), chain0_fields
, TAP_IDLE
);
1712 CHECK_RETVAL(jtag_execute_queue());
1714 switch (arm11
->device_id
& 0x0FFFF000)
1716 case 0x07B36000: LOG_INFO("found ARM1136"); break;
1717 case 0x07B56000: LOG_INFO("found ARM1156"); break;
1718 case 0x07B76000: LOG_INFO("found ARM1176"); break;
1721 LOG_ERROR("'target arm11' expects IDCODE 0x*7B*7****");
1726 arm11
->debug_version
= (arm11
->didr
>> 16) & 0x0F;
1728 if (arm11
->debug_version
!= ARM11_DEBUG_V6
&&
1729 arm11
->debug_version
!= ARM11_DEBUG_V61
)
1731 LOG_ERROR("Only ARMv6 v6 and v6.1 architectures supported.");
1735 arm11
->brp
= ((arm11
->didr
>> 24) & 0x0F) + 1;
1736 arm11
->wrp
= ((arm11
->didr
>> 28) & 0x0F) + 1;
1738 /** \todo TODO: reserve one brp slot if we allow breakpoints during step */
1739 arm11
->free_brps
= arm11
->brp
;
1740 arm11
->free_wrps
= arm11
->wrp
;
1742 LOG_DEBUG("IDCODE %08" PRIx32
" IMPLEMENTOR %02x DIDR %08" PRIx32
"",
1744 (int)(arm11
->implementor
),
1747 /* as a side-effect this reads DSCR and thus
1748 * clears the ARM11_DSCR_STICKY_PRECISE_DATA_ABORT / Sticky Precise Data Abort Flag
1749 * as suggested by the spec.
1752 arm11_check_init(arm11
, NULL
);
1754 target_set_examined(target
);
1759 int arm11_quit(void)
1761 FNC_INFO_NOTIMPLEMENTED
;
1766 /** Load a register that is marked !valid in the register cache */
1767 int arm11_get_reg(reg_t
*reg
)
1771 target_t
* target
= ((arm11_reg_state_t
*)reg
->arch_info
)->target
;
1773 if (target
->state
!= TARGET_HALTED
)
1775 LOG_WARNING("target was not halted");
1776 return ERROR_TARGET_NOT_HALTED
;
1779 /** \todo TODO: Check this. We assume that all registers are fetched at debug entry. */
1782 arm11_common_t
*arm11
= target
->arch_info
;
1783 const arm11_reg_defs_t
* arm11_reg_info
= arm11_reg_defs
+ ((arm11_reg_state_t
*)reg
->arch_info
)->def_index
;
1789 /** Change a value in the register cache */
1790 int arm11_set_reg(reg_t
*reg
, uint8_t *buf
)
1794 target_t
* target
= ((arm11_reg_state_t
*)reg
->arch_info
)->target
;
1795 arm11_common_t
*arm11
= target
->arch_info
;
1796 // const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index;
1798 arm11
->reg_values
[((arm11_reg_state_t
*)reg
->arch_info
)->def_index
] = buf_get_u32(buf
, 0, 32);
1805 int arm11_build_reg_cache(target_t
*target
)
1807 arm11_common_t
*arm11
= target
->arch_info
;
1809 NEW(reg_cache_t
, cache
, 1);
1810 NEW(reg_t
, reg_list
, ARM11_REGCACHE_COUNT
);
1811 NEW(arm11_reg_state_t
, arm11_reg_states
, ARM11_REGCACHE_COUNT
);
1813 if (arm11_regs_arch_type
== -1)
1814 arm11_regs_arch_type
= register_reg_arch_type(arm11_get_reg
, arm11_set_reg
);
1816 register_init_dummy(&arm11_gdb_dummy_fp_reg
);
1817 register_init_dummy(&arm11_gdb_dummy_fps_reg
);
1819 arm11
->reg_list
= reg_list
;
1821 /* Build the process context cache */
1822 cache
->name
= "arm11 registers";
1824 cache
->reg_list
= reg_list
;
1825 cache
->num_regs
= ARM11_REGCACHE_COUNT
;
1827 reg_cache_t
**cache_p
= register_get_last_cache_p(&target
->reg_cache
);
1830 arm11
->core_cache
= cache
;
1831 // armv7m->process_context = cache;
1835 /* Not very elegant assertion */
1836 if (ARM11_REGCACHE_COUNT
!= asizeof(arm11
->reg_values
) ||
1837 ARM11_REGCACHE_COUNT
!= asizeof(arm11_reg_defs
) ||
1838 ARM11_REGCACHE_COUNT
!= ARM11_RC_MAX
)
1840 LOG_ERROR("BUG: arm11->reg_values inconsistent (%d " ZU
" " ZU
" %d)", ARM11_REGCACHE_COUNT
, asizeof(arm11
->reg_values
), asizeof(arm11_reg_defs
), ARM11_RC_MAX
);
1844 for (i
= 0; i
< ARM11_REGCACHE_COUNT
; i
++)
1846 reg_t
* r
= reg_list
+ i
;
1847 const arm11_reg_defs_t
* rd
= arm11_reg_defs
+ i
;
1848 arm11_reg_state_t
* rs
= arm11_reg_states
+ i
;
1852 r
->value
= (uint8_t *)(arm11
->reg_values
+ i
);
1855 r
->bitfield_desc
= NULL
;
1856 r
->num_bitfields
= 0;
1857 r
->arch_type
= arm11_regs_arch_type
;
1861 rs
->target
= target
;
1867 int arm11_handle_bool(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, bool * var
, char * name
)
1871 LOG_INFO("%s is %s.", name
, *var
? "enabled" : "disabled");
1876 return ERROR_COMMAND_SYNTAX_ERROR
;
1881 case 'f': /* false */
1883 case 'd': /* disable */
1889 case 't': /* true */
1891 case 'e': /* enable */
1897 LOG_INFO("%s %s.", *var
? "Enabled" : "Disabled", name
);
1902 #define BOOL_WRAPPER(name, print_name) \
1903 int arm11_handle_bool_##name(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) \
1905 return arm11_handle_bool(cmd_ctx, cmd, args, argc, &arm11_config_##name, print_name); \
1908 #define RC_TOP(name, descr, more) \
1910 command_t * new_cmd = register_command(cmd_ctx, top_cmd, name, NULL, COMMAND_ANY, descr); \
1911 command_t * top_cmd = new_cmd; \
1915 #define RC_FINAL(name, descr, handler) \
1916 register_command(cmd_ctx, top_cmd, name, handler, COMMAND_ANY, descr);
1918 #define RC_FINAL_BOOL(name, descr, var) \
1919 register_command(cmd_ctx, top_cmd, name, arm11_handle_bool_##var, COMMAND_ANY, descr);
1921 BOOL_WRAPPER(memwrite_burst
, "memory write burst mode")
1922 BOOL_WRAPPER(memwrite_error_fatal
, "fatal error mode for memory writes")
1923 BOOL_WRAPPER(memrw_no_increment
, "\"no increment\" mode for memory transfers")
1924 BOOL_WRAPPER(step_irq_enable
, "IRQs while stepping")
1925 BOOL_WRAPPER(hardware_step
, "hardware single step")
1927 int arm11_handle_vcr(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1931 arm11_vcr
= strtoul(args
[0], NULL
, 0);
1935 return ERROR_COMMAND_SYNTAX_ERROR
;
1938 LOG_INFO("VCR 0x%08" PRIx32
"", arm11_vcr
);
1942 const uint32_t arm11_coproc_instruction_limits
[] =
1944 15, /* coprocessor */
1949 0xFFFFFFFF, /* value */
1952 const char arm11_mrc_syntax
[] = "Syntax: mrc <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2>. All parameters are numbers only.";
1953 const char arm11_mcr_syntax
[] = "Syntax: mcr <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2> <32bit value to write>. All parameters are numbers only.";
1955 arm11_common_t
* arm11_find_target(const char * arg
)
1960 tap
= jtag_tap_by_string(arg
);
1965 for (t
= all_targets
; t
; t
= t
->next
)
1970 /* if (t->type == arm11_target) */
1971 if (0 == strcmp(target_get_name(t
), "arm11"))
1972 return t
->arch_info
;
1978 int arm11_handle_mrc_mcr(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, bool read
)
1980 if (argc
!= (read
? 6 : 7))
1982 LOG_ERROR("Invalid number of arguments. %s", read
? arm11_mrc_syntax
: arm11_mcr_syntax
);
1986 arm11_common_t
* arm11
= arm11_find_target(args
[0]);
1990 LOG_ERROR("Parameter 1 is not a the JTAG chain position of an ARM11 device. %s",
1991 read
? arm11_mrc_syntax
: arm11_mcr_syntax
);
1996 if (arm11
->target
->state
!= TARGET_HALTED
)
1998 LOG_WARNING("target was not halted");
1999 return ERROR_TARGET_NOT_HALTED
;
2004 for (size_t i
= 0; i
< (read
? 5 : 6); i
++)
2006 values
[i
] = strtoul(args
[i
+ 1], NULL
, 0);
2008 if (values
[i
] > arm11_coproc_instruction_limits
[i
])
2010 LOG_ERROR("Parameter %ld out of bounds (%" PRId32
" max). %s",
2012 arm11_coproc_instruction_limits
[i
],
2013 read
? arm11_mrc_syntax
: arm11_mcr_syntax
);
2018 uint32_t instr
= 0xEE000010 |
2026 instr
|= 0x00100000;
2028 arm11_run_instr_data_prepare(arm11
);
2033 arm11_run_instr_data_from_core_via_r0(arm11
, instr
, &result
);
2035 LOG_INFO("MRC p%d, %d, R0, c%d, c%d, %d = 0x%08" PRIx32
" (%" PRId32
")",
2040 (int)(values
[4]), result
, result
);
2044 arm11_run_instr_data_to_core_via_r0(arm11
, instr
, values
[5]);
2046 LOG_INFO("MRC p%d, %d, R0 (#0x%08" PRIx32
"), c%d, c%d, %d",
2047 (int)(values
[0]), (int)(values
[1]),
2049 (int)(values
[2]), (int)(values
[3]), (int)(values
[4]));
2052 arm11_run_instr_data_finish(arm11
);
2058 int arm11_handle_mrc(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
2060 return arm11_handle_mrc_mcr(cmd_ctx
, cmd
, args
, argc
, true);
2063 int arm11_handle_mcr(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
2065 return arm11_handle_mrc_mcr(cmd_ctx
, cmd
, args
, argc
, false);
2068 int arm11_register_commands(struct command_context_s
*cmd_ctx
)
2072 command_t
* top_cmd
= NULL
;
2074 RC_TOP("arm11", "arm11 specific commands",
2076 RC_TOP("memwrite", "Control memory write transfer mode",
2078 RC_FINAL_BOOL("burst", "Enable/Disable non-standard but fast burst mode (default: enabled)",
2081 RC_FINAL_BOOL("error_fatal", "Terminate program if transfer error was found (default: enabled)",
2082 memwrite_error_fatal
)
2085 RC_FINAL_BOOL("no_increment", "Don't increment address on multi-read/-write (default: disabled)",
2088 RC_FINAL_BOOL("step_irq_enable", "Enable interrupts while stepping (default: disabled)",
2090 RC_FINAL_BOOL("hardware_step", "hardware single stepping. By default use simulate + breakpoint. This command is only here to check if simulate + breakpoint implementation is broken.",
2093 RC_FINAL("vcr", "Control (Interrupt) Vector Catch Register",
2096 RC_FINAL("mrc", "Read Coprocessor register",
2099 RC_FINAL("mcr", "Write Coprocessor register",
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