1 /***************************************************************************
2 * Copyright (C) 2008 digenius technology GmbH. *
5 * Copyright (C) 2008 Oyvind Harboe oyvind.harboe@zylin.com *
7 * Copyright (C) 2008 Georg Acher <acher@in.tum.de> *
9 * This program is free software; you can redistribute it and/or modify *
10 * it under the terms of the GNU General Public License as published by *
11 * the Free Software Foundation; either version 2 of the License, or *
12 * (at your option) any later version. *
14 * This program is distributed in the hope that it will be useful, *
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
17 * GNU General Public License for more details. *
19 * You should have received a copy of the GNU General Public License *
20 * along with this program; if not, write to the *
21 * Free Software Foundation, Inc., *
22 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
23 ***************************************************************************/
31 #include "arm_simulator.h"
32 #include "target_type.h"
36 #define _DEBUG_INSTRUCTION_EXECUTION_
40 #define FNC_INFO LOG_DEBUG("-")
46 #define FNC_INFO_NOTIMPLEMENTED do { LOG_DEBUG("NOT IMPLEMENTED"); /*exit(-1);*/ } while (0)
48 #define FNC_INFO_NOTIMPLEMENTED
51 static int arm11_on_enter_debug_state(arm11_common_t
* arm11
);
53 bool arm11_config_memwrite_burst
= true;
54 bool arm11_config_memwrite_error_fatal
= true;
55 uint32_t arm11_vcr
= 0;
56 bool arm11_config_memrw_no_increment
= false;
57 bool arm11_config_step_irq_enable
= false;
59 #define ARM11_HANDLER(x) \
62 target_type_t arm11_target
=
67 ARM11_HANDLER(arch_state
),
69 ARM11_HANDLER(target_request_data
),
72 ARM11_HANDLER(resume
),
75 ARM11_HANDLER(assert_reset
),
76 ARM11_HANDLER(deassert_reset
),
77 ARM11_HANDLER(soft_reset_halt
),
79 ARM11_HANDLER(get_gdb_reg_list
),
81 ARM11_HANDLER(read_memory
),
82 ARM11_HANDLER(write_memory
),
84 ARM11_HANDLER(bulk_write_memory
),
86 ARM11_HANDLER(checksum_memory
),
88 ARM11_HANDLER(add_breakpoint
),
89 ARM11_HANDLER(remove_breakpoint
),
90 ARM11_HANDLER(add_watchpoint
),
91 ARM11_HANDLER(remove_watchpoint
),
93 ARM11_HANDLER(run_algorithm
),
95 ARM11_HANDLER(register_commands
),
96 ARM11_HANDLER(target_create
),
97 ARM11_HANDLER(init_target
),
98 ARM11_HANDLER(examine
),
102 int arm11_regs_arch_type
= -1;
120 ARM11_REGISTER_SPSR_FIQ
,
121 ARM11_REGISTER_SPSR_SVC
,
122 ARM11_REGISTER_SPSR_ABT
,
123 ARM11_REGISTER_SPSR_IRQ
,
124 ARM11_REGISTER_SPSR_UND
,
125 ARM11_REGISTER_SPSR_MON
,
134 typedef struct arm11_reg_defs_s
139 enum arm11_regtype type
;
142 /* update arm11_regcache_ids when changing this */
143 static const arm11_reg_defs_t arm11_reg_defs
[] =
145 {"r0", 0, 0, ARM11_REGISTER_CORE
},
146 {"r1", 1, 1, ARM11_REGISTER_CORE
},
147 {"r2", 2, 2, ARM11_REGISTER_CORE
},
148 {"r3", 3, 3, ARM11_REGISTER_CORE
},
149 {"r4", 4, 4, ARM11_REGISTER_CORE
},
150 {"r5", 5, 5, ARM11_REGISTER_CORE
},
151 {"r6", 6, 6, ARM11_REGISTER_CORE
},
152 {"r7", 7, 7, ARM11_REGISTER_CORE
},
153 {"r8", 8, 8, ARM11_REGISTER_CORE
},
154 {"r9", 9, 9, ARM11_REGISTER_CORE
},
155 {"r10", 10, 10, ARM11_REGISTER_CORE
},
156 {"r11", 11, 11, ARM11_REGISTER_CORE
},
157 {"r12", 12, 12, ARM11_REGISTER_CORE
},
158 {"sp", 13, 13, ARM11_REGISTER_CORE
},
159 {"lr", 14, 14, ARM11_REGISTER_CORE
},
160 {"pc", 15, 15, ARM11_REGISTER_CORE
},
162 #if ARM11_REGCACHE_FREGS
163 {"f0", 0, 16, ARM11_REGISTER_FX
},
164 {"f1", 1, 17, ARM11_REGISTER_FX
},
165 {"f2", 2, 18, ARM11_REGISTER_FX
},
166 {"f3", 3, 19, ARM11_REGISTER_FX
},
167 {"f4", 4, 20, ARM11_REGISTER_FX
},
168 {"f5", 5, 21, ARM11_REGISTER_FX
},
169 {"f6", 6, 22, ARM11_REGISTER_FX
},
170 {"f7", 7, 23, ARM11_REGISTER_FX
},
171 {"fps", 0, 24, ARM11_REGISTER_FPS
},
174 {"cpsr", 0, 25, ARM11_REGISTER_CPSR
},
176 #if ARM11_REGCACHE_MODEREGS
177 {"r8_fiq", 8, -1, ARM11_REGISTER_FIQ
},
178 {"r9_fiq", 9, -1, ARM11_REGISTER_FIQ
},
179 {"r10_fiq", 10, -1, ARM11_REGISTER_FIQ
},
180 {"r11_fiq", 11, -1, ARM11_REGISTER_FIQ
},
181 {"r12_fiq", 12, -1, ARM11_REGISTER_FIQ
},
182 {"r13_fiq", 13, -1, ARM11_REGISTER_FIQ
},
183 {"r14_fiq", 14, -1, ARM11_REGISTER_FIQ
},
184 {"spsr_fiq", 0, -1, ARM11_REGISTER_SPSR_FIQ
},
186 {"r13_svc", 13, -1, ARM11_REGISTER_SVC
},
187 {"r14_svc", 14, -1, ARM11_REGISTER_SVC
},
188 {"spsr_svc", 0, -1, ARM11_REGISTER_SPSR_SVC
},
190 {"r13_abt", 13, -1, ARM11_REGISTER_ABT
},
191 {"r14_abt", 14, -1, ARM11_REGISTER_ABT
},
192 {"spsr_abt", 0, -1, ARM11_REGISTER_SPSR_ABT
},
194 {"r13_irq", 13, -1, ARM11_REGISTER_IRQ
},
195 {"r14_irq", 14, -1, ARM11_REGISTER_IRQ
},
196 {"spsr_irq", 0, -1, ARM11_REGISTER_SPSR_IRQ
},
198 {"r13_und", 13, -1, ARM11_REGISTER_UND
},
199 {"r14_und", 14, -1, ARM11_REGISTER_UND
},
200 {"spsr_und", 0, -1, ARM11_REGISTER_SPSR_UND
},
203 {"r13_mon", 13, -1, ARM11_REGISTER_MON
},
204 {"r14_mon", 14, -1, ARM11_REGISTER_MON
},
205 {"spsr_mon", 0, -1, ARM11_REGISTER_SPSR_MON
},
208 /* Debug Registers */
209 {"dscr", 0, -1, ARM11_REGISTER_DSCR
},
210 {"wdtr", 0, -1, ARM11_REGISTER_WDTR
},
211 {"rdtr", 0, -1, ARM11_REGISTER_RDTR
},
214 enum arm11_regcache_ids
217 ARM11_RC_RX
= ARM11_RC_R0
,
232 ARM11_RC_SP
= ARM11_RC_R13
,
234 ARM11_RC_LR
= ARM11_RC_R14
,
236 ARM11_RC_PC
= ARM11_RC_R15
,
238 #if ARM11_REGCACHE_FREGS
240 ARM11_RC_FX
= ARM11_RC_F0
,
253 #if ARM11_REGCACHE_MODEREGS
291 #define ARM11_GDB_REGISTER_COUNT 26
293 uint8_t arm11_gdb_dummy_fp_value
[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
295 reg_t arm11_gdb_dummy_fp_reg
=
297 "GDB dummy floating-point register", arm11_gdb_dummy_fp_value
, 0, 1, 96, NULL
, 0, NULL
, 0
300 uint8_t arm11_gdb_dummy_fps_value
[] = {0, 0, 0, 0};
302 reg_t arm11_gdb_dummy_fps_reg
=
304 "GDB dummy floating-point status register", arm11_gdb_dummy_fps_value
, 0, 1, 32, NULL
, 0, NULL
, 0
309 /** Check and if necessary take control of the system
311 * \param arm11 Target state variable.
312 * \param dscr If the current DSCR content is
313 * available a pointer to a word holding the
314 * DSCR can be passed. Otherwise use NULL.
316 int arm11_check_init(arm11_common_t
* arm11
, uint32_t * dscr
)
320 uint32_t dscr_local_tmp_copy
;
324 dscr
= &dscr_local_tmp_copy
;
326 CHECK_RETVAL(arm11_read_DSCR(arm11
, dscr
));
329 if (!(*dscr
& ARM11_DSCR_MODE_SELECT
))
331 LOG_DEBUG("Bringing target into debug mode");
333 *dscr
|= ARM11_DSCR_MODE_SELECT
; /* Halt debug-mode */
334 arm11_write_DSCR(arm11
, *dscr
);
336 /* add further reset initialization here */
338 arm11
->simulate_reset_on_next_halt
= true;
340 if (*dscr
& ARM11_DSCR_CORE_HALTED
)
342 /** \todo TODO: this needs further scrutiny because
343 * arm11_on_enter_debug_state() never gets properly called.
344 * As a result we don't read the actual register states from
348 arm11
->target
->state
= TARGET_HALTED
;
349 arm11
->target
->debug_reason
= arm11_get_DSCR_debug_reason(*dscr
);
353 arm11
->target
->state
= TARGET_RUNNING
;
354 arm11
->target
->debug_reason
= DBG_REASON_NOTHALTED
;
357 arm11_sc7_clear_vbw(arm11
);
366 (arm11->reg_values[ARM11_RC_##x])
368 /** Save processor state.
370 * This is called when the HALT instruction has succeeded
371 * or on other occasions that stop the processor.
374 static int arm11_on_enter_debug_state(arm11_common_t
* arm11
)
378 for (size_t i
= 0; i
< asizeof(arm11
->reg_values
); i
++)
380 arm11
->reg_list
[i
].valid
= 1;
381 arm11
->reg_list
[i
].dirty
= 0;
385 CHECK_RETVAL(arm11_read_DSCR(arm11
, &R(DSCR
)));
389 if (R(DSCR
) & ARM11_DSCR_WDTR_FULL
)
391 arm11_add_debug_SCAN_N(arm11
, 0x05, ARM11_TAP_DEFAULT
);
393 arm11_add_IR(arm11
, ARM11_INTEST
, ARM11_TAP_DEFAULT
);
395 scan_field_t chain5_fields
[3];
397 arm11_setup_field(arm11
, 32, NULL
, &R(WDTR
), chain5_fields
+ 0);
398 arm11_setup_field(arm11
, 1, NULL
, NULL
, chain5_fields
+ 1);
399 arm11_setup_field(arm11
, 1, NULL
, NULL
, chain5_fields
+ 2);
401 arm11_add_dr_scan_vc(asizeof(chain5_fields
), chain5_fields
, TAP_DRPAUSE
);
405 arm11
->reg_list
[ARM11_RC_WDTR
].valid
= 0;
409 /* DSCR: set ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE */
410 /* ARM1176 spec says this is needed only for wDTR/rDTR's "ITR mode", but not to issue ITRs
411 ARM1136 seems to require this to issue ITR's as well */
413 uint32_t new_dscr
= R(DSCR
) | ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE
;
415 /* this executes JTAG queue: */
417 arm11_write_DSCR(arm11
, new_dscr
);
421 Before executing any instruction in debug state you have to drain the write buffer.
422 This ensures that no imprecise Data Aborts can return at a later point:*/
424 /** \todo TODO: Test drain write buffer. */
429 /* MRC p14,0,R0,c5,c10,0 */
430 // arm11_run_instr_no_data1(arm11, /*0xee150e1a*/0xe320f000);
432 /* mcr 15, 0, r0, cr7, cr10, {4} */
433 arm11_run_instr_no_data1(arm11
, 0xee070f9a);
435 uint32_t dscr
= arm11_read_DSCR(arm11
);
437 LOG_DEBUG("DRAIN, DSCR %08x", dscr
);
439 if (dscr
& ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT
)
441 arm11_run_instr_no_data1(arm11
, 0xe320f000);
443 dscr
= arm11_read_DSCR(arm11
);
445 LOG_DEBUG("DRAIN, DSCR %08x (DONE)", dscr
);
452 arm11_run_instr_data_prepare(arm11
);
456 /** \todo TODO: handle other mode registers */
458 for (size_t i
= 0; i
< 15; i
++)
460 /* MCR p14,0,R?,c0,c5,0 */
461 arm11_run_instr_data_from_core(arm11
, 0xEE000E15 | (i
<< 12), &R(RX
+ i
), 1);
466 /* check rDTRfull in DSCR */
468 if (R(DSCR
) & ARM11_DSCR_RDTR_FULL
)
470 /* MRC p14,0,R0,c0,c5,0 (move rDTR -> r0 (-> wDTR -> local var)) */
471 arm11_run_instr_data_from_core_via_r0(arm11
, 0xEE100E15, &R(RDTR
));
475 arm11
->reg_list
[ARM11_RC_RDTR
].valid
= 0;
480 /* MRS r0,CPSR (move CPSR -> r0 (-> wDTR -> local var)) */
481 arm11_run_instr_data_from_core_via_r0(arm11
, 0xE10F0000, &R(CPSR
));
485 /* MOV R0,PC (move PC -> r0 (-> wDTR -> local var)) */
486 arm11_run_instr_data_from_core_via_r0(arm11
, 0xE1A0000F, &R(PC
));
488 /* adjust PC depending on ARM state */
490 if (R(CPSR
) & ARM11_CPSR_J
) /* Java state */
492 arm11
->reg_values
[ARM11_RC_PC
] -= 0;
494 else if (R(CPSR
) & ARM11_CPSR_T
) /* Thumb state */
496 arm11
->reg_values
[ARM11_RC_PC
] -= 4;
500 arm11
->reg_values
[ARM11_RC_PC
] -= 8;
503 if (arm11
->simulate_reset_on_next_halt
)
505 arm11
->simulate_reset_on_next_halt
= false;
507 LOG_DEBUG("Reset c1 Control Register");
509 /* Write 0 (reset value) to Control register 0 to disable MMU/Cache etc. */
511 /* MCR p15,0,R0,c1,c0,0 */
512 arm11_run_instr_data_to_core_via_r0(arm11
, 0xee010f10, 0);
516 arm11_run_instr_data_finish(arm11
);
518 arm11_dump_reg_changes(arm11
);
523 void arm11_dump_reg_changes(arm11_common_t
* arm11
)
526 if (!(debug_level
>= LOG_LVL_DEBUG
))
531 for (size_t i
= 0; i
< ARM11_REGCACHE_COUNT
; i
++)
533 if (!arm11
->reg_list
[i
].valid
)
535 if (arm11
->reg_history
[i
].valid
)
536 LOG_DEBUG("%8s INVALID (%08" PRIx32
")", arm11_reg_defs
[i
].name
, arm11
->reg_history
[i
].value
);
540 if (arm11
->reg_history
[i
].valid
)
542 if (arm11
->reg_history
[i
].value
!= arm11
->reg_values
[i
])
543 LOG_DEBUG("%8s %08" PRIx32
" (%08" PRIx32
")", arm11_reg_defs
[i
].name
, arm11
->reg_values
[i
], arm11
->reg_history
[i
].value
);
547 LOG_DEBUG("%8s %08" PRIx32
" (INVALID)", arm11_reg_defs
[i
].name
, arm11
->reg_values
[i
]);
553 /** Restore processor state
555 * This is called in preparation for the RESTART function.
558 int arm11_leave_debug_state(arm11_common_t
* arm11
)
562 arm11_run_instr_data_prepare(arm11
);
564 /** \todo TODO: handle other mode registers */
566 /* restore R1 - R14 */
568 for (size_t i
= 1; i
< 15; i
++)
570 if (!arm11
->reg_list
[ARM11_RC_RX
+ i
].dirty
)
573 /* MRC p14,0,r?,c0,c5,0 */
574 arm11_run_instr_data_to_core1(arm11
, 0xee100e15 | (i
<< 12), R(RX
+ i
));
576 // LOG_DEBUG("RESTORE R" ZU " %08x", i, R(RX + i));
579 arm11_run_instr_data_finish(arm11
);
581 /* spec says clear wDTR and rDTR; we assume they are clear as
582 otherwise our programming would be sloppy */
586 CHECK_RETVAL(arm11_read_DSCR(arm11
, &DSCR
));
588 if (DSCR
& (ARM11_DSCR_RDTR_FULL
| ARM11_DSCR_WDTR_FULL
))
590 LOG_ERROR("wDTR/rDTR inconsistent (DSCR %08" PRIx32
")", DSCR
);
594 arm11_run_instr_data_prepare(arm11
);
596 /* restore original wDTR */
598 if ((R(DSCR
) & ARM11_DSCR_WDTR_FULL
) || arm11
->reg_list
[ARM11_RC_WDTR
].dirty
)
600 /* MCR p14,0,R0,c0,c5,0 */
601 arm11_run_instr_data_to_core_via_r0(arm11
, 0xee000e15, R(WDTR
));
607 arm11_run_instr_data_to_core_via_r0(arm11
, 0xe129f000, R(CPSR
));
612 arm11_run_instr_data_to_core_via_r0(arm11
, 0xe1a0f000, R(PC
));
616 /* MRC p14,0,r0,c0,c5,0 */
617 arm11_run_instr_data_to_core1(arm11
, 0xee100e15, R(R0
));
619 arm11_run_instr_data_finish(arm11
);
623 arm11_write_DSCR(arm11
, R(DSCR
));
627 if (R(DSCR
) & ARM11_DSCR_RDTR_FULL
|| arm11
->reg_list
[ARM11_RC_RDTR
].dirty
)
629 arm11_add_debug_SCAN_N(arm11
, 0x05, ARM11_TAP_DEFAULT
);
631 arm11_add_IR(arm11
, ARM11_EXTEST
, ARM11_TAP_DEFAULT
);
633 scan_field_t chain5_fields
[3];
635 uint8_t Ready
= 0; /* ignored */
636 uint8_t Valid
= 0; /* ignored */
638 arm11_setup_field(arm11
, 32, &R(RDTR
), NULL
, chain5_fields
+ 0);
639 arm11_setup_field(arm11
, 1, &Ready
, NULL
, chain5_fields
+ 1);
640 arm11_setup_field(arm11
, 1, &Valid
, NULL
, chain5_fields
+ 2);
642 arm11_add_dr_scan_vc(asizeof(chain5_fields
), chain5_fields
, TAP_DRPAUSE
);
645 arm11_record_register_history(arm11
);
650 void arm11_record_register_history(arm11_common_t
* arm11
)
652 for (size_t i
= 0; i
< ARM11_REGCACHE_COUNT
; i
++)
654 arm11
->reg_history
[i
].value
= arm11
->reg_values
[i
];
655 arm11
->reg_history
[i
].valid
= arm11
->reg_list
[i
].valid
;
657 arm11
->reg_list
[i
].valid
= 0;
658 arm11
->reg_list
[i
].dirty
= 0;
663 /* poll current target status */
664 int arm11_poll(struct target_s
*target
)
668 arm11_common_t
* arm11
= target
->arch_info
;
670 if (arm11
->trst_active
)
675 CHECK_RETVAL(arm11_read_DSCR(arm11
, &dscr
));
677 LOG_DEBUG("DSCR %08" PRIx32
"", dscr
);
679 CHECK_RETVAL(arm11_check_init(arm11
, &dscr
));
681 if (dscr
& ARM11_DSCR_CORE_HALTED
)
683 if (target
->state
!= TARGET_HALTED
)
685 enum target_state old_state
= target
->state
;
687 LOG_DEBUG("enter TARGET_HALTED");
688 target
->state
= TARGET_HALTED
;
689 target
->debug_reason
= arm11_get_DSCR_debug_reason(dscr
);
690 arm11_on_enter_debug_state(arm11
);
692 target_call_event_callbacks(target
,
693 old_state
== TARGET_DEBUG_RUNNING
? TARGET_EVENT_DEBUG_HALTED
: TARGET_EVENT_HALTED
);
698 if (target
->state
!= TARGET_RUNNING
&& target
->state
!= TARGET_DEBUG_RUNNING
)
700 LOG_DEBUG("enter TARGET_RUNNING");
701 target
->state
= TARGET_RUNNING
;
702 target
->debug_reason
= DBG_REASON_NOTHALTED
;
708 /* architecture specific status reply */
709 int arm11_arch_state(struct target_s
*target
)
711 arm11_common_t
* arm11
= target
->arch_info
;
713 LOG_USER("target halted due to %s\ncpsr: 0x%8.8" PRIx32
" pc: 0x%8.8" PRIx32
"",
714 Jim_Nvp_value2name_simple(nvp_target_debug_reason
, target
->debug_reason
)->name
,
721 /* target request support */
722 int arm11_target_request_data(struct target_s
*target
, uint32_t size
, uint8_t *buffer
)
724 FNC_INFO_NOTIMPLEMENTED
;
729 /* target execution control */
730 int arm11_halt(struct target_s
*target
)
734 arm11_common_t
* arm11
= target
->arch_info
;
736 LOG_DEBUG("target->state: %s",
737 target_state_name(target
));
739 if (target
->state
== TARGET_UNKNOWN
)
741 arm11
->simulate_reset_on_next_halt
= true;
744 if (target
->state
== TARGET_HALTED
)
746 LOG_DEBUG("target was already halted");
750 if (arm11
->trst_active
)
752 arm11
->halt_requested
= true;
756 arm11_add_IR(arm11
, ARM11_HALT
, TAP_IDLE
);
758 CHECK_RETVAL(jtag_execute_queue());
764 CHECK_RETVAL(arm11_read_DSCR(arm11
, &dscr
));
766 if (dscr
& ARM11_DSCR_CORE_HALTED
)
770 arm11_on_enter_debug_state(arm11
);
772 enum target_state old_state
= target
->state
;
774 target
->state
= TARGET_HALTED
;
775 target
->debug_reason
= arm11_get_DSCR_debug_reason(dscr
);
778 target_call_event_callbacks(target
,
779 old_state
== TARGET_DEBUG_RUNNING
? TARGET_EVENT_DEBUG_HALTED
: TARGET_EVENT_HALTED
));
784 int arm11_resume(struct target_s
*target
, int current
, uint32_t address
, int handle_breakpoints
, int debug_execution
)
788 // LOG_DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d",
789 // current, address, handle_breakpoints, debug_execution);
791 arm11_common_t
* arm11
= target
->arch_info
;
793 LOG_DEBUG("target->state: %s",
794 target_state_name(target
));
797 if (target
->state
!= TARGET_HALTED
)
799 LOG_ERROR("Target not halted");
800 return ERROR_TARGET_NOT_HALTED
;
806 LOG_DEBUG("RESUME PC %08" PRIx32
"%s", R(PC
), !current
? "!" : "");
808 /* clear breakpoints/watchpoints and VCR*/
809 arm11_sc7_clear_vbw(arm11
);
811 /* Set up breakpoints */
812 if (!debug_execution
)
814 /* check if one matches PC and step over it if necessary */
818 for (bp
= target
->breakpoints
; bp
; bp
= bp
->next
)
820 if (bp
->address
== R(PC
))
822 LOG_DEBUG("must step over %08" PRIx32
"", bp
->address
);
823 arm11_step(target
, 1, 0, 0);
828 /* set all breakpoints */
832 for (bp
= target
->breakpoints
; bp
; bp
= bp
->next
)
834 arm11_sc7_action_t brp
[2];
837 brp
[0].address
= ARM11_SC7_BVR0
+ brp_num
;
838 brp
[0].value
= bp
->address
;
840 brp
[1].address
= ARM11_SC7_BCR0
+ brp_num
;
841 brp
[1].value
= 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
843 arm11_sc7_run(arm11
, brp
, asizeof(brp
));
845 LOG_DEBUG("Add BP " ZU
" at %08" PRIx32
"", brp_num
, bp
->address
);
850 arm11_sc7_set_vcr(arm11
, arm11_vcr
);
853 arm11_leave_debug_state(arm11
);
855 arm11_add_IR(arm11
, ARM11_RESTART
, TAP_IDLE
);
857 CHECK_RETVAL(jtag_execute_queue());
863 CHECK_RETVAL(arm11_read_DSCR(arm11
, &dscr
));
865 LOG_DEBUG("DSCR %08" PRIx32
"", dscr
);
867 if (dscr
& ARM11_DSCR_CORE_RESTARTED
)
871 if (!debug_execution
)
873 target
->state
= TARGET_RUNNING
;
874 target
->debug_reason
= DBG_REASON_NOTHALTED
;
876 CHECK_RETVAL(target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
));
880 target
->state
= TARGET_DEBUG_RUNNING
;
881 target
->debug_reason
= DBG_REASON_NOTHALTED
;
883 CHECK_RETVAL(target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
));
890 static int armv4_5_to_arm11(int reg
)
897 return ARM11_RC_CPSR
;
899 /* FIX!!! handle thumb better! */
900 return ARM11_RC_CPSR
;
902 LOG_ERROR("BUG: register translation from armv4_5 to arm11 not supported %d", reg
);
908 static uint32_t arm11_sim_get_reg(struct arm_sim_interface
*sim
, int reg
)
910 arm11_common_t
* arm11
= (arm11_common_t
*)sim
->user_data
;
912 reg
=armv4_5_to_arm11(reg
);
914 return buf_get_u32(arm11
->reg_list
[reg
].value
, 0, 32);
917 static void arm11_sim_set_reg(struct arm_sim_interface
*sim
, int reg
, uint32_t value
)
919 arm11_common_t
* arm11
= (arm11_common_t
*)sim
->user_data
;
921 reg
=armv4_5_to_arm11(reg
);
923 buf_set_u32(arm11
->reg_list
[reg
].value
, 0, 32, value
);
926 static uint32_t arm11_sim_get_cpsr(struct arm_sim_interface
*sim
, int pos
, int bits
)
928 arm11_common_t
* arm11
= (arm11_common_t
*)sim
->user_data
;
930 return buf_get_u32(arm11
->reg_list
[ARM11_RC_CPSR
].value
, pos
, bits
);
933 static enum armv4_5_state
arm11_sim_get_state(struct arm_sim_interface
*sim
)
935 // arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
937 /* FIX!!!! we should implement thumb for arm11 */
938 return ARMV4_5_STATE_ARM
;
941 static void arm11_sim_set_state(struct arm_sim_interface
*sim
, enum armv4_5_state mode
)
943 // arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
945 /* FIX!!!! we should implement thumb for arm11 */
946 LOG_ERROR("Not implemetned!");
950 static enum armv4_5_mode
arm11_sim_get_mode(struct arm_sim_interface
*sim
)
952 //arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
954 /* FIX!!!! we should implement something that returns the current mode here!!! */
955 return ARMV4_5_MODE_USR
;
958 static int arm11_simulate_step(target_t
*target
, uint32_t *dry_run_pc
)
960 struct arm_sim_interface sim
;
962 sim
.user_data
=target
->arch_info
;
963 sim
.get_reg
=&arm11_sim_get_reg
;
964 sim
.set_reg
=&arm11_sim_set_reg
;
965 sim
.get_reg_mode
=&arm11_sim_get_reg
;
966 sim
.set_reg_mode
=&arm11_sim_set_reg
;
967 sim
.get_cpsr
=&arm11_sim_get_cpsr
;
968 sim
.get_mode
=&arm11_sim_get_mode
;
969 sim
.get_state
=&arm11_sim_get_state
;
970 sim
.set_state
=&arm11_sim_set_state
;
972 return arm_simulate_step_core(target
, dry_run_pc
, &sim
);
976 int arm11_step(struct target_s
*target
, int current
, uint32_t address
, int handle_breakpoints
)
981 LOG_DEBUG("target->state: %s",
982 target_state_name(target
));
984 if (target
->state
!= TARGET_HALTED
)
986 LOG_WARNING("target was not halted");
987 return ERROR_TARGET_NOT_HALTED
;
990 arm11_common_t
* arm11
= target
->arch_info
;
995 LOG_DEBUG("STEP PC %08" PRIx32
"%s", R(PC
), !current
? "!" : "");
998 /* TODO: to implement single stepping on arm11 devices that can't
999 * do single stepping in hardware we need to calculate the next
1000 * pc and set up breakpoints accordingingly. */
1002 retval
= arm11_simulate_step(target
, &next_pc
);
1003 if (retval
!= ERROR_OK
)
1007 /** \todo TODO: Thumb not supported here */
1009 uint32_t next_instruction
;
1011 CHECK_RETVAL(arm11_read_memory_word(arm11
, R(PC
), &next_instruction
));
1013 /* skip over BKPT */
1014 if ((next_instruction
& 0xFFF00070) == 0xe1200070)
1017 arm11
->reg_list
[ARM11_RC_PC
].valid
= 1;
1018 arm11
->reg_list
[ARM11_RC_PC
].dirty
= 0;
1019 LOG_DEBUG("Skipping BKPT");
1021 /* skip over Wait for interrupt / Standby */
1022 /* mcr 15, 0, r?, cr7, cr0, {4} */
1023 else if ((next_instruction
& 0xFFFF0FFF) == 0xee070f90)
1026 arm11
->reg_list
[ARM11_RC_PC
].valid
= 1;
1027 arm11
->reg_list
[ARM11_RC_PC
].dirty
= 0;
1028 LOG_DEBUG("Skipping WFI");
1030 /* ignore B to self */
1031 else if ((next_instruction
& 0xFEFFFFFF) == 0xeafffffe)
1033 LOG_DEBUG("Not stepping jump to self");
1037 /** \todo TODO: check if break-/watchpoints make any sense at all in combination
1040 /** \todo TODO: check if disabling IRQs might be a good idea here. Alternatively
1041 * the VCR might be something worth looking into. */
1044 /* Set up breakpoint for stepping */
1046 arm11_sc7_action_t brp
[2];
1049 brp
[0].address
= ARM11_SC7_BVR0
;
1050 brp
[0].value
= R(PC
);
1052 brp
[1].address
= ARM11_SC7_BCR0
;
1053 brp
[1].value
= 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (2 << 21);
1055 CHECK_RETVAL(arm11_sc7_run(arm11
, brp
, asizeof(brp
)));
1060 if (arm11_config_step_irq_enable
)
1061 R(DSCR
) &= ~ARM11_DSCR_INTERRUPTS_DISABLE
; /* should be redundant */
1063 R(DSCR
) |= ARM11_DSCR_INTERRUPTS_DISABLE
;
1066 CHECK_RETVAL(arm11_leave_debug_state(arm11
));
1068 arm11_add_IR(arm11
, ARM11_RESTART
, TAP_IDLE
);
1070 CHECK_RETVAL(jtag_execute_queue());
1072 /** \todo TODO: add a timeout */
1080 CHECK_RETVAL(arm11_read_DSCR(arm11
, &dscr
));
1082 LOG_DEBUG("DSCR %08" PRIx32
"e", dscr
);
1084 if ((dscr
& (ARM11_DSCR_CORE_RESTARTED
| ARM11_DSCR_CORE_HALTED
)) ==
1085 (ARM11_DSCR_CORE_RESTARTED
| ARM11_DSCR_CORE_HALTED
))
1089 /* clear breakpoint */
1090 arm11_sc7_clear_vbw(arm11
);
1093 CHECK_RETVAL(arm11_on_enter_debug_state(arm11
));
1095 /* restore default state */
1096 R(DSCR
) &= ~ARM11_DSCR_INTERRUPTS_DISABLE
;
1100 // target->state = TARGET_HALTED;
1101 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
1103 CHECK_RETVAL(target_call_event_callbacks(target
, TARGET_EVENT_HALTED
));
1105 if (R(PC
) != next_pc
)
1107 LOG_WARNING("next pc != simulated address %08" PRIx32
"!=%08" PRIx32
, R(PC
), next_pc
);
1113 /* target reset control */
1114 int arm11_assert_reset(struct target_s
*target
)
1119 /* assert reset lines */
1120 /* resets only the DBGTAP, not the ARM */
1122 jtag_add_reset(1, 0);
1123 jtag_add_sleep(5000);
1125 arm11_common_t
* arm11
= target
->arch_info
;
1126 arm11
->trst_active
= true;
1129 if (target
->reset_halt
)
1131 CHECK_RETVAL(target_halt(target
));
1137 int arm11_deassert_reset(struct target_s
*target
)
1142 LOG_DEBUG("target->state: %s",
1143 target_state_name(target
));
1146 /* deassert reset lines */
1147 jtag_add_reset(0, 0);
1149 arm11_common_t
* arm11
= target
->arch_info
;
1150 arm11
->trst_active
= false;
1152 if (arm11
->halt_requested
)
1153 return arm11_halt(target
);
1159 int arm11_soft_reset_halt(struct target_s
*target
)
1161 FNC_INFO_NOTIMPLEMENTED
;
1166 /* target register access for gdb */
1167 int arm11_get_gdb_reg_list(struct target_s
*target
, struct reg_s
**reg_list
[], int *reg_list_size
)
1171 arm11_common_t
* arm11
= target
->arch_info
;
1173 *reg_list_size
= ARM11_GDB_REGISTER_COUNT
;
1174 *reg_list
= malloc(sizeof(reg_t
*) * ARM11_GDB_REGISTER_COUNT
);
1176 for (size_t i
= 16; i
< 24; i
++)
1178 (*reg_list
)[i
] = &arm11_gdb_dummy_fp_reg
;
1181 (*reg_list
)[24] = &arm11_gdb_dummy_fps_reg
;
1183 for (size_t i
= 0; i
< ARM11_REGCACHE_COUNT
; i
++)
1185 if (arm11_reg_defs
[i
].gdb_num
== -1)
1188 (*reg_list
)[arm11_reg_defs
[i
].gdb_num
] = arm11
->reg_list
+ i
;
1194 /* target memory access
1195 * size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
1196 * count: number of items of <size>
1198 int arm11_read_memory(struct target_s
*target
, uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
)
1200 /** \todo TODO: check if buffer cast to uint32_t* and uint16_t* might cause alignment problems */
1204 if (target
->state
!= TARGET_HALTED
)
1206 LOG_WARNING("target was not halted");
1207 return ERROR_TARGET_NOT_HALTED
;
1210 LOG_DEBUG("ADDR %08" PRIx32
" SIZE %08" PRIx32
" COUNT %08" PRIx32
"", address
, size
, count
);
1212 arm11_common_t
* arm11
= target
->arch_info
;
1214 arm11_run_instr_data_prepare(arm11
);
1216 /* MRC p14,0,r0,c0,c5,0 */
1217 arm11_run_instr_data_to_core1(arm11
, 0xee100e15, address
);
1222 /** \todo TODO: check if dirty is the right choice to force a rewrite on arm11_resume() */
1223 arm11
->reg_list
[ARM11_RC_R1
].dirty
= 1;
1225 for (size_t i
= 0; i
< count
; i
++)
1227 /* ldrb r1, [r0], #1 */
1229 arm11_run_instr_no_data1(arm11
,
1230 !arm11_config_memrw_no_increment
? 0xe4d01001 : 0xe5d01000);
1233 /* MCR p14,0,R1,c0,c5,0 */
1234 arm11_run_instr_data_from_core(arm11
, 0xEE001E15, &res
, 1);
1243 arm11
->reg_list
[ARM11_RC_R1
].dirty
= 1;
1245 for (size_t i
= 0; i
< count
; i
++)
1247 /* ldrh r1, [r0], #2 */
1248 arm11_run_instr_no_data1(arm11
,
1249 !arm11_config_memrw_no_increment
? 0xe0d010b2 : 0xe1d010b0);
1253 /* MCR p14,0,R1,c0,c5,0 */
1254 arm11_run_instr_data_from_core(arm11
, 0xEE001E15, &res
, 1);
1256 uint16_t svalue
= res
;
1257 memcpy(buffer
+ i
* sizeof(uint16_t), &svalue
, sizeof(uint16_t));
1265 uint32_t instr
= !arm11_config_memrw_no_increment
? 0xecb05e01 : 0xed905e00;
1266 /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
1267 uint32_t *words
= (uint32_t *)buffer
;
1269 /* LDC p14,c5,[R0],#4 */
1270 /* LDC p14,c5,[R0] */
1271 arm11_run_instr_data_from_core(arm11
, instr
, words
, count
);
1276 arm11_run_instr_data_finish(arm11
);
1281 int arm11_write_memory(struct target_s
*target
, uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
)
1285 if (target
->state
!= TARGET_HALTED
)
1287 LOG_WARNING("target was not halted");
1288 return ERROR_TARGET_NOT_HALTED
;
1291 LOG_DEBUG("ADDR %08" PRIx32
" SIZE %08" PRIx32
" COUNT %08" PRIx32
"", address
, size
, count
);
1293 arm11_common_t
* arm11
= target
->arch_info
;
1295 arm11_run_instr_data_prepare(arm11
);
1297 /* MRC p14,0,r0,c0,c5,0 */
1298 arm11_run_instr_data_to_core1(arm11
, 0xee100e15, address
);
1304 arm11
->reg_list
[ARM11_RC_R1
].dirty
= 1;
1306 for (size_t i
= 0; i
< count
; i
++)
1308 /* MRC p14,0,r1,c0,c5,0 */
1309 arm11_run_instr_data_to_core1(arm11
, 0xee101e15, *buffer
++);
1311 /* strb r1, [r0], #1 */
1313 arm11_run_instr_no_data1(arm11
,
1314 !arm11_config_memrw_no_increment
? 0xe4c01001 : 0xe5c01000);
1322 arm11
->reg_list
[ARM11_RC_R1
].dirty
= 1;
1324 for (size_t i
= 0; i
< count
; i
++)
1327 memcpy(&value
, buffer
+ i
* sizeof(uint16_t), sizeof(uint16_t));
1329 /* MRC p14,0,r1,c0,c5,0 */
1330 arm11_run_instr_data_to_core1(arm11
, 0xee101e15, value
);
1332 /* strh r1, [r0], #2 */
1334 arm11_run_instr_no_data1(arm11
,
1335 !arm11_config_memrw_no_increment
? 0xe0c010b2 : 0xe1c010b0);
1342 uint32_t instr
= !arm11_config_memrw_no_increment
? 0xeca05e01 : 0xed805e00;
1344 /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
1345 uint32_t *words
= (uint32_t*)buffer
;
1347 if (!arm11_config_memwrite_burst
)
1349 /* STC p14,c5,[R0],#4 */
1350 /* STC p14,c5,[R0]*/
1351 arm11_run_instr_data_to_core(arm11
, instr
, words
, count
);
1355 /* STC p14,c5,[R0],#4 */
1356 /* STC p14,c5,[R0]*/
1357 arm11_run_instr_data_to_core_noack(arm11
, instr
, words
, count
);
1365 /* r0 verification */
1366 if (!arm11_config_memrw_no_increment
)
1370 /* MCR p14,0,R0,c0,c5,0 */
1371 arm11_run_instr_data_from_core(arm11
, 0xEE000E15, &r0
, 1);
1373 if (address
+ size
* count
!= r0
)
1375 LOG_ERROR("Data transfer failed. (%d)", (int)((r0
- address
) - size
* count
));
1377 if (arm11_config_memwrite_burst
)
1378 LOG_ERROR("use 'arm11 memwrite burst disable' to disable fast burst mode");
1380 if (arm11_config_memwrite_error_fatal
)
1386 arm11_run_instr_data_finish(arm11
);
1392 /* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
1393 int arm11_bulk_write_memory(struct target_s
*target
, uint32_t address
, uint32_t count
, uint8_t *buffer
)
1397 if (target
->state
!= TARGET_HALTED
)
1399 LOG_WARNING("target was not halted");
1400 return ERROR_TARGET_NOT_HALTED
;
1403 return arm11_write_memory(target
, address
, 4, count
, buffer
);
1406 /* here we have nothing target specific to contribute, so we fail and then the
1407 * fallback code will read data from the target and calculate the CRC on the
1410 int arm11_checksum_memory(struct target_s
*target
, uint32_t address
, uint32_t count
, uint32_t* checksum
)
1415 /* target break-/watchpoint control
1416 * rw: 0 = write, 1 = read, 2 = access
1418 int arm11_add_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
)
1422 arm11_common_t
* arm11
= target
->arch_info
;
1425 if (breakpoint
->type
== BKPT_SOFT
)
1427 LOG_INFO("sw breakpoint requested, but software breakpoints not enabled");
1428 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1432 if (!arm11
->free_brps
)
1434 LOG_DEBUG("no breakpoint unit available for hardware breakpoint");
1435 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1438 if (breakpoint
->length
!= 4)
1440 LOG_DEBUG("only breakpoints of four bytes length supported");
1441 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1449 int arm11_remove_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
)
1453 arm11_common_t
* arm11
= target
->arch_info
;
1460 int arm11_add_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
)
1462 FNC_INFO_NOTIMPLEMENTED
;
1467 int arm11_remove_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
)
1469 FNC_INFO_NOTIMPLEMENTED
;
1474 // HACKHACKHACK - FIXME mode/state
1475 /* target algorithm support */
1476 int arm11_run_algorithm(struct target_s
*target
, int num_mem_params
, mem_param_t
*mem_params
,
1477 int num_reg_params
, reg_param_t
*reg_params
, uint32_t entry_point
, uint32_t exit_point
,
1478 int timeout_ms
, void *arch_info
)
1480 arm11_common_t
*arm11
= target
->arch_info
;
1481 // enum armv4_5_state core_state = arm11->core_state;
1482 // enum armv4_5_mode core_mode = arm11->core_mode;
1483 uint32_t context
[16];
1485 int exit_breakpoint_size
= 0;
1486 int retval
= ERROR_OK
;
1487 LOG_DEBUG("Running algorithm");
1490 if (target
->state
!= TARGET_HALTED
)
1492 LOG_WARNING("target not halted");
1493 return ERROR_TARGET_NOT_HALTED
;
1497 // if (armv4_5_mode_to_number(arm11->core_mode)==-1)
1498 // return ERROR_FAIL;
1501 for (size_t i
= 0; i
< 16; i
++)
1503 context
[i
] = buf_get_u32((uint8_t*)(&arm11
->reg_values
[i
]),0,32);
1504 LOG_DEBUG("Save %zi: 0x%" PRIx32
"",i
,context
[i
]);
1507 cpsr
= buf_get_u32((uint8_t*)(arm11
->reg_values
+ ARM11_RC_CPSR
),0,32);
1508 LOG_DEBUG("Save CPSR: 0x%" PRIx32
"", cpsr
);
1510 for (int i
= 0; i
< num_mem_params
; i
++)
1512 target_write_buffer(target
, mem_params
[i
].address
, mem_params
[i
].size
, mem_params
[i
].value
);
1515 // Set register parameters
1516 for (int i
= 0; i
< num_reg_params
; i
++)
1518 reg_t
*reg
= register_get_by_name(arm11
->core_cache
, reg_params
[i
].reg_name
, 0);
1521 LOG_ERROR("BUG: register '%s' not found", reg_params
[i
].reg_name
);
1525 if (reg
->size
!= reg_params
[i
].size
)
1527 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params
[i
].reg_name
);
1530 arm11_set_reg(reg
,reg_params
[i
].value
);
1531 // printf("%i: Set %s =%08x\n", i, reg_params[i].reg_name,val);
1534 exit_breakpoint_size
= 4;
1536 /* arm11->core_state = arm11_algorithm_info->core_state;
1537 if (arm11->core_state == ARMV4_5_STATE_ARM)
1538 exit_breakpoint_size = 4;
1539 else if (arm11->core_state == ARMV4_5_STATE_THUMB)
1540 exit_breakpoint_size = 2;
1543 LOG_ERROR("BUG: can't execute algorithms when not in ARM or Thumb state");
1549 /* arm11 at this point only supports ARM not THUMB mode
1550 however if this test needs to be reactivated the current state can be read back
1553 if (arm11_algorithm_info
->core_mode
!= ARMV4_5_MODE_ANY
)
1555 LOG_DEBUG("setting core_mode: 0x%2.2x", arm11_algorithm_info
->core_mode
);
1556 buf_set_u32(arm11
->reg_list
[ARM11_RC_CPSR
].value
, 0, 5, arm11_algorithm_info
->core_mode
);
1557 arm11
->reg_list
[ARM11_RC_CPSR
].dirty
= 1;
1558 arm11
->reg_list
[ARM11_RC_CPSR
].valid
= 1;
1562 if ((retval
= breakpoint_add(target
, exit_point
, exit_breakpoint_size
, BKPT_HARD
)) != ERROR_OK
)
1564 LOG_ERROR("can't add breakpoint to finish algorithm execution");
1565 retval
= ERROR_TARGET_FAILURE
;
1569 // no debug, otherwise breakpoint is not set
1570 CHECK_RETVAL(target_resume(target
, 0, entry_point
, 1, 0));
1572 CHECK_RETVAL(target_wait_state(target
, TARGET_HALTED
, timeout_ms
));
1574 if (target
->state
!= TARGET_HALTED
)
1576 CHECK_RETVAL(target_halt(target
));
1578 CHECK_RETVAL(target_wait_state(target
, TARGET_HALTED
, 500));
1580 retval
= ERROR_TARGET_TIMEOUT
;
1582 goto del_breakpoint
;
1585 if (buf_get_u32(arm11
->reg_list
[15].value
, 0, 32) != exit_point
)
1587 LOG_WARNING("target reentered debug state, but not at the desired exit point: 0x%4.4" PRIx32
"",
1588 buf_get_u32(arm11
->reg_list
[15].value
, 0, 32));
1589 retval
= ERROR_TARGET_TIMEOUT
;
1590 goto del_breakpoint
;
1593 for (int i
= 0; i
< num_mem_params
; i
++)
1595 if (mem_params
[i
].direction
!= PARAM_OUT
)
1596 target_read_buffer(target
, mem_params
[i
].address
, mem_params
[i
].size
, mem_params
[i
].value
);
1599 for (int i
= 0; i
< num_reg_params
; i
++)
1601 if (reg_params
[i
].direction
!= PARAM_OUT
)
1603 reg_t
*reg
= register_get_by_name(arm11
->core_cache
, reg_params
[i
].reg_name
, 0);
1606 LOG_ERROR("BUG: register '%s' not found", reg_params
[i
].reg_name
);
1610 if (reg
->size
!= reg_params
[i
].size
)
1612 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params
[i
].reg_name
);
1616 buf_set_u32(reg_params
[i
].value
, 0, 32, buf_get_u32(reg
->value
, 0, 32));
1621 breakpoint_remove(target
, exit_point
);
1625 for (size_t i
= 0; i
< 16; i
++)
1627 LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32
"",
1628 arm11
->reg_list
[i
].name
, context
[i
]);
1629 arm11_set_reg(&arm11
->reg_list
[i
], (uint8_t*)&context
[i
]);
1631 LOG_DEBUG("restoring CPSR with value 0x%8.8" PRIx32
"", cpsr
);
1632 arm11_set_reg(&arm11
->reg_list
[ARM11_RC_CPSR
], (uint8_t*)&cpsr
);
1634 // arm11->core_state = core_state;
1635 // arm11->core_mode = core_mode;
1640 int arm11_target_create(struct target_s
*target
, Jim_Interp
*interp
)
1644 NEW(arm11_common_t
, arm11
, 1);
1646 arm11
->target
= target
;
1648 if (target
->tap
== NULL
)
1651 if (target
->tap
->ir_length
!= 5)
1653 LOG_ERROR("'target arm11' expects IR LENGTH = 5");
1654 return ERROR_COMMAND_SYNTAX_ERROR
;
1657 target
->arch_info
= arm11
;
1662 int arm11_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
)
1664 /* Initialize anything we can set up without talking to the target */
1665 return arm11_build_reg_cache(target
);
1668 /* talk to the target and set things up */
1669 int arm11_examine(struct target_s
*target
)
1673 arm11_common_t
* arm11
= target
->arch_info
;
1677 arm11_add_IR(arm11
, ARM11_IDCODE
, ARM11_TAP_DEFAULT
);
1679 scan_field_t idcode_field
;
1681 arm11_setup_field(arm11
, 32, NULL
, &arm11
->device_id
, &idcode_field
);
1683 arm11_add_dr_scan_vc(1, &idcode_field
, TAP_DRPAUSE
);
1687 arm11_add_debug_SCAN_N(arm11
, 0x00, ARM11_TAP_DEFAULT
);
1689 arm11_add_IR(arm11
, ARM11_INTEST
, ARM11_TAP_DEFAULT
);
1691 scan_field_t chain0_fields
[2];
1693 arm11_setup_field(arm11
, 32, NULL
, &arm11
->didr
, chain0_fields
+ 0);
1694 arm11_setup_field(arm11
, 8, NULL
, &arm11
->implementor
, chain0_fields
+ 1);
1696 arm11_add_dr_scan_vc(asizeof(chain0_fields
), chain0_fields
, TAP_IDLE
);
1698 CHECK_RETVAL(jtag_execute_queue());
1700 switch (arm11
->device_id
& 0x0FFFF000)
1702 case 0x07B36000: LOG_INFO("found ARM1136"); break;
1703 case 0x07B56000: LOG_INFO("found ARM1156"); break;
1704 case 0x07B76000: LOG_INFO("found ARM1176"); break;
1707 LOG_ERROR("'target arm11' expects IDCODE 0x*7B*7****");
1712 arm11
->debug_version
= (arm11
->didr
>> 16) & 0x0F;
1714 if (arm11
->debug_version
!= ARM11_DEBUG_V6
&&
1715 arm11
->debug_version
!= ARM11_DEBUG_V61
)
1717 LOG_ERROR("Only ARMv6 v6 and v6.1 architectures supported.");
1721 arm11
->brp
= ((arm11
->didr
>> 24) & 0x0F) + 1;
1722 arm11
->wrp
= ((arm11
->didr
>> 28) & 0x0F) + 1;
1724 /** \todo TODO: reserve one brp slot if we allow breakpoints during step */
1725 arm11
->free_brps
= arm11
->brp
;
1726 arm11
->free_wrps
= arm11
->wrp
;
1728 LOG_DEBUG("IDCODE %08" PRIx32
" IMPLEMENTOR %02x DIDR %08" PRIx32
"",
1730 (int)(arm11
->implementor
),
1733 /* as a side-effect this reads DSCR and thus
1734 * clears the ARM11_DSCR_STICKY_PRECISE_DATA_ABORT / Sticky Precise Data Abort Flag
1735 * as suggested by the spec.
1738 arm11_check_init(arm11
, NULL
);
1740 target_set_examined(target
);
1745 int arm11_quit(void)
1747 FNC_INFO_NOTIMPLEMENTED
;
1752 /** Load a register that is marked !valid in the register cache */
1753 int arm11_get_reg(reg_t
*reg
)
1757 target_t
* target
= ((arm11_reg_state_t
*)reg
->arch_info
)->target
;
1759 if (target
->state
!= TARGET_HALTED
)
1761 LOG_WARNING("target was not halted");
1762 return ERROR_TARGET_NOT_HALTED
;
1765 /** \todo TODO: Check this. We assume that all registers are fetched at debug entry. */
1768 arm11_common_t
*arm11
= target
->arch_info
;
1769 const arm11_reg_defs_t
* arm11_reg_info
= arm11_reg_defs
+ ((arm11_reg_state_t
*)reg
->arch_info
)->def_index
;
1775 /** Change a value in the register cache */
1776 int arm11_set_reg(reg_t
*reg
, uint8_t *buf
)
1780 target_t
* target
= ((arm11_reg_state_t
*)reg
->arch_info
)->target
;
1781 arm11_common_t
*arm11
= target
->arch_info
;
1782 // const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index;
1784 arm11
->reg_values
[((arm11_reg_state_t
*)reg
->arch_info
)->def_index
] = buf_get_u32(buf
, 0, 32);
1791 int arm11_build_reg_cache(target_t
*target
)
1793 arm11_common_t
*arm11
= target
->arch_info
;
1795 NEW(reg_cache_t
, cache
, 1);
1796 NEW(reg_t
, reg_list
, ARM11_REGCACHE_COUNT
);
1797 NEW(arm11_reg_state_t
, arm11_reg_states
, ARM11_REGCACHE_COUNT
);
1799 if (arm11_regs_arch_type
== -1)
1800 arm11_regs_arch_type
= register_reg_arch_type(arm11_get_reg
, arm11_set_reg
);
1802 register_init_dummy(&arm11_gdb_dummy_fp_reg
);
1803 register_init_dummy(&arm11_gdb_dummy_fps_reg
);
1805 arm11
->reg_list
= reg_list
;
1807 /* Build the process context cache */
1808 cache
->name
= "arm11 registers";
1810 cache
->reg_list
= reg_list
;
1811 cache
->num_regs
= ARM11_REGCACHE_COUNT
;
1813 reg_cache_t
**cache_p
= register_get_last_cache_p(&target
->reg_cache
);
1816 arm11
->core_cache
= cache
;
1817 // armv7m->process_context = cache;
1821 /* Not very elegant assertion */
1822 if (ARM11_REGCACHE_COUNT
!= asizeof(arm11
->reg_values
) ||
1823 ARM11_REGCACHE_COUNT
!= asizeof(arm11_reg_defs
) ||
1824 ARM11_REGCACHE_COUNT
!= ARM11_RC_MAX
)
1826 LOG_ERROR("BUG: arm11->reg_values inconsistent (%d " ZU
" " ZU
" %d)", ARM11_REGCACHE_COUNT
, asizeof(arm11
->reg_values
), asizeof(arm11_reg_defs
), ARM11_RC_MAX
);
1830 for (i
= 0; i
< ARM11_REGCACHE_COUNT
; i
++)
1832 reg_t
* r
= reg_list
+ i
;
1833 const arm11_reg_defs_t
* rd
= arm11_reg_defs
+ i
;
1834 arm11_reg_state_t
* rs
= arm11_reg_states
+ i
;
1838 r
->value
= (uint8_t *)(arm11
->reg_values
+ i
);
1841 r
->bitfield_desc
= NULL
;
1842 r
->num_bitfields
= 0;
1843 r
->arch_type
= arm11_regs_arch_type
;
1847 rs
->target
= target
;
1853 int arm11_handle_bool(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, bool * var
, char * name
)
1857 LOG_INFO("%s is %s.", name
, *var
? "enabled" : "disabled");
1862 return ERROR_COMMAND_SYNTAX_ERROR
;
1867 case 'f': /* false */
1869 case 'd': /* disable */
1875 case 't': /* true */
1877 case 'e': /* enable */
1883 LOG_INFO("%s %s.", *var
? "Enabled" : "Disabled", name
);
1888 #define BOOL_WRAPPER(name, print_name) \
1889 int arm11_handle_bool_##name(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) \
1891 return arm11_handle_bool(cmd_ctx, cmd, args, argc, &arm11_config_##name, print_name); \
1894 #define RC_TOP(name, descr, more) \
1896 command_t * new_cmd = register_command(cmd_ctx, top_cmd, name, NULL, COMMAND_ANY, descr); \
1897 command_t * top_cmd = new_cmd; \
1901 #define RC_FINAL(name, descr, handler) \
1902 register_command(cmd_ctx, top_cmd, name, handler, COMMAND_ANY, descr);
1904 #define RC_FINAL_BOOL(name, descr, var) \
1905 register_command(cmd_ctx, top_cmd, name, arm11_handle_bool_##var, COMMAND_ANY, descr);
1907 BOOL_WRAPPER(memwrite_burst
, "memory write burst mode")
1908 BOOL_WRAPPER(memwrite_error_fatal
, "fatal error mode for memory writes")
1909 BOOL_WRAPPER(memrw_no_increment
, "\"no increment\" mode for memory transfers")
1910 BOOL_WRAPPER(step_irq_enable
, "IRQs while stepping")
1912 int arm11_handle_vcr(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1916 arm11_vcr
= strtoul(args
[0], NULL
, 0);
1920 return ERROR_COMMAND_SYNTAX_ERROR
;
1923 LOG_INFO("VCR 0x%08" PRIx32
"", arm11_vcr
);
1927 const uint32_t arm11_coproc_instruction_limits
[] =
1929 15, /* coprocessor */
1934 0xFFFFFFFF, /* value */
1937 const char arm11_mrc_syntax
[] = "Syntax: mrc <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2>. All parameters are numbers only.";
1938 const char arm11_mcr_syntax
[] = "Syntax: mcr <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2> <32bit value to write>. All parameters are numbers only.";
1940 arm11_common_t
* arm11_find_target(const char * arg
)
1945 tap
= jtag_tap_by_string(arg
);
1950 for (t
= all_targets
; t
; t
= t
->next
)
1955 /* if (t->type == arm11_target) */
1956 if (0 == strcmp(target_get_name(t
), "arm11"))
1957 return t
->arch_info
;
1963 int arm11_handle_mrc_mcr(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, bool read
)
1965 if (argc
!= (read
? 6 : 7))
1967 LOG_ERROR("Invalid number of arguments. %s", read
? arm11_mrc_syntax
: arm11_mcr_syntax
);
1971 arm11_common_t
* arm11
= arm11_find_target(args
[0]);
1975 LOG_ERROR("Parameter 1 is not a the JTAG chain position of an ARM11 device. %s",
1976 read
? arm11_mrc_syntax
: arm11_mcr_syntax
);
1981 if (arm11
->target
->state
!= TARGET_HALTED
)
1983 LOG_WARNING("target was not halted");
1984 return ERROR_TARGET_NOT_HALTED
;
1989 for (size_t i
= 0; i
< (read
? 5 : 6); i
++)
1991 values
[i
] = strtoul(args
[i
+ 1], NULL
, 0);
1993 if (values
[i
] > arm11_coproc_instruction_limits
[i
])
1995 LOG_ERROR("Parameter %ld out of bounds (%" PRId32
" max). %s",
1997 arm11_coproc_instruction_limits
[i
],
1998 read
? arm11_mrc_syntax
: arm11_mcr_syntax
);
2003 uint32_t instr
= 0xEE000010 |
2011 instr
|= 0x00100000;
2013 arm11_run_instr_data_prepare(arm11
);
2018 arm11_run_instr_data_from_core_via_r0(arm11
, instr
, &result
);
2020 LOG_INFO("MRC p%d, %d, R0, c%d, c%d, %d = 0x%08" PRIx32
" (%" PRId32
")",
2025 (int)(values
[4]), result
, result
);
2029 arm11_run_instr_data_to_core_via_r0(arm11
, instr
, values
[5]);
2031 LOG_INFO("MRC p%d, %d, R0 (#0x%08" PRIx32
"), c%d, c%d, %d",
2032 (int)(values
[0]), (int)(values
[1]),
2034 (int)(values
[2]), (int)(values
[3]), (int)(values
[4]));
2037 arm11_run_instr_data_finish(arm11
);
2043 int arm11_handle_mrc(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
2045 return arm11_handle_mrc_mcr(cmd_ctx
, cmd
, args
, argc
, true);
2048 int arm11_handle_mcr(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
2050 return arm11_handle_mrc_mcr(cmd_ctx
, cmd
, args
, argc
, false);
2053 int arm11_register_commands(struct command_context_s
*cmd_ctx
)
2057 command_t
* top_cmd
= NULL
;
2059 RC_TOP("arm11", "arm11 specific commands",
2061 RC_TOP("memwrite", "Control memory write transfer mode",
2063 RC_FINAL_BOOL("burst", "Enable/Disable non-standard but fast burst mode (default: enabled)",
2066 RC_FINAL_BOOL("error_fatal", "Terminate program if transfer error was found (default: enabled)",
2067 memwrite_error_fatal
)
2070 RC_FINAL_BOOL("no_increment", "Don't increment address on multi-read/-write (default: disabled)",
2073 RC_FINAL_BOOL("step_irq_enable", "Enable interrupts while stepping (default: disabled)",
2076 RC_FINAL("vcr", "Control (Interrupt) Vector Catch Register",
2079 RC_FINAL("mrc", "Read Coprocessor register",
2082 RC_FINAL("mcr", "Write Coprocessor register",
Linking to existing account procedure
If you already have an account and want to add another login method
you
MUST first sign in with your existing account and
then change URL to read
https://review.openocd.org/login/?link
to get to this page again but this time it'll work for linking. Thank you.
SSH host keys fingerprints
1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=.. |
|+o.. . |
|*.o . . |
|+B . . . |
|Bo. = o S |
|Oo.+ + = |
|oB=.* = . o |
| =+=.+ + E |
|. .=o . o |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)