src/target/arm.h

   1 /*
   2  * Copyright (C) 2005 by Dominic Rath
   3  * Dominic.Rath@gmx.de
   4  *
   5  * Copyright (C) 2008 by Spencer Oliver
   6  * spen@spen-soft.co.uk
   7  *
   8  * Copyright (C) 2009 by Øyvind Harboe
   9  * oyvind.harboe@zylin.com
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the
  23  * Free Software Foundation, Inc.,
  24  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  25  */
  26
  27 #ifndef ARM_H
  28 #define ARM_H
  29
  30 #include <helper/command.h>
  31 #include "target.h"
  32
  33
  34 /**
  35  * @file
  36  * Holds the interface to ARM cores.
  37  *
  38  * At this writing, only "classic ARM" cores built on the ARMv4 register
  39  * and mode model are supported.  The Thumb2-only microcontroller profile
  40  * support has not yet been integrated, affecting Cortex-M parts.
  41  */
  42
  43 /**
  44  * Represent state of an ARM core.
  45  *
  46  * Most numbers match the five low bits of the *PSR registers on
  47  * "classic ARM" processors, which build on the ARMv4 processor
  48  * modes and register set.
  49  *
  50  * ARM_MODE_ANY is a magic value, often used as a wildcard.
  51  *
  52  * Only the microcontroller cores (ARMv6-M, ARMv7-M) support ARM_MODE_THREAD,
  53  * ARM_MODE_USER_THREAD, and ARM_MODE_HANDLER.  Those are the only modes
  54  * they support.
  55  */
  56 enum arm_mode {
  57         ARM_MODE_USR = 16,
  58         ARM_MODE_FIQ = 17,
  59         ARM_MODE_IRQ = 18,
  60         ARM_MODE_SVC = 19,
  61         ARM_MODE_MON = 22,
  62         ARM_MODE_ABT = 23,
  63         ARM_MODE_UND = 27,
  64         ARM_MODE_1176_MON = 28,
  65         ARM_MODE_SYS = 31,
  66
  67         ARM_MODE_THREAD = 0,
  68         ARM_MODE_USER_THREAD = 1,
  69         ARM_MODE_HANDLER = 2,
  70
  71         ARM_MODE_ANY = -1
  72 };
  73
  74 const char *arm_mode_name(unsigned psr_mode);
  75 bool is_arm_mode(unsigned psr_mode);
  76
  77 /** The PSR "T" and "J" bits define the mode of "classic ARM" cores. */
  78 enum arm_state {
  79         ARM_STATE_ARM,
  80         ARM_STATE_THUMB,
  81         ARM_STATE_JAZELLE,
  82         ARM_STATE_THUMB_EE,
  83 };
  84
  85 #define ARM_COMMON_MAGIC 0x0A450A45
  86
  87 /**
  88  * Represents a generic ARM core, with standard application registers.
  89  *
  90  * There are sixteen application registers (including PC, SP, LR) and a PSR.
  91  * Cortex-M series cores do not support as many core states or shadowed
  92  * registers as traditional ARM cores, and only support Thumb2 instructions.
  93  */
  94 struct arm {
  95         int common_magic;
  96         struct reg_cache *core_cache;
  97
  98         /** Handle to the PC; valid in all core modes. */
  99         struct reg *pc;
 100
 101         /** Handle to the CPSR/xPSR; valid in all core modes. */
 102         struct reg *cpsr;
 103
 104         /** Handle to the SPSR; valid only in core modes with an SPSR. */
 105         struct reg *spsr;
 106
 107         /** Support for arm_reg_current() */
 108         const int *map;
 109
 110         /**
 111          * Indicates what registers are in the ARM state core register set.
 112          * ARM_MODE_ANY indicates the standard set of 37 registers,
 113          * seen on for example ARM7TDMI cores.  ARM_MODE_MON indicates three
 114          * more registers are shadowed, for "Secure Monitor" mode.
 115          * ARM_MODE_THREAD indicates a microcontroller profile core,
 116          * which only shadows SP.
 117          */
 118         enum arm_mode core_type;
 119
 120         /** Record the current core mode: SVC, USR, or some other mode. */
 121         enum arm_mode core_mode;
 122
 123         /** Record the current core state: ARM, Thumb, or otherwise. */
 124         enum arm_state core_state;
 125
 126         /** Flag reporting unavailability of the BKPT instruction. */
 127         bool is_armv4;
 128
 129         /** Flag reporting armv6m based core. */
 130         bool is_armv6m;
 131
 132         /** Flag reporting whether semihosting is active. */
 133         bool is_semihosting;
 134
 135         /** Value to be returned by semihosting SYS_ERRNO request. */
 136         int semihosting_errno;
 137
 138         int (*setup_semihosting)(struct target *target, int enable);
 139
 140         /** Backpointer to the target. */
 141         struct target *target;
 142
 143         /** Handle for the debug module, if one is present. */
 144         struct arm_dpm *dpm;
 145
 146         /** Handle for the Embedded Trace Module, if one is present. */
 147         struct etm_context *etm;
 148
 149         /* FIXME all these methods should take "struct arm *" not target */
 150
 151         /** Retrieve all core registers, for display. */
 152         int (*full_context)(struct target *target);
 153
 154         /** Retrieve a single core register. */
 155         int (*read_core_reg)(struct target *target, struct reg *reg,
 156                         int num, enum arm_mode mode);
 157         int (*write_core_reg)(struct target *target, struct reg *reg,
 158                         int num, enum arm_mode mode, uint8_t *value);
 159
 160         /** Read coprocessor register.  */
 161         int (*mrc)(struct target *target, int cpnum,
 162                         uint32_t op1, uint32_t op2,
 163                         uint32_t CRn, uint32_t CRm,
 164                         uint32_t *value);
 165
 166         /** Write coprocessor register.  */
 167         int (*mcr)(struct target *target, int cpnum,
 168                         uint32_t op1, uint32_t op2,
 169                         uint32_t CRn, uint32_t CRm,
 170                         uint32_t value);
 171
 172         void *arch_info;
 173
 174         /** For targets conforming to ARM Debug Interface v5,
 175          * this handle references the Debug Access Port (DAP)
 176          * used to make requests to the target.
 177          */
 178         struct adiv5_dap *dap;
 179 };
 180
 181 /** Convert target handle to generic ARM target state handle. */
 182 static inline struct arm *target_to_arm(struct target *target)
 183 {
 184         assert(target != NULL);
 185         return target->arch_info;
 186 }
 187
 188 static inline bool is_arm(struct arm *arm)
 189 {
 190         assert(arm != NULL);
 191         return arm->common_magic == ARM_COMMON_MAGIC;
 192 }
 193
 194 struct arm_algorithm {
 195         int common_magic;
 196
 197         enum arm_mode core_mode;
 198         enum arm_state core_state;
 199 };
 200
 201 struct arm_reg {
 202         int num;
 203         enum arm_mode mode;
 204         struct target *target;
 205         struct arm *arm;
 206         uint8_t value[4];
 207 };
 208
 209 struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm);
 210
 211 extern const struct command_registration arm_command_handlers[];
 212
 213 int arm_arch_state(struct target *target);
 214 int arm_get_gdb_reg_list(struct target *target,
 215                 struct reg **reg_list[], int *reg_list_size,
 216                 enum target_register_class reg_class);
 217
 218 int arm_init_arch_info(struct target *target, struct arm *arm);
 219
 220 /* REVISIT rename this once it's usable by ARMv7-M */
 221 int armv4_5_run_algorithm(struct target *target,
 222                 int num_mem_params, struct mem_param *mem_params,
 223                 int num_reg_params, struct reg_param *reg_params,
 224                 uint32_t entry_point, uint32_t exit_point,
 225                 int timeout_ms, void *arch_info);
 226 int armv4_5_run_algorithm_inner(struct target *target,
 227                 int num_mem_params, struct mem_param *mem_params,
 228                 int num_reg_params, struct reg_param *reg_params,
 229                 uint32_t entry_point, uint32_t exit_point,
 230                 int timeout_ms, void *arch_info,
 231                 int (*run_it)(struct target *target, uint32_t exit_point,
 232                                 int timeout_ms, void *arch_info));
 233
 234 int arm_checksum_memory(struct target *target,
 235                 uint32_t address, uint32_t count, uint32_t *checksum);
 236 int arm_blank_check_memory(struct target *target,
 237                 uint32_t address, uint32_t count, uint32_t *blank);
 238
 239 void arm_set_cpsr(struct arm *arm, uint32_t cpsr);
 240 struct reg *arm_reg_current(struct arm *arm, unsigned regnum);
 241
 242 extern struct reg arm_gdb_dummy_fp_reg;
 243 extern struct reg arm_gdb_dummy_fps_reg;
 244
 245 #endif /* ARM_H */