src/target/arm.h

   1 /*
   2  * Copyright (C) 2005 by Dominic Rath
   3  * Dominic.Rath@gmx.de
   4  *
   5  * Copyright (C) 2008 by Spencer Oliver
   6  * spen@spen-soft.co.uk
   7  *
   8  * Copyright (C) 2009 by Øyvind Harboe
   9  * oyvind.harboe@zylin.com
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  23  */
  24
  25 #ifndef ARM_H
  26 #define ARM_H
  27
  28 #include <helper/command.h>
  29 #include "target.h"
  30
  31
  32 /**
  33  * @file
  34  * Holds the interface to ARM cores.
  35  *
  36  * At this writing, only "classic ARM" cores built on the ARMv4 register
  37  * and mode model are supported.  The Thumb2-only microcontroller profile
  38  * support has not yet been integrated, affecting Cortex-M parts.
  39  */
  40
  41 /**
  42  * Represent state of an ARM core.
  43  *
  44  * Most numbers match the five low bits of the *PSR registers on
  45  * "classic ARM" processors, which build on the ARMv4 processor
  46  * modes and register set.
  47  *
  48  * ARM_MODE_ANY is a magic value, often used as a wildcard.
  49  *
  50  * Only the microcontroller cores (ARMv6-M, ARMv7-M) support ARM_MODE_THREAD,
  51  * ARM_MODE_USER_THREAD, and ARM_MODE_HANDLER.  Those are the only modes
  52  * they support.
  53  */
  54 enum arm_mode {
  55         ARM_MODE_USR = 16,
  56         ARM_MODE_FIQ = 17,
  57         ARM_MODE_IRQ = 18,
  58         ARM_MODE_SVC = 19,
  59         ARM_MODE_MON = 22,
  60         ARM_MODE_ABT = 23,
  61         ARM_MODE_UND = 27,
  62         ARM_MODE_1176_MON = 28,
  63         ARM_MODE_SYS = 31,
  64
  65         ARM_MODE_THREAD = 0,
  66         ARM_MODE_USER_THREAD = 1,
  67         ARM_MODE_HANDLER = 2,
  68
  69         ARM_MODE_ANY = -1
  70 };
  71
  72 const char *arm_mode_name(unsigned psr_mode);
  73 bool is_arm_mode(unsigned psr_mode);
  74
  75 /** The PSR "T" and "J" bits define the mode of "classic ARM" cores. */
  76 enum arm_state {
  77         ARM_STATE_ARM,
  78         ARM_STATE_THUMB,
  79         ARM_STATE_JAZELLE,
  80         ARM_STATE_THUMB_EE,
  81 };
  82
  83 #define ARM_COMMON_MAGIC 0x0A450A45
  84
  85 /**
  86  * Represents a generic ARM core, with standard application registers.
  87  *
  88  * There are sixteen application registers (including PC, SP, LR) and a PSR.
  89  * Cortex-M series cores do not support as many core states or shadowed
  90  * registers as traditional ARM cores, and only support Thumb2 instructions.
  91  */
  92 struct arm {
  93         int common_magic;
  94         struct reg_cache *core_cache;
  95
  96         /** Handle to the PC; valid in all core modes. */
  97         struct reg *pc;
  98
  99         /** Handle to the CPSR/xPSR; valid in all core modes. */
 100         struct reg *cpsr;
 101
 102         /** Handle to the SPSR; valid only in core modes with an SPSR. */
 103         struct reg *spsr;
 104
 105         /** Support for arm_reg_current() */
 106         const int *map;
 107
 108         /**
 109          * Indicates what registers are in the ARM state core register set.
 110          * ARM_MODE_ANY indicates the standard set of 37 registers,
 111          * seen on for example ARM7TDMI cores.  ARM_MODE_MON indicates three
 112          * more registers are shadowed, for "Secure Monitor" mode.
 113          * ARM_MODE_THREAD indicates a microcontroller profile core,
 114          * which only shadows SP.
 115          */
 116         enum arm_mode core_type;
 117
 118         /** Record the current core mode: SVC, USR, or some other mode. */
 119         enum arm_mode core_mode;
 120
 121         /** Record the current core state: ARM, Thumb, or otherwise. */
 122         enum arm_state core_state;
 123
 124         /** Flag reporting unavailability of the BKPT instruction. */
 125         bool is_armv4;
 126
 127         /** Flag reporting armv6m based core. */
 128         bool is_armv6m;
 129
 130         /** Flag reporting whether semihosting is active. */
 131         bool is_semihosting;
 132
 133         /** Value to be returned by semihosting SYS_ERRNO request. */
 134         int semihosting_errno;
 135
 136         int (*setup_semihosting)(struct target *target, int enable);
 137
 138         /** Backpointer to the target. */
 139         struct target *target;
 140
 141         /** Handle for the debug module, if one is present. */
 142         struct arm_dpm *dpm;
 143
 144         /** Handle for the Embedded Trace Module, if one is present. */
 145         struct etm_context *etm;
 146
 147         /* FIXME all these methods should take "struct arm *" not target */
 148
 149         /** Retrieve all core registers, for display. */
 150         int (*full_context)(struct target *target);
 151
 152         /** Retrieve a single core register. */
 153         int (*read_core_reg)(struct target *target, struct reg *reg,
 154                         int num, enum arm_mode mode);
 155         int (*write_core_reg)(struct target *target, struct reg *reg,
 156                         int num, enum arm_mode mode, uint8_t *value);
 157
 158         /** Read coprocessor register.  */
 159         int (*mrc)(struct target *target, int cpnum,
 160                         uint32_t op1, uint32_t op2,
 161                         uint32_t CRn, uint32_t CRm,
 162                         uint32_t *value);
 163
 164         /** Write coprocessor register.  */
 165         int (*mcr)(struct target *target, int cpnum,
 166                         uint32_t op1, uint32_t op2,
 167                         uint32_t CRn, uint32_t CRm,
 168                         uint32_t value);
 169
 170         void *arch_info;
 171
 172         /** For targets conforming to ARM Debug Interface v5,
 173          * this handle references the Debug Access Port (DAP)
 174          * used to make requests to the target.
 175          */
 176         struct adiv5_dap *dap;
 177 };
 178
 179 /** Convert target handle to generic ARM target state handle. */
 180 static inline struct arm *target_to_arm(struct target *target)
 181 {
 182         assert(target != NULL);
 183         return target->arch_info;
 184 }
 185
 186 static inline bool is_arm(struct arm *arm)
 187 {
 188         assert(arm != NULL);
 189         return arm->common_magic == ARM_COMMON_MAGIC;
 190 }
 191
 192 struct arm_algorithm {
 193         int common_magic;
 194
 195         enum arm_mode core_mode;
 196         enum arm_state core_state;
 197 };
 198
 199 struct arm_reg {
 200         int num;
 201         enum arm_mode mode;
 202         struct target *target;
 203         struct arm *arm;
 204         uint8_t value[4];
 205 };
 206
 207 struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm);
 208
 209 extern const struct command_registration arm_command_handlers[];
 210
 211 int arm_arch_state(struct target *target);
 212 int arm_get_gdb_reg_list(struct target *target,
 213                 struct reg **reg_list[], int *reg_list_size,
 214                 enum target_register_class reg_class);
 215
 216 int arm_init_arch_info(struct target *target, struct arm *arm);
 217
 218 /* REVISIT rename this once it's usable by ARMv7-M */
 219 int armv4_5_run_algorithm(struct target *target,
 220                 int num_mem_params, struct mem_param *mem_params,
 221                 int num_reg_params, struct reg_param *reg_params,
 222                 uint32_t entry_point, uint32_t exit_point,
 223                 int timeout_ms, void *arch_info);
 224 int armv4_5_run_algorithm_inner(struct target *target,
 225                 int num_mem_params, struct mem_param *mem_params,
 226                 int num_reg_params, struct reg_param *reg_params,
 227                 uint32_t entry_point, uint32_t exit_point,
 228                 int timeout_ms, void *arch_info,
 229                 int (*run_it)(struct target *target, uint32_t exit_point,
 230                                 int timeout_ms, void *arch_info));
 231
 232 int arm_checksum_memory(struct target *target,
 233                 uint32_t address, uint32_t count, uint32_t *checksum);
 234 int arm_blank_check_memory(struct target *target,
 235                 uint32_t address, uint32_t count, uint32_t *blank);
 236
 237 void arm_set_cpsr(struct arm *arm, uint32_t cpsr);
 238 struct reg *arm_reg_current(struct arm *arm, unsigned regnum);
 239
 240 extern struct reg arm_gdb_dummy_fp_reg;
 241 extern struct reg arm_gdb_dummy_fps_reg;
 242
 243 #endif /* ARM_H */