src/target/arm.h

   1 /*
   2  * Copyright (C) 2005 by Dominic Rath
   3  * Dominic.Rath@gmx.de
   4  *
   5  * Copyright (C) 2008 by Spencer Oliver
   6  * spen@spen-soft.co.uk
   7  *
   8  * Copyright (C) 2009 by Øyvind Harboe
   9  * oyvind.harboe@zylin.com
  10  *
  11  * Copyright (C) 2018 by Liviu Ionescu
  12  *   <ilg@livius.net>
  13  *
  14  * This program is free software; you can redistribute it and/or modify
  15  * it under the terms of the GNU General Public License as published by
  16  * the Free Software Foundation; either version 2 of the License, or
  17  * (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  26  */
  27
  28 #ifndef OPENOCD_TARGET_ARM_H
  29 #define OPENOCD_TARGET_ARM_H
  30
  31 #include <helper/command.h>
  32 #include "target.h"
  33
  34 /**
  35  * @file
  36  * Holds the interface to ARM cores.
  37  *
  38  * At this writing, only "classic ARM" cores built on the ARMv4 register
  39  * and mode model are supported.  The Thumb2-only microcontroller profile
  40  * support has not yet been integrated, affecting Cortex-M parts.
  41  */
  42
  43 /**
  44  * Represent state of an ARM core.
  45  *
  46  * Most numbers match the five low bits of the *PSR registers on
  47  * "classic ARM" processors, which build on the ARMv4 processor
  48  * modes and register set.
  49  *
  50  * ARM_MODE_ANY is a magic value, often used as a wildcard.
  51  *
  52  * Only the microcontroller cores (ARMv6-M, ARMv7-M) support ARM_MODE_THREAD,
  53  * ARM_MODE_USER_THREAD, and ARM_MODE_HANDLER.  Those are the only modes
  54  * they support.
  55  */
  56 enum arm_mode {
  57         ARM_MODE_USR = 16,
  58         ARM_MODE_FIQ = 17,
  59         ARM_MODE_IRQ = 18,
  60         ARM_MODE_SVC = 19,
  61         ARM_MODE_MON = 22,
  62         ARM_MODE_ABT = 23,
  63         ARM_MODE_UND = 27,
  64         ARM_MODE_1176_MON = 28,
  65         ARM_MODE_SYS = 31,
  66
  67         ARM_MODE_THREAD = 0,
  68         ARM_MODE_USER_THREAD = 1,
  69         ARM_MODE_HANDLER = 2,
  70
  71         ARMV8_64_EL0T = 0x0,
  72         ARMV8_64_EL1T = 0x4,
  73         ARMV8_64_EL1H = 0x5,
  74         ARMV8_64_EL2T = 0x8,
  75         ARMV8_64_EL2H = 0x9,
  76         ARMV8_64_EL3T = 0xC,
  77         ARMV8_64_EL3H = 0xD,
  78
  79         ARM_MODE_ANY = -1
  80 };
  81
  82 /* VFPv3 internal register numbers mapping to d0:31 */
  83 enum {
  84         ARM_VFP_V3_D0 = 51,
  85         ARM_VFP_V3_D1,
  86         ARM_VFP_V3_D2,
  87         ARM_VFP_V3_D3,
  88         ARM_VFP_V3_D4,
  89         ARM_VFP_V3_D5,
  90         ARM_VFP_V3_D6,
  91         ARM_VFP_V3_D7,
  92         ARM_VFP_V3_D8,
  93         ARM_VFP_V3_D9,
  94         ARM_VFP_V3_D10,
  95         ARM_VFP_V3_D11,
  96         ARM_VFP_V3_D12,
  97         ARM_VFP_V3_D13,
  98         ARM_VFP_V3_D14,
  99         ARM_VFP_V3_D15,
 100         ARM_VFP_V3_D16,
 101         ARM_VFP_V3_D17,
 102         ARM_VFP_V3_D18,
 103         ARM_VFP_V3_D19,
 104         ARM_VFP_V3_D20,
 105         ARM_VFP_V3_D21,
 106         ARM_VFP_V3_D22,
 107         ARM_VFP_V3_D23,
 108         ARM_VFP_V3_D24,
 109         ARM_VFP_V3_D25,
 110         ARM_VFP_V3_D26,
 111         ARM_VFP_V3_D27,
 112         ARM_VFP_V3_D28,
 113         ARM_VFP_V3_D29,
 114         ARM_VFP_V3_D30,
 115         ARM_VFP_V3_D31,
 116         ARM_VFP_V3_FPSCR,
 117 };
 118
 119 const char *arm_mode_name(unsigned psr_mode);
 120 bool is_arm_mode(unsigned psr_mode);
 121
 122 /** The PSR "T" and "J" bits define the mode of "classic ARM" cores. */
 123 enum arm_state {
 124         ARM_STATE_ARM,
 125         ARM_STATE_THUMB,
 126         ARM_STATE_JAZELLE,
 127         ARM_STATE_THUMB_EE,
 128         ARM_STATE_AARCH64,
 129 };
 130
 131 /** ARM vector floating point enabled, if yes which version. */
 132 enum arm_vfp_version {
 133         ARM_VFP_DISABLED,
 134         ARM_VFP_V1,
 135         ARM_VFP_V2,
 136         ARM_VFP_V3,
 137 };
 138
 139 #define ARM_COMMON_MAGIC 0x0A450A45
 140
 141 /**
 142  * Represents a generic ARM core, with standard application registers.
 143  *
 144  * There are sixteen application registers (including PC, SP, LR) and a PSR.
 145  * Cortex-M series cores do not support as many core states or shadowed
 146  * registers as traditional ARM cores, and only support Thumb2 instructions.
 147  */
 148 struct arm {
 149         int common_magic;
 150         struct reg_cache *core_cache;
 151
 152         /** Handle to the PC; valid in all core modes. */
 153         struct reg *pc;
 154
 155         /** Handle to the CPSR/xPSR; valid in all core modes. */
 156         struct reg *cpsr;
 157
 158         /** Handle to the SPSR; valid only in core modes with an SPSR. */
 159         struct reg *spsr;
 160
 161         /** Support for arm_reg_current() */
 162         const int *map;
 163
 164         /**
 165          * Indicates what registers are in the ARM state core register set.
 166          * ARM_MODE_ANY indicates the standard set of 37 registers,
 167          * seen on for example ARM7TDMI cores.  ARM_MODE_MON indicates three
 168          * more registers are shadowed, for "Secure Monitor" mode.
 169          * ARM_MODE_THREAD indicates a microcontroller profile core,
 170          * which only shadows SP.
 171          */
 172         enum arm_mode core_type;
 173
 174         /** Record the current core mode: SVC, USR, or some other mode. */
 175         enum arm_mode core_mode;
 176
 177         /** Record the current core state: ARM, Thumb, or otherwise. */
 178         enum arm_state core_state;
 179
 180         /** Flag reporting unavailability of the BKPT instruction. */
 181         bool is_armv4;
 182
 183         /** Flag reporting armv6m based core. */
 184         bool is_armv6m;
 185
 186         /** Floating point or VFP version, 0 if disabled. */
 187         int arm_vfp_version;
 188
 189         int (*setup_semihosting)(struct target *target, int enable);
 190
 191         /** Backpointer to the target. */
 192         struct target *target;
 193
 194         /** Handle for the debug module, if one is present. */
 195         struct arm_dpm *dpm;
 196
 197         /** Handle for the Embedded Trace Module, if one is present. */
 198         struct etm_context *etm;
 199
 200         /* FIXME all these methods should take "struct arm *" not target */
 201
 202         /** Retrieve all core registers, for display. */
 203         int (*full_context)(struct target *target);
 204
 205         /** Retrieve a single core register. */
 206         int (*read_core_reg)(struct target *target, struct reg *reg,
 207                         int num, enum arm_mode mode);
 208         int (*write_core_reg)(struct target *target, struct reg *reg,
 209                         int num, enum arm_mode mode, uint8_t *value);
 210
 211         /** Read coprocessor register.  */
 212         int (*mrc)(struct target *target, int cpnum,
 213                         uint32_t op1, uint32_t op2,
 214                         uint32_t CRn, uint32_t CRm,
 215                         uint32_t *value);
 216
 217         /** Write coprocessor register.  */
 218         int (*mcr)(struct target *target, int cpnum,
 219                         uint32_t op1, uint32_t op2,
 220                         uint32_t CRn, uint32_t CRm,
 221                         uint32_t value);
 222
 223         void *arch_info;
 224
 225         /** For targets conforming to ARM Debug Interface v5,
 226          * this handle references the Debug Access Port (DAP)
 227          * used to make requests to the target.
 228          */
 229         struct adiv5_dap *dap;
 230 };
 231
 232 /** Convert target handle to generic ARM target state handle. */
 233 static inline struct arm *target_to_arm(struct target *target)
 234 {
 235         assert(target != NULL);
 236         return target->arch_info;
 237 }
 238
 239 static inline bool is_arm(struct arm *arm)
 240 {
 241         assert(arm != NULL);
 242         return arm->common_magic == ARM_COMMON_MAGIC;
 243 }
 244
 245 struct arm_algorithm {
 246         int common_magic;
 247
 248         enum arm_mode core_mode;
 249         enum arm_state core_state;
 250 };
 251
 252 struct arm_reg {
 253         int num;
 254         enum arm_mode mode;
 255         struct target *target;
 256         struct arm *arm;
 257         uint8_t value[16];
 258 };
 259
 260 struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm);
 261 struct reg_cache *armv8_build_reg_cache(struct target *target);
 262
 263 extern const struct command_registration arm_command_handlers[];
 264
 265 int arm_arch_state(struct target *target);
 266 const char *arm_get_gdb_arch(struct target *target);
 267 int arm_get_gdb_reg_list(struct target *target,
 268                 struct reg **reg_list[], int *reg_list_size,
 269                 enum target_register_class reg_class);
 270 const char *armv8_get_gdb_arch(struct target *target);
 271 int armv8_get_gdb_reg_list(struct target *target,
 272                 struct reg **reg_list[], int *reg_list_size,
 273                 enum target_register_class reg_class);
 274
 275 int arm_init_arch_info(struct target *target, struct arm *arm);
 276
 277 /* REVISIT rename this once it's usable by ARMv7-M */
 278 int armv4_5_run_algorithm(struct target *target,
 279                 int num_mem_params, struct mem_param *mem_params,
 280                 int num_reg_params, struct reg_param *reg_params,
 281                 target_addr_t entry_point, target_addr_t exit_point,
 282                 int timeout_ms, void *arch_info);
 283 int armv4_5_run_algorithm_inner(struct target *target,
 284                 int num_mem_params, struct mem_param *mem_params,
 285                 int num_reg_params, struct reg_param *reg_params,
 286                 uint32_t entry_point, uint32_t exit_point,
 287                 int timeout_ms, void *arch_info,
 288                 int (*run_it)(struct target *target, uint32_t exit_point,
 289                                 int timeout_ms, void *arch_info));
 290
 291 int arm_checksum_memory(struct target *target,
 292                 target_addr_t address, uint32_t count, uint32_t *checksum);
 293 int arm_blank_check_memory(struct target *target,
 294                 struct target_memory_check_block *blocks, int num_blocks, uint8_t erased_value);
 295
 296 void arm_set_cpsr(struct arm *arm, uint32_t cpsr);
 297 struct reg *arm_reg_current(struct arm *arm, unsigned regnum);
 298 struct reg *armv8_reg_current(struct arm *arm, unsigned regnum);
 299
 300 extern struct reg arm_gdb_dummy_fp_reg;
 301 extern struct reg arm_gdb_dummy_fps_reg;
 302
 303 #endif /* OPENOCD_TARGET_ARM_H */