e4f203838f3b3fee5cae7717e3a7ffd094c6da85
[openocd.git] / src / target / arm.h
1 /*
2 * Copyright (C) 2005 by Dominic Rath
3 * Dominic.Rath@gmx.de
4 *
5 * Copyright (C) 2008 by Spencer Oliver
6 * spen@spen-soft.co.uk
7 *
8 * Copyright (C) 2009 by √ėyvind Harboe
9 * oyvind.harboe@zylin.com
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 */
24
25 #ifndef OPENOCD_TARGET_ARM_H
26 #define OPENOCD_TARGET_ARM_H
27
28 #include <helper/command.h>
29 #include "target.h"
30
31
32 /**
33 * @file
34 * Holds the interface to ARM cores.
35 *
36 * At this writing, only "classic ARM" cores built on the ARMv4 register
37 * and mode model are supported. The Thumb2-only microcontroller profile
38 * support has not yet been integrated, affecting Cortex-M parts.
39 */
40
41 /**
42 * Represent state of an ARM core.
43 *
44 * Most numbers match the five low bits of the *PSR registers on
45 * "classic ARM" processors, which build on the ARMv4 processor
46 * modes and register set.
47 *
48 * ARM_MODE_ANY is a magic value, often used as a wildcard.
49 *
50 * Only the microcontroller cores (ARMv6-M, ARMv7-M) support ARM_MODE_THREAD,
51 * ARM_MODE_USER_THREAD, and ARM_MODE_HANDLER. Those are the only modes
52 * they support.
53 */
54 enum arm_mode {
55 ARM_MODE_USR = 16,
56 ARM_MODE_FIQ = 17,
57 ARM_MODE_IRQ = 18,
58 ARM_MODE_SVC = 19,
59 ARM_MODE_MON = 22,
60 ARM_MODE_ABT = 23,
61 ARM_MODE_UND = 27,
62 ARM_MODE_1176_MON = 28,
63 ARM_MODE_SYS = 31,
64
65 ARM_MODE_THREAD = 0,
66 ARM_MODE_USER_THREAD = 1,
67 ARM_MODE_HANDLER = 2,
68
69 ARM_MODE_ANY = -1
70 };
71
72 const char *arm_mode_name(unsigned psr_mode);
73 bool is_arm_mode(unsigned psr_mode);
74
75 /** The PSR "T" and "J" bits define the mode of "classic ARM" cores. */
76 enum arm_state {
77 ARM_STATE_ARM,
78 ARM_STATE_THUMB,
79 ARM_STATE_JAZELLE,
80 ARM_STATE_THUMB_EE,
81 ARM_STATE_AARCH64,
82 };
83
84 #define ARM_COMMON_MAGIC 0x0A450A45
85
86 /**
87 * Represents a generic ARM core, with standard application registers.
88 *
89 * There are sixteen application registers (including PC, SP, LR) and a PSR.
90 * Cortex-M series cores do not support as many core states or shadowed
91 * registers as traditional ARM cores, and only support Thumb2 instructions.
92 */
93 struct arm {
94 int common_magic;
95 struct reg_cache *core_cache;
96
97 /** Handle to the PC; valid in all core modes. */
98 struct reg *pc;
99
100 /** Handle to the CPSR/xPSR; valid in all core modes. */
101 struct reg *cpsr;
102
103 /** Handle to the SPSR; valid only in core modes with an SPSR. */
104 struct reg *spsr;
105
106 /** Support for arm_reg_current() */
107 const int *map;
108
109 /**
110 * Indicates what registers are in the ARM state core register set.
111 * ARM_MODE_ANY indicates the standard set of 37 registers,
112 * seen on for example ARM7TDMI cores. ARM_MODE_MON indicates three
113 * more registers are shadowed, for "Secure Monitor" mode.
114 * ARM_MODE_THREAD indicates a microcontroller profile core,
115 * which only shadows SP.
116 */
117 enum arm_mode core_type;
118
119 /** Record the current core mode: SVC, USR, or some other mode. */
120 enum arm_mode core_mode;
121
122 /** Record the current core state: ARM, Thumb, or otherwise. */
123 enum arm_state core_state;
124
125 /** Flag reporting unavailability of the BKPT instruction. */
126 bool is_armv4;
127
128 /** Flag reporting armv6m based core. */
129 bool is_armv6m;
130
131 /** Flag reporting whether semihosting is active. */
132 bool is_semihosting;
133
134 /** Flag reporting whether semihosting fileio is active. */
135 bool is_semihosting_fileio;
136
137 /** Flag reporting whether semihosting fileio operation is active. */
138 bool semihosting_hit_fileio;
139
140 /** Current semihosting operation. */
141 int semihosting_op;
142
143 /** Current semihosting result. */
144 int semihosting_result;
145
146 /** Value to be returned by semihosting SYS_ERRNO request. */
147 int semihosting_errno;
148
149 int (*setup_semihosting)(struct target *target, int enable);
150
151 /** Backpointer to the target. */
152 struct target *target;
153
154 /** Handle for the debug module, if one is present. */
155 struct arm_dpm *dpm;
156
157 /** Handle for the Embedded Trace Module, if one is present. */
158 struct etm_context *etm;
159
160 /* FIXME all these methods should take "struct arm *" not target */
161
162 /** Retrieve all core registers, for display. */
163 int (*full_context)(struct target *target);
164
165 /** Retrieve a single core register. */
166 int (*read_core_reg)(struct target *target, struct reg *reg,
167 int num, enum arm_mode mode);
168 int (*write_core_reg)(struct target *target, struct reg *reg,
169 int num, enum arm_mode mode, uint8_t *value);
170
171 /** Read coprocessor register. */
172 int (*mrc)(struct target *target, int cpnum,
173 uint32_t op1, uint32_t op2,
174 uint32_t CRn, uint32_t CRm,
175 uint32_t *value);
176
177 /** Write coprocessor register. */
178 int (*mcr)(struct target *target, int cpnum,
179 uint32_t op1, uint32_t op2,
180 uint32_t CRn, uint32_t CRm,
181 uint32_t value);
182
183 void *arch_info;
184
185 /** For targets conforming to ARM Debug Interface v5,
186 * this handle references the Debug Access Port (DAP)
187 * used to make requests to the target.
188 */
189 struct adiv5_dap *dap;
190 };
191
192 /** Convert target handle to generic ARM target state handle. */
193 static inline struct arm *target_to_arm(struct target *target)
194 {
195 assert(target != NULL);
196 return target->arch_info;
197 }
198
199 static inline bool is_arm(struct arm *arm)
200 {
201 assert(arm != NULL);
202 return arm->common_magic == ARM_COMMON_MAGIC;
203 }
204
205 struct arm_algorithm {
206 int common_magic;
207
208 enum arm_mode core_mode;
209 enum arm_state core_state;
210 };
211
212 struct arm_reg {
213 int num;
214 enum arm_mode mode;
215 struct target *target;
216 struct arm *arm;
217 uint8_t value[4];
218 };
219
220 struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm);
221 struct reg_cache *armv8_build_reg_cache(struct target *target);
222
223 extern const struct command_registration arm_command_handlers[];
224
225 int arm_arch_state(struct target *target);
226 int arm_get_gdb_reg_list(struct target *target,
227 struct reg **reg_list[], int *reg_list_size,
228 enum target_register_class reg_class);
229 int armv8_get_gdb_reg_list(struct target *target,
230 struct reg **reg_list[], int *reg_list_size,
231 enum target_register_class reg_class);
232
233 int arm_init_arch_info(struct target *target, struct arm *arm);
234
235 /* REVISIT rename this once it's usable by ARMv7-M */
236 int armv4_5_run_algorithm(struct target *target,
237 int num_mem_params, struct mem_param *mem_params,
238 int num_reg_params, struct reg_param *reg_params,
239 target_addr_t entry_point, target_addr_t exit_point,
240 int timeout_ms, void *arch_info);
241 int armv4_5_run_algorithm_inner(struct target *target,
242 int num_mem_params, struct mem_param *mem_params,
243 int num_reg_params, struct reg_param *reg_params,
244 uint32_t entry_point, uint32_t exit_point,
245 int timeout_ms, void *arch_info,
246 int (*run_it)(struct target *target, uint32_t exit_point,
247 int timeout_ms, void *arch_info));
248
249 int arm_checksum_memory(struct target *target,
250 target_addr_t address, uint32_t count, uint32_t *checksum);
251 int arm_blank_check_memory(struct target *target,
252 target_addr_t address, uint32_t count, uint32_t *blank, uint8_t erased_value);
253
254 void arm_set_cpsr(struct arm *arm, uint32_t cpsr);
255 struct reg *arm_reg_current(struct arm *arm, unsigned regnum);
256 struct reg *armv8_reg_current(struct arm *arm, unsigned regnum);
257
258 extern struct reg arm_gdb_dummy_fp_reg;
259 extern struct reg arm_gdb_dummy_fps_reg;
260
261 #endif /* OPENOCD_TARGET_ARM_H */