63932e117ee8abb1b46f0c8406a7066d229b8f9b
[openocd.git] / src / target / arm.h
1 /*
2 * Copyright (C) 2005 by Dominic Rath
3 * Dominic.Rath@gmx.de
4 *
5 * Copyright (C) 2008 by Spencer Oliver
6 * spen@spen-soft.co.uk
7 *
8 * Copyright (C) 2009 by √ėyvind Harboe
9 * oyvind.harboe@zylin.com
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the
23 * Free Software Foundation, Inc.,
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
25 */
26 #ifndef ARM_H
27 #define ARM_H
28
29 #include <helper/command.h>
30 #include "target.h"
31
32
33 /**
34 * @file
35 * Holds the interface to ARM cores.
36 *
37 * At this writing, only "classic ARM" cores built on the ARMv4 register
38 * and mode model are supported. The Thumb2-only microcontroller profile
39 * support has not yet been integrated, affecting Cortex-M parts.
40 */
41
42 /**
43 * Represent state of an ARM core.
44 *
45 * Most numbers match the five low bits of the *PSR registers on
46 * "classic ARM" processors, which build on the ARMv4 processor
47 * modes and register set.
48 *
49 * ARM_MODE_ANY is a magic value, often used as a wildcard.
50 *
51 * Only the microcontroller cores (ARMv6-M, ARMv7-M) support ARM_MODE_THREAD,
52 * ARM_MODE_USER_THREAD, and ARM_MODE_HANDLER. Those are the only modes
53 * they support.
54 */
55 enum arm_mode {
56 ARM_MODE_USR = 16,
57 ARM_MODE_FIQ = 17,
58 ARM_MODE_IRQ = 18,
59 ARM_MODE_SVC = 19,
60 ARM_MODE_ABT = 23,
61 ARM_MODE_MON = 26,
62 ARM_MODE_UND = 27,
63 ARM_MODE_SYS = 31,
64
65 ARM_MODE_THREAD,
66 ARM_MODE_USER_THREAD,
67 ARM_MODE_HANDLER,
68
69 ARM_MODE_ANY = -1
70 };
71
72 const char *arm_mode_name(unsigned psr_mode);
73 bool is_arm_mode(unsigned psr_mode);
74
75 /** The PSR "T" and "J" bits define the mode of "classic ARM" cores. */
76 enum arm_state {
77 ARM_STATE_ARM,
78 ARM_STATE_THUMB,
79 ARM_STATE_JAZELLE,
80 ARM_STATE_THUMB_EE,
81 };
82
83 #define ARM_COMMON_MAGIC 0x0A450A45
84
85 /**
86 * Represents a generic ARM core, with standard application registers.
87 *
88 * There are sixteen application registers (including PC, SP, LR) and a PSR.
89 * Cortex-M series cores do not support as many core states or shadowed
90 * registers as traditional ARM cores, and only support Thumb2 instructions.
91 */
92 struct arm {
93 int common_magic;
94 struct reg_cache *core_cache;
95
96 /** Handle to the PC; valid in all core modes. */
97 struct reg *pc;
98
99 /** Handle to the CPSR; valid in all core modes. */
100 struct reg *cpsr;
101
102 /** Handle to the SPSR; valid only in core modes with an SPSR. */
103 struct reg *spsr;
104
105 /** Support for arm_reg_current() */
106 const int *map;
107
108 /**
109 * Indicates what registers are in the ARM state core register set.
110 * ARM_MODE_ANY indicates the standard set of 37 registers,
111 * seen on for example ARM7TDMI cores. ARM_MODE_MON indicates three
112 * more registers are shadowed, for "Secure Monitor" mode.
113 * ARM_MODE_THREAD indicates a microcontroller profile core,
114 * which only shadows SP.
115 */
116 enum arm_mode core_type;
117
118 /** Record the current core mode: SVC, USR, or some other mode. */
119 enum arm_mode core_mode;
120
121 /** Record the current core state: ARM, Thumb, or otherwise. */
122 enum arm_state core_state;
123
124 /** Flag reporting unavailability of the BKPT instruction. */
125 bool is_armv4;
126
127 /** Flag reporting whether semihosting is active. */
128 bool is_semihosting;
129
130 /** Value to be returned by semihosting SYS_ERRNO request. */
131 int semihosting_errno;
132
133 int (*setup_semihosting)(struct target *target, int enable);
134
135 /** Backpointer to the target. */
136 struct target *target;
137
138 /** Handle for the debug module, if one is present. */
139 struct arm_dpm *dpm;
140
141 /** Handle for the Embedded Trace Module, if one is present. */
142 struct etm_context *etm;
143
144 /* FIXME all these methods should take "struct arm *" not target */
145
146 /** Retrieve all core registers, for display. */
147 int (*full_context)(struct target *target);
148
149 /** Retrieve a single core register. */
150 int (*read_core_reg)(struct target *target, struct reg *reg,
151 int num, enum arm_mode mode);
152 int (*write_core_reg)(struct target *target, struct reg *reg,
153 int num, enum arm_mode mode, uint32_t value);
154
155 /** Read coprocessor register. */
156 int (*mrc)(struct target *target, int cpnum,
157 uint32_t op1, uint32_t op2,
158 uint32_t CRn, uint32_t CRm,
159 uint32_t *value);
160
161 /** Write coprocessor register. */
162 int (*mcr)(struct target *target, int cpnum,
163 uint32_t op1, uint32_t op2,
164 uint32_t CRn, uint32_t CRm,
165 uint32_t value);
166
167 void *arch_info;
168
169 /** For targets conforming to ARM Debug Interface v5,
170 * this handle references the Debug Access Port (DAP)
171 * used to make requests to the target.
172 */
173 struct adiv5_dap *dap;
174 };
175
176 /** Convert target handle to generic ARM target state handle. */
177 static inline struct arm *target_to_arm(struct target *target)
178 {
179 assert(target != NULL);
180 return target->arch_info;
181 }
182
183 static inline bool is_arm(struct arm *arm)
184 {
185 assert(arm != NULL);
186 return arm->common_magic == ARM_COMMON_MAGIC;
187 }
188
189 struct arm_algorithm {
190 int common_magic;
191
192 enum arm_mode core_mode;
193 enum arm_state core_state;
194 };
195
196 struct arm_reg {
197 int num;
198 enum arm_mode mode;
199 struct target *target;
200 struct arm *armv4_5_common;
201 uint32_t value;
202 };
203
204 struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm);
205
206 extern const struct command_registration arm_command_handlers[];
207
208 int arm_arch_state(struct target *target);
209 int arm_get_gdb_reg_list(struct target *target,
210 struct reg **reg_list[], int *reg_list_size);
211
212 int arm_init_arch_info(struct target *target, struct arm *arm);
213
214 /* REVISIT rename this once it's usable by ARMv7-M */
215 int armv4_5_run_algorithm(struct target *target,
216 int num_mem_params, struct mem_param *mem_params,
217 int num_reg_params, struct reg_param *reg_params,
218 uint32_t entry_point, uint32_t exit_point,
219 int timeout_ms, void *arch_info);
220 int armv4_5_run_algorithm_inner(struct target *target,
221 int num_mem_params, struct mem_param *mem_params,
222 int num_reg_params, struct reg_param *reg_params,
223 uint32_t entry_point, uint32_t exit_point,
224 int timeout_ms, void *arch_info,
225 int (*run_it)(struct target *target, uint32_t exit_point,
226 int timeout_ms, void *arch_info));
227
228 int arm_checksum_memory(struct target *target,
229 uint32_t address, uint32_t count, uint32_t *checksum);
230 int arm_blank_check_memory(struct target *target,
231 uint32_t address, uint32_t count, uint32_t *blank);
232
233 void arm_set_cpsr(struct arm *arm, uint32_t cpsr);
234 struct reg *arm_reg_current(struct arm *arm, unsigned regnum);
235
236 void arm_endianness(uint8_t *tmp, void *in, int size, int be, int flip);
237
238 extern struct reg arm_gdb_dummy_fp_reg;
239 extern struct reg arm_gdb_dummy_fps_reg;
240
241 #endif /* ARM_H */