src/target/arc.h

   1 /***************************************************************************
   2  *   Copyright (C) 2013-2015,2019-2020 Synopsys, Inc.                      *
   3  *   Frank Dols <frank.dols@synopsys.com>                                  *
   4  *   Mischa Jonker <mischa.jonker@synopsys.com>                            *
   5  *   Anton Kolesov <anton.kolesov@synopsys.com>                            *
   6  *   Evgeniy Didin <didin@synopsys.com>                                    *
   7  *                                                                         *
   8  *   SPDX-License-Identifier: GPL-2.0-or-later                             *
   9  ***************************************************************************/
  10
  11 #ifndef OPENOCD_TARGET_ARC_H
  12 #define OPENOCD_TARGET_ARC_H
  13
  14 #include <helper/time_support.h>
  15 #include <jtag/jtag.h>
  16
  17 #include "algorithm.h"
  18 #include "breakpoints.h"
  19 #include "jtag/interface.h"
  20 #include "register.h"
  21 #include "target.h"
  22 #include "target_request.h"
  23 #include "target_type.h"
  24 #include "helper/bits.h"
  25
  26 #include "arc_jtag.h"
  27 #include "arc_cmd.h"
  28 #include "arc_mem.h"
  29
  30 #define ARC_COMMON_MAGIC        0xB32EB324  /* just a unique number */
  31
  32 #define AUX_DEBUG_REG                   0x5
  33 #define AUX_PC_REG                      0x6
  34 #define AUX_STATUS32_REG                0xA
  35
  36
  37 #define SET_CORE_FORCE_HALT             BIT(1)
  38 #define SET_CORE_HALT_BIT               BIT(0)      /* STATUS32[0] = H field */
  39 #define SET_CORE_ENABLE_INTERRUPTS      BIT(31)
  40 /* STATUS32[5] or AE bit indicates if the processor is in exception state */
  41 #define SET_CORE_AE_BIT                 BIT(5)
  42 /* Single instruction step bit in Debug register */
  43 #define SET_CORE_SINGLE_INSTR_STEP      BIT(11)
  44
  45 #define AUX_STATUS32_REG_HALT_BIT       BIT(0)
  46 #define AUX_STATUS32_REG_IE_BIT         BIT(31)    /* STATUS32[31] = IE field */
  47
  48 /* Reserved core registers */
  49 #define CORE_R61_NUM                    (61)
  50 #define CORE_R62_NUM                    (62)
  51
  52 #define CORE_REG_MAX_NUMBER             (63)
  53
  54 /* Limit reg_type/reg_type_field  name to 20 symbols */
  55 #define REG_TYPE_MAX_NAME_LENGTH        20
  56
  57 /* ARC 32bits opcodes */
  58 #define ARC_SDBBP_32 0x256F003F  /* BRK */
  59
  60 /* ARC 16bits opcodes */
  61 #define ARC_SDBBP_16 0x7FFF      /* BRK_S */
  62
  63 struct arc_reg_bitfield {
  64         struct reg_data_type_bitfield bitfield;
  65         char name[REG_TYPE_MAX_NAME_LENGTH];
  66 };
  67 /* Register data type */
  68 struct arc_reg_data_type {
  69         struct list_head list;
  70         struct reg_data_type data_type;
  71         struct reg_data_type_flags data_type_flags;
  72         struct reg_data_type_struct data_type_struct;
  73         char data_type_id[REG_TYPE_MAX_NAME_LENGTH];
  74         struct arc_reg_bitfield *bitfields;
  75         union {
  76                 struct reg_data_type_struct_field *reg_type_struct_field;
  77                 struct reg_data_type_flags_field *reg_type_flags_field;
  78         };
  79 };
  80
  81
  82
  83 /* Standard GDB register types */
  84 static const struct reg_data_type standard_gdb_types[] = {
  85         { .type = REG_TYPE_INT,         .id = "int" },
  86         { .type = REG_TYPE_INT8,        .id = "int8" },
  87         { .type = REG_TYPE_INT16,       .id = "int16" },
  88         { .type = REG_TYPE_INT32,       .id = "int32" },
  89         { .type = REG_TYPE_INT64,       .id = "int64" },
  90         { .type = REG_TYPE_INT128,      .id = "int128" },
  91         { .type = REG_TYPE_UINT8,       .id = "uint8" },
  92         { .type = REG_TYPE_UINT16,      .id = "uint16" },
  93         { .type = REG_TYPE_UINT32,      .id = "uint32" },
  94         { .type = REG_TYPE_UINT64,      .id = "uint64" },
  95         { .type = REG_TYPE_UINT128,     .id = "uint128" },
  96         { .type = REG_TYPE_CODE_PTR,    .id = "code_ptr" },
  97         { .type = REG_TYPE_DATA_PTR,    .id = "data_ptr" },
  98         { .type = REG_TYPE_FLOAT,       .id = "float" },
  99         { .type = REG_TYPE_IEEE_SINGLE, .id = "ieee_single" },
 100         { .type = REG_TYPE_IEEE_DOUBLE, .id = "ieee_double" },
 101 };
 102
 103
 104 struct arc_common {
 105         uint32_t common_magic;
 106
 107         struct arc_jtag jtag_info;
 108
 109         struct reg_cache *core_and_aux_cache;
 110         struct reg_cache *bcr_cache;
 111
 112         /* Indicate if cach was built (for deinit function) */
 113         bool core_aux_cache_built;
 114         bool bcr_cache_built;
 115         /* Closely Coupled memory(CCM) regions for performance-critical
 116          * code (optional). */
 117         uint32_t iccm0_start;
 118         uint32_t iccm0_end;
 119         uint32_t iccm1_start;
 120         uint32_t iccm1_end;
 121         uint32_t dccm_start;
 122         uint32_t dccm_end;
 123
 124         int irq_state;
 125
 126         /* Register descriptions */
 127         struct list_head reg_data_types;
 128         struct list_head core_reg_descriptions;
 129         struct list_head aux_reg_descriptions;
 130         struct list_head bcr_reg_descriptions;
 131         unsigned long num_regs;
 132         unsigned long num_core_regs;
 133         unsigned long num_aux_regs;
 134         unsigned long num_bcr_regs;
 135         unsigned long last_general_reg;
 136
 137         /* PC register location in register cache. */
 138         unsigned long pc_index_in_cache;
 139         /* DEBUG register location in register cache. */
 140         unsigned long debug_index_in_cache;
 141 };
 142
 143 /* Borrowed from nds32.h */
 144 #define CHECK_RETVAL(action)                    \
 145         do {                                    \
 146                 int __retval = (action);        \
 147                 if (__retval != ERROR_OK) {     \
 148                         LOG_DEBUG("error while calling \"%s\"", \
 149                                 # action);     \
 150                         return __retval;        \
 151                 }                               \
 152         } while (0)
 153
 154 #define JIM_CHECK_RETVAL(action)                \
 155         do {                                    \
 156                 int __retval = (action);        \
 157                 if (__retval != JIM_OK) {       \
 158                         LOG_DEBUG("error while calling \"%s\"", \
 159                                 # action);     \
 160                         return __retval;        \
 161                 }                               \
 162         } while (0)
 163
 164 static inline struct arc_common *target_to_arc(struct target *target)
 165 {
 166         return target->arch_info;
 167 }
 168
 169 /* ----- Inlined functions ------------------------------------------------- */
 170
 171 /**
 172  * Convert data in host endianness to the middle endian. This is required to
 173  * write 4-byte instructions.
 174  */
 175 static inline void arc_h_u32_to_me(uint8_t *buf, int val)
 176 {
 177         buf[1] = (uint8_t) (val >> 24);
 178         buf[0] = (uint8_t) (val >> 16);
 179         buf[3] = (uint8_t) (val >> 8);
 180         buf[2] = (uint8_t) (val >> 0);
 181 }
 182
 183 /**
 184  * Convert data in middle endian to host endian. This is required to read 32-bit
 185  * instruction from little endian ARCs.
 186  */
 187 static inline uint32_t arc_me_to_h_u32(const uint8_t *buf)
 188 {
 189         return (uint32_t)(buf[2] | buf[3] << 8 | buf[0] << 16 | buf[1] << 24);
 190 }
 191
 192
 193 /* ARC Register description */
 194 struct arc_reg_desc {
 195
 196         struct target *target;
 197
 198         /* Register name */
 199         char *name;
 200
 201         /* Actual place of storing reg_value */
 202         uint8_t reg_value[4];
 203
 204         /* Actual place of storing register feature */
 205         struct reg_feature feature;
 206
 207         /* GDB XML feature */
 208         char *gdb_xml_feature;
 209
 210         /* Is this a register in g/G-packet? */
 211         bool is_general;
 212
 213         /* Architectural number: core reg num or AUX reg num */
 214         uint32_t arch_num;
 215
 216         /* Core or AUX register? */
 217         bool is_core;
 218
 219         /* Build configuration register? */
 220         bool is_bcr;
 221
 222         /* Data type */
 223         struct reg_data_type *data_type;
 224
 225         struct list_head list;
 226 };
 227
 228 /* Error codes */
 229 #define ERROR_ARC_REGISTER_NOT_FOUND       (-700)
 230 #define ERROR_ARC_REGISTER_FIELD_NOT_FOUND (-701)
 231 #define ERROR_ARC_REGISTER_IS_NOT_STRUCT   (-702)
 232 #define ERROR_ARC_FIELD_IS_NOT_BITFIELD    (-703)
 233 #define ERROR_ARC_REGTYPE_NOT_FOUND        (-704)
 234
 235 void free_reg_desc(struct arc_reg_desc *r);
 236
 237
 238 void arc_reg_data_type_add(struct target *target,
 239                 struct arc_reg_data_type *data_type);
 240
 241 int arc_reg_add(struct target *target, struct arc_reg_desc *arc_reg,
 242                 const char * const type_name, const size_t type_name_len);
 243
 244 struct reg *arc_reg_get_by_name(struct reg_cache *first,
 245                                         const char *name, bool search_all);
 246
 247 int arc_reg_get_field(struct target *target, const char *reg_name,
 248                 const char *field_name, uint32_t *value_ptr);
 249
 250 #endif /* OPENOCD_TARGET_ARC_H */