1 /***************************************************************************
2 * Copyright (C) 2013-2015,2019-2020 Synopsys, Inc. *
3 * Frank Dols <frank.dols@synopsys.com> *
4 * Mischa Jonker <mischa.jonker@synopsys.com> *
5 * Anton Kolesov <anton.kolesov@synopsys.com> *
6 * Evgeniy Didin <didin@synopsys.com> *
8 * SPDX-License-Identifier: GPL-2.0-or-later *
9 ***************************************************************************/
21 * ARC architecture specific details.
23 * ARC has two types of registers:
24 * 1) core registers(e.g. r0,r1..) [is_core = true]
25 * 2) Auxiliary registers [is_core = false]..
27 * Auxiliary registers at the same time can be divided into
28 * read-only BCR(build configuration regs, e.g. isa_config, mpu_build) and
29 * R/RW non-BCR ("control" register, e.g. pc, status32_t, debug).
31 * The way of accessing to Core and AUX registers differs on Jtag level.
32 * BCR/non-BCR describes if the register is immutable and that reading
33 * unexisting register is safe RAZ, rather then an error.
34 * Note, core registers cannot be BCR.
36 * In arc/cpu/ tcl files all regiters are defined as core, non-BCR aux
37 * and BCR aux, in "add-reg" command they are passed to three lists
38 * respectively: core_reg_descriptions, aux_reg_descriptions,
39 * bcr_reg_descriptions.
41 * Due to the specifics of accessing to BCR/non-BCR registers there are two
43 * 1) core_and_aux_cache - includes registers described in
44 * core_reg_descriptions and aux_reg_descriptions lists.
45 * Used during save/restore context step.
46 * 2) bcr_cache - includes registers described bcr_reg_descriptions.
47 * Currently used internally during configure step.
52 void arc_reg_data_type_add(struct target
*target
,
53 struct arc_reg_data_type
*data_type
)
55 LOG_DEBUG("Adding %s reg_data_type", data_type
->data_type
.id
);
56 struct arc_common
*arc
= target_to_arc(target
);
59 list_add_tail(&data_type
->list
, &arc
->reg_data_types
);
63 * Private implementation of register_get_by_name() for ARC that
64 * doesn't skip not [yet] existing registers. Used in many places
65 * for iteration through registers and even for marking required registers as
68 struct reg
*arc_reg_get_by_name(struct reg_cache
*first
,
69 const char *name
, bool search_all
)
72 struct reg_cache
*cache
= first
;
75 for (i
= 0; i
< cache
->num_regs
; i
++) {
76 if (!strcmp(cache
->reg_list
[i
].name
, name
))
77 return &(cache
->reg_list
[i
]);
90 /* Initialize arc_common structure, which passes to openocd target instance */
91 static int arc_init_arch_info(struct target
*target
, struct arc_common
*arc
,
94 arc
->common_magic
= ARC_COMMON_MAGIC
;
95 target
->arch_info
= arc
;
97 arc
->jtag_info
.tap
= tap
;
99 /* The only allowed ir_length is 4 for ARC jtag. */
100 if (tap
->ir_length
!= 4) {
101 LOG_ERROR("ARC jtag instruction length should be equal to 4");
105 /* Add standard GDB data types */
106 INIT_LIST_HEAD(&arc
->reg_data_types
);
107 struct arc_reg_data_type
*std_types
= calloc(ARRAY_SIZE(standard_gdb_types
),
111 LOG_ERROR("Unable to allocate memory");
115 for (unsigned int i
= 0; i
< ARRAY_SIZE(standard_gdb_types
); i
++) {
116 std_types
[i
].data_type
.type
= standard_gdb_types
[i
].type
;
117 std_types
[i
].data_type
.id
= standard_gdb_types
[i
].id
;
118 arc_reg_data_type_add(target
, &(std_types
[i
]));
121 /* Fields related to target descriptions */
122 INIT_LIST_HEAD(&arc
->core_reg_descriptions
);
123 INIT_LIST_HEAD(&arc
->aux_reg_descriptions
);
124 INIT_LIST_HEAD(&arc
->bcr_reg_descriptions
);
126 arc
->num_core_regs
= 0;
127 arc
->num_aux_regs
= 0;
128 arc
->num_bcr_regs
= 0;
129 arc
->last_general_reg
= ULONG_MAX
;
130 arc
->pc_index_in_cache
= ULONG_MAX
;
131 arc
->debug_index_in_cache
= ULONG_MAX
;
136 int arc_reg_add(struct target
*target
, struct arc_reg_desc
*arc_reg
,
137 const char * const type_name
, const size_t type_name_len
)
142 struct arc_common
*arc
= target_to_arc(target
);
145 /* Find register type */
147 struct arc_reg_data_type
*type
;
148 list_for_each_entry(type
, &arc
->reg_data_types
, list
)
149 if (!strncmp(type
->data_type
.id
, type_name
, type_name_len
)) {
150 arc_reg
->data_type
= &(type
->data_type
);
154 if (!arc_reg
->data_type
)
155 return ERROR_ARC_REGTYPE_NOT_FOUND
;
158 if (arc_reg
->is_core
) {
159 list_add_tail(&arc_reg
->list
, &arc
->core_reg_descriptions
);
160 arc
->num_core_regs
+= 1;
161 } else if (arc_reg
->is_bcr
) {
162 list_add_tail(&arc_reg
->list
, &arc
->bcr_reg_descriptions
);
163 arc
->num_bcr_regs
+= 1;
165 list_add_tail(&arc_reg
->list
, &arc
->aux_reg_descriptions
);
166 arc
->num_aux_regs
+= 1;
171 "added register {name=%s, num=0x%x, type=%s%s%s%s}",
172 arc_reg
->name
, arc_reg
->arch_num
, arc_reg
->data_type
->id
,
173 arc_reg
->is_core
? ", core" : "", arc_reg
->is_bcr
? ", bcr" : "",
174 arc_reg
->is_general
? ", general" : ""
180 /* Reading core or aux register */
181 static int arc_get_register(struct reg
*reg
)
185 struct arc_reg_desc
*desc
= reg
->arch_info
;
186 struct target
*target
= desc
->target
;
187 struct arc_common
*arc
= target_to_arc(target
);
192 LOG_DEBUG("Get register (cached) gdb_num=%" PRIu32
", name=%s, value=0x%" PRIx32
,
193 reg
->number
, desc
->name
, target_buffer_get_u32(target
, reg
->value
));
198 /* Accessing to R61/R62 registers causes Jtag hang */
199 if (desc
->arch_num
== CORE_R61_NUM
|| desc
->arch_num
== CORE_R62_NUM
) {
200 LOG_ERROR("It is forbidden to read core registers 61 and 62.");
203 CHECK_RETVAL(arc_jtag_read_core_reg_one(&arc
->jtag_info
, desc
->arch_num
,
206 CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc
->jtag_info
, desc
->arch_num
,
210 target_buffer_set_u32(target
, reg
->value
, value
);
212 /* If target is unhalted all register reads should be uncached. */
213 if (target
->state
== TARGET_HALTED
)
220 LOG_DEBUG("Get register gdb_num=%" PRIu32
", name=%s, value=0x%" PRIx32
,
221 reg
->number
, desc
->name
, value
);
227 /* Writing core or aux register */
228 static int arc_set_register(struct reg
*reg
, uint8_t *buf
)
230 struct arc_reg_desc
*desc
= reg
->arch_info
;
231 struct target
*target
= desc
->target
;
232 uint32_t value
= target_buffer_get_u32(target
, buf
);
233 /* Unlike "get" function "set" is supported only if target
234 * is in halt mode. Async writes are not supported yet. */
235 if (target
->state
!= TARGET_HALTED
)
236 return ERROR_TARGET_NOT_HALTED
;
238 /* Accessing to R61/R62 registers causes Jtag hang */
239 if (desc
->is_core
&& (desc
->arch_num
== CORE_R61_NUM
||
240 desc
->arch_num
== CORE_R62_NUM
)) {
241 LOG_ERROR("It is forbidden to write core registers 61 and 62.");
244 target_buffer_set_u32(target
, reg
->value
, value
);
246 LOG_DEBUG("Set register gdb_num=%" PRIu32
", name=%s, value=0x%08" PRIx32
,
247 reg
->number
, desc
->name
, value
);
255 const struct reg_arch_type arc_reg_type
= {
256 .get
= arc_get_register
,
257 .set
= arc_set_register
,
260 /* GDB register groups. For now we suport only general and "empty" */
261 static const char * const reg_group_general
= "general";
262 static const char * const reg_group_other
= "";
264 /* Common code to initialize `struct reg` for different registers: core, aux, bcr. */
265 static int arc_init_reg(struct target
*target
, struct reg
*reg
,
266 struct arc_reg_desc
*reg_desc
, unsigned long number
)
272 struct arc_common
*arc
= target_to_arc(target
);
274 /* Initialize struct reg */
275 reg
->name
= reg_desc
->name
;
276 reg
->size
= 32; /* All register in ARC are 32-bit */
277 reg
->value
= ®_desc
->reg_value
;
278 reg
->type
= &arc_reg_type
;
279 reg
->arch_info
= reg_desc
;
280 reg
->caller_save
= true; /* @todo should be configurable. */
281 reg
->reg_data_type
= reg_desc
->data_type
;
282 reg
->feature
= ®_desc
->feature
;
284 reg
->feature
->name
= reg_desc
->gdb_xml_feature
;
286 /* reg->number is used by OpenOCD as value for @regnum. Thus when setting
287 * value of a register GDB will use it as a number of register in
288 * P-packet. OpenOCD gdbserver will then use number of register in
289 * P-packet as an array index in the reg_list returned by
290 * arc_regs_get_gdb_reg_list. So to ensure that registers are assigned
291 * correctly it would be required to either sort registers in
292 * arc_regs_get_gdb_reg_list or to assign numbers sequentially here and
293 * according to how registers will be sorted in
294 * arc_regs_get_gdb_reg_list. Second options is much more simpler. */
295 reg
->number
= number
;
297 if (reg_desc
->is_general
) {
298 arc
->last_general_reg
= reg
->number
;
299 reg
->group
= reg_group_general
;
301 reg
->group
= reg_group_other
;
307 /* Building aux/core reg_cache */
308 static int arc_build_reg_cache(struct target
*target
)
311 struct arc_reg_desc
*reg_desc
;
312 /* get pointers to arch-specific information */
313 struct arc_common
*arc
= target_to_arc(target
);
314 const unsigned long num_regs
= arc
->num_core_regs
+ arc
->num_aux_regs
;
315 struct reg_cache
**cache_p
= register_get_last_cache_p(&target
->reg_cache
);
316 struct reg_cache
*cache
= calloc(1, sizeof(*cache
));
317 struct reg
*reg_list
= calloc(num_regs
, sizeof(*reg_list
));
319 if (!cache
|| !reg_list
) {
320 LOG_ERROR("Not enough memory");
324 /* Build the process context cache */
325 cache
->name
= "arc registers";
327 cache
->reg_list
= reg_list
;
328 cache
->num_regs
= num_regs
;
329 arc
->core_and_aux_cache
= cache
;
332 if (list_empty(&arc
->core_reg_descriptions
)) {
333 LOG_ERROR("No core registers were defined");
337 list_for_each_entry(reg_desc
, &arc
->core_reg_descriptions
, list
) {
338 CHECK_RETVAL(arc_init_reg(target
, ®_list
[i
], reg_desc
, i
));
340 LOG_DEBUG("reg n=%3li name=%3s group=%s feature=%s", i
,
341 reg_list
[i
].name
, reg_list
[i
].group
,
342 reg_list
[i
].feature
->name
);
347 if (list_empty(&arc
->aux_reg_descriptions
)) {
348 LOG_ERROR("No aux registers were defined");
352 list_for_each_entry(reg_desc
, &arc
->aux_reg_descriptions
, list
) {
353 CHECK_RETVAL(arc_init_reg(target
, ®_list
[i
], reg_desc
, i
));
355 LOG_DEBUG("reg n=%3li name=%3s group=%s feature=%s", i
,
356 reg_list
[i
].name
, reg_list
[i
].group
,
357 reg_list
[i
].feature
->name
);
359 /* PC and DEBUG are essential so we search for them. */
360 if (!strcmp("pc", reg_desc
->name
)) {
361 if (arc
->pc_index_in_cache
!= ULONG_MAX
) {
362 LOG_ERROR("Double definition of PC in configuration");
365 arc
->pc_index_in_cache
= i
;
366 } else if (!strcmp("debug", reg_desc
->name
)) {
367 if (arc
->debug_index_in_cache
!= ULONG_MAX
) {
368 LOG_ERROR("Double definition of DEBUG in configuration");
371 arc
->debug_index_in_cache
= i
;
376 if (arc
->pc_index_in_cache
== ULONG_MAX
377 || arc
->debug_index_in_cache
== ULONG_MAX
) {
378 LOG_ERROR("`pc' and `debug' registers must be present in target description.");
382 assert(i
== (arc
->num_core_regs
+ arc
->num_aux_regs
));
384 arc
->core_aux_cache_built
= true;
395 /* Build bcr reg_cache.
396 * This function must be called only after arc_build_reg_cache */
397 static int arc_build_bcr_reg_cache(struct target
*target
)
399 /* get pointers to arch-specific information */
400 struct arc_common
*arc
= target_to_arc(target
);
401 const unsigned long num_regs
= arc
->num_bcr_regs
;
402 struct reg_cache
**cache_p
= register_get_last_cache_p(&target
->reg_cache
);
403 struct reg_cache
*cache
= malloc(sizeof(*cache
));
404 struct reg
*reg_list
= calloc(num_regs
, sizeof(*reg_list
));
406 struct arc_reg_desc
*reg_desc
;
408 unsigned long gdb_regnum
= arc
->core_and_aux_cache
->num_regs
;
410 if (!cache
|| !reg_list
) {
411 LOG_ERROR("Unable to allocate memory");
415 /* Build the process context cache */
416 cache
->name
= "arc.bcr";
418 cache
->reg_list
= reg_list
;
419 cache
->num_regs
= num_regs
;
420 arc
->bcr_cache
= cache
;
423 if (list_empty(&arc
->bcr_reg_descriptions
)) {
424 LOG_ERROR("No BCR registers are defined");
428 list_for_each_entry(reg_desc
, &arc
->bcr_reg_descriptions
, list
) {
429 CHECK_RETVAL(arc_init_reg(target
, ®_list
[i
], reg_desc
, gdb_regnum
));
430 /* BCRs always semantically, they are just read-as-zero, if there is
431 * not real register. */
432 reg_list
[i
].exist
= true;
434 LOG_DEBUG("reg n=%3li name=%3s group=%s feature=%s", i
,
435 reg_list
[i
].name
, reg_list
[i
].group
,
436 reg_list
[i
].feature
->name
);
441 assert(i
== arc
->num_bcr_regs
);
443 arc
->bcr_cache_built
= true;
455 static int arc_get_gdb_reg_list(struct target
*target
, struct reg
**reg_list
[],
456 int *reg_list_size
, enum target_register_class reg_class
)
458 assert(target
->reg_cache
);
459 struct arc_common
*arc
= target_to_arc(target
);
461 /* get pointers to arch-specific information storage */
462 *reg_list_size
= arc
->num_regs
;
463 *reg_list
= calloc(*reg_list_size
, sizeof(struct reg
*));
466 LOG_ERROR("Unable to allocate memory");
470 /* OpenOCD gdb_server API seems to be inconsistent here: when it generates
471 * XML tdesc it filters out !exist registers, however when creating a
472 * g-packet it doesn't do so. REG_CLASS_ALL is used in first case, and
473 * REG_CLASS_GENERAL used in the latter one. Due to this we had to filter
474 * out !exist register for "general", but not for "all". Attempts to filter out
475 * !exist for "all" as well will cause a failed check in OpenOCD GDB
477 if (reg_class
== REG_CLASS_ALL
) {
479 struct reg_cache
*reg_cache
= target
->reg_cache
;
481 for (unsigned j
= 0; j
< reg_cache
->num_regs
; j
++, i
++)
482 (*reg_list
)[i
] = ®_cache
->reg_list
[j
];
483 reg_cache
= reg_cache
->next
;
485 assert(i
== arc
->num_regs
);
486 LOG_DEBUG("REG_CLASS_ALL: number of regs=%i", *reg_list_size
);
489 unsigned long gdb_reg_number
= 0;
490 struct reg_cache
*reg_cache
= target
->reg_cache
;
493 j
< reg_cache
->num_regs
&& gdb_reg_number
<= arc
->last_general_reg
;
495 if (reg_cache
->reg_list
[j
].exist
) {
496 (*reg_list
)[i
] = ®_cache
->reg_list
[j
];
501 reg_cache
= reg_cache
->next
;
504 LOG_DEBUG("REG_CLASS_GENERAL: number of regs=%i", *reg_list_size
);
510 /* Reading field of struct_type register */
511 int arc_reg_get_field(struct target
*target
, const char *reg_name
,
512 const char *field_name
, uint32_t *value_ptr
)
514 struct reg_data_type_struct_field
*field
;
516 LOG_DEBUG("getting register field (reg_name=%s, field_name=%s)", reg_name
, field_name
);
519 struct reg
*reg
= arc_reg_get_by_name(target
->reg_cache
, reg_name
, true);
522 LOG_ERROR("Requested register `%s' doens't exist.", reg_name
);
523 return ERROR_ARC_REGISTER_NOT_FOUND
;
526 if (reg
->reg_data_type
->type
!= REG_TYPE_ARCH_DEFINED
527 || reg
->reg_data_type
->type_class
!= REG_TYPE_CLASS_STRUCT
)
528 return ERROR_ARC_REGISTER_IS_NOT_STRUCT
;
530 /* Get field in a register */
531 struct reg_data_type_struct
*reg_struct
=
532 reg
->reg_data_type
->reg_type_struct
;
533 for (field
= reg_struct
->fields
;
535 field
= field
->next
) {
536 if (!strcmp(field
->name
, field_name
))
541 return ERROR_ARC_REGISTER_FIELD_NOT_FOUND
;
543 if (!field
->use_bitfields
)
544 return ERROR_ARC_FIELD_IS_NOT_BITFIELD
;
547 CHECK_RETVAL(reg
->type
->get(reg
));
549 /* First do endiannes-safe read of register value
550 * then convert it to binary buffer for further
551 * field extraction */
553 *value_ptr
= buf_get_u32(reg
->value
, field
->bitfield
->start
,
554 field
->bitfield
->end
- field
->bitfield
->start
+ 1);
559 static int arc_get_register_value(struct target
*target
, const char *reg_name
,
562 LOG_DEBUG("reg_name=%s", reg_name
);
564 struct reg
*reg
= arc_reg_get_by_name(target
->reg_cache
, reg_name
, true);
567 return ERROR_ARC_REGISTER_NOT_FOUND
;
570 CHECK_RETVAL(reg
->type
->get(reg
));
572 *value_ptr
= target_buffer_get_u32(target
, reg
->value
);
578 /* Configure DCCM's */
579 static int arc_configure_dccm(struct target
*target
)
581 struct arc_common
*arc
= target_to_arc(target
);
583 uint32_t dccm_build_version
, dccm_build_size0
, dccm_build_size1
;
584 CHECK_RETVAL(arc_reg_get_field(target
, "dccm_build", "version",
585 &dccm_build_version
));
586 CHECK_RETVAL(arc_reg_get_field(target
, "dccm_build", "size0",
588 CHECK_RETVAL(arc_reg_get_field(target
, "dccm_build", "size1",
590 /* There is no yet support of configurable number of cycles,
591 * So there is no difference between v3 and v4 */
592 if ((dccm_build_version
== 3 || dccm_build_version
== 4) && dccm_build_size0
> 0) {
593 CHECK_RETVAL(arc_get_register_value(target
, "aux_dccm", &(arc
->dccm_start
)));
594 uint32_t dccm_size
= 0x100;
595 dccm_size
<<= dccm_build_size0
;
596 if (dccm_build_size0
== 0xF)
597 dccm_size
<<= dccm_build_size1
;
598 arc
->dccm_end
= arc
->dccm_start
+ dccm_size
;
599 LOG_DEBUG("DCCM detected start=0x%" PRIx32
" end=0x%" PRIx32
,
600 arc
->dccm_start
, arc
->dccm_end
);
607 /* Configure ICCM's */
609 static int arc_configure_iccm(struct target
*target
)
611 struct arc_common
*arc
= target_to_arc(target
);
614 uint32_t iccm_build_version
, iccm_build_size00
, iccm_build_size01
;
615 uint32_t aux_iccm
= 0;
616 CHECK_RETVAL(arc_reg_get_field(target
, "iccm_build", "version",
617 &iccm_build_version
));
618 CHECK_RETVAL(arc_reg_get_field(target
, "iccm_build", "iccm0_size0",
619 &iccm_build_size00
));
620 CHECK_RETVAL(arc_reg_get_field(target
, "iccm_build", "iccm0_size1",
621 &iccm_build_size01
));
622 if (iccm_build_version
== 4 && iccm_build_size00
> 0) {
623 CHECK_RETVAL(arc_get_register_value(target
, "aux_iccm", &aux_iccm
));
624 uint32_t iccm0_size
= 0x100;
625 iccm0_size
<<= iccm_build_size00
;
626 if (iccm_build_size00
== 0xF)
627 iccm0_size
<<= iccm_build_size01
;
628 /* iccm0 start is located in highest 4 bits of aux_iccm */
629 arc
->iccm0_start
= aux_iccm
& 0xF0000000;
630 arc
->iccm0_end
= arc
->iccm0_start
+ iccm0_size
;
631 LOG_DEBUG("ICCM0 detected start=0x%" PRIx32
" end=0x%" PRIx32
,
632 arc
->iccm0_start
, arc
->iccm0_end
);
636 uint32_t iccm_build_size10
, iccm_build_size11
;
637 CHECK_RETVAL(arc_reg_get_field(target
, "iccm_build", "iccm1_size0",
638 &iccm_build_size10
));
639 CHECK_RETVAL(arc_reg_get_field(target
, "iccm_build", "iccm1_size1",
640 &iccm_build_size11
));
641 if (iccm_build_version
== 4 && iccm_build_size10
> 0) {
642 /* Use value read for ICCM0 */
644 CHECK_RETVAL(arc_get_register_value(target
, "aux_iccm", &aux_iccm
));
645 uint32_t iccm1_size
= 0x100;
646 iccm1_size
<<= iccm_build_size10
;
647 if (iccm_build_size10
== 0xF)
648 iccm1_size
<<= iccm_build_size11
;
649 arc
->iccm1_start
= aux_iccm
& 0x0F000000;
650 arc
->iccm1_end
= arc
->iccm1_start
+ iccm1_size
;
651 LOG_DEBUG("ICCM1 detected start=0x%" PRIx32
" end=0x%" PRIx32
,
652 arc
->iccm1_start
, arc
->iccm1_end
);
657 /* Configure some core features, depending on BCRs. */
658 static int arc_configure(struct target
*target
)
660 LOG_DEBUG("Configuring ARC ICCM and DCCM");
662 /* Configuring DCCM if DCCM_BUILD and AUX_DCCM are known registers. */
663 if (arc_reg_get_by_name(target
->reg_cache
, "dccm_build", true) &&
664 arc_reg_get_by_name(target
->reg_cache
, "aux_dccm", true))
665 CHECK_RETVAL(arc_configure_dccm(target
));
667 /* Configuring ICCM if ICCM_BUILD and AUX_ICCM are known registers. */
668 if (arc_reg_get_by_name(target
->reg_cache
, "iccm_build", true) &&
669 arc_reg_get_by_name(target
->reg_cache
, "aux_iccm", true))
670 CHECK_RETVAL(arc_configure_iccm(target
));
675 /* arc_examine is function, which is used for all arc targets*/
676 static int arc_examine(struct target
*target
)
679 struct arc_common
*arc
= target_to_arc(target
);
681 CHECK_RETVAL(arc_jtag_startup(&arc
->jtag_info
));
683 if (!target_was_examined(target
)) {
684 CHECK_RETVAL(arc_jtag_status(&arc
->jtag_info
, &status
));
685 if (status
& ARC_JTAG_STAT_RU
)
686 target
->state
= TARGET_RUNNING
;
688 target
->state
= TARGET_HALTED
;
690 /* Read BCRs and configure optional registers. */
691 CHECK_RETVAL(arc_configure(target
));
693 target_set_examined(target
);
699 static int arc_halt(struct target
*target
)
701 uint32_t value
, irq_state
;
702 struct arc_common
*arc
= target_to_arc(target
);
704 LOG_DEBUG("target->state: %s", target_state_name(target
));
706 if (target
->state
== TARGET_HALTED
) {
707 LOG_DEBUG("target was already halted");
711 if (target
->state
== TARGET_UNKNOWN
)
712 LOG_WARNING("target was in unknown state when halt was requested");
714 if (target
->state
== TARGET_RESET
) {
715 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST
) && jtag_get_srst()) {
716 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
717 return ERROR_TARGET_FAILURE
;
719 target
->debug_reason
= DBG_REASON_DBGRQ
;
723 /* Break (stop) processor.
724 * Do read-modify-write sequence, or DEBUG.UB will be reset unintentionally.
725 * We do not use here arc_get/set_core_reg functions here because they imply
726 * that the processor is already halted. */
727 CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc
->jtag_info
, AUX_DEBUG_REG
, &value
));
728 value
|= SET_CORE_FORCE_HALT
; /* set the HALT bit */
729 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc
->jtag_info
, AUX_DEBUG_REG
, value
));
732 /* Save current IRQ state */
733 CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc
->jtag_info
, AUX_STATUS32_REG
, &irq_state
));
735 if (irq_state
& AUX_STATUS32_REG_IE_BIT
)
740 /* update state and notify gdb*/
741 target
->state
= TARGET_HALTED
;
742 CHECK_RETVAL(target_call_event_callbacks(target
, TARGET_EVENT_HALTED
));
744 /* some more debug information */
745 if (debug_level
>= LOG_LVL_DEBUG
) {
746 LOG_DEBUG("core stopped (halted) DEGUB-REG: 0x%08" PRIx32
, value
);
747 CHECK_RETVAL(arc_get_register_value(target
, "status32", &value
));
748 LOG_DEBUG("core STATUS32: 0x%08" PRIx32
, value
);
755 * Read registers that are used in GDB g-packet. We don't read them one-by-one,
756 * but do that in one batch operation to improve speed. Calls to JTAG layer are
757 * expensive so it is better to make one big call that reads all necessary
758 * registers, instead of many calls, one for one register.
760 static int arc_save_context(struct target
*target
)
762 int retval
= ERROR_OK
;
764 struct arc_common
*arc
= target_to_arc(target
);
765 struct reg
*reg_list
= arc
->core_and_aux_cache
->reg_list
;
767 LOG_DEBUG("Saving aux and core registers values");
770 /* It is assumed that there is at least one AUX register in the list, for
772 const uint32_t core_regs_size
= arc
->num_core_regs
* sizeof(uint32_t);
773 /* last_general_reg is inclusive number. To get count of registers it is
774 * required to do +1. */
775 const uint32_t regs_to_scan
=
776 MIN(arc
->last_general_reg
+ 1, arc
->num_regs
);
777 const uint32_t aux_regs_size
= arc
->num_aux_regs
* sizeof(uint32_t);
778 uint32_t *core_values
= malloc(core_regs_size
);
779 uint32_t *aux_values
= malloc(aux_regs_size
);
780 uint32_t *core_addrs
= malloc(core_regs_size
);
781 uint32_t *aux_addrs
= malloc(aux_regs_size
);
782 unsigned int core_cnt
= 0;
783 unsigned int aux_cnt
= 0;
785 if (!core_values
|| !core_addrs
|| !aux_values
|| !aux_addrs
) {
786 LOG_ERROR("Unable to allocate memory");
791 memset(core_values
, 0xff, core_regs_size
);
792 memset(core_addrs
, 0xff, core_regs_size
);
793 memset(aux_values
, 0xff, aux_regs_size
);
794 memset(aux_addrs
, 0xff, aux_regs_size
);
796 for (i
= 0; i
< MIN(arc
->num_core_regs
, regs_to_scan
); i
++) {
797 struct reg
*reg
= &(reg_list
[i
]);
798 struct arc_reg_desc
*arc_reg
= reg
->arch_info
;
799 if (!reg
->valid
&& reg
->exist
) {
800 core_addrs
[core_cnt
] = arc_reg
->arch_num
;
805 for (i
= arc
->num_core_regs
; i
< regs_to_scan
; i
++) {
806 struct reg
*reg
= &(reg_list
[i
]);
807 struct arc_reg_desc
*arc_reg
= reg
->arch_info
;
808 if (!reg
->valid
&& reg
->exist
) {
809 aux_addrs
[aux_cnt
] = arc_reg
->arch_num
;
814 /* Read data from target. */
816 retval
= arc_jtag_read_core_reg(&arc
->jtag_info
, core_addrs
, core_cnt
, core_values
);
817 if (ERROR_OK
!= retval
) {
818 LOG_ERROR("Attempt to read core registers failed.");
824 retval
= arc_jtag_read_aux_reg(&arc
->jtag_info
, aux_addrs
, aux_cnt
, aux_values
);
825 if (ERROR_OK
!= retval
) {
826 LOG_ERROR("Attempt to read aux registers failed.");
832 /* Parse core regs */
834 for (i
= 0; i
< MIN(arc
->num_core_regs
, regs_to_scan
); i
++) {
835 struct reg
*reg
= &(reg_list
[i
]);
836 struct arc_reg_desc
*arc_reg
= reg
->arch_info
;
837 if (!reg
->valid
&& reg
->exist
) {
838 target_buffer_set_u32(target
, reg
->value
, core_values
[core_cnt
]);
842 LOG_DEBUG("Get core register regnum=%" PRIu32
", name=%s, value=0x%08" PRIx32
,
843 i
, arc_reg
->name
, core_values
[core_cnt
]);
849 for (i
= arc
->num_core_regs
; i
< regs_to_scan
; i
++) {
850 struct reg
*reg
= &(reg_list
[i
]);
851 struct arc_reg_desc
*arc_reg
= reg
->arch_info
;
852 if (!reg
->valid
&& reg
->exist
) {
853 target_buffer_set_u32(target
, reg
->value
, aux_values
[aux_cnt
]);
857 LOG_DEBUG("Get aux register regnum=%" PRIu32
", name=%s, value=0x%08" PRIx32
,
858 i
, arc_reg
->name
, aux_values
[aux_cnt
]);
871 static int arc_examine_debug_reason(struct target
*target
)
875 /* Only check for reason if don't know it already. */
876 /* BTW After singlestep at this point core is not marked as halted, so
877 * reading from memory to get current instruction wouldn't work anyway. */
878 if (target
->debug_reason
== DBG_REASON_DBGRQ
||
879 target
->debug_reason
== DBG_REASON_SINGLESTEP
) {
883 CHECK_RETVAL(arc_reg_get_field(target
, "debug", "bh",
887 /* DEBUG.BH is set if core halted due to BRK instruction. */
888 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
890 /* TODO: Add Actionpoint check when AP support will be introduced*/
891 LOG_WARNING("Unknown debug reason");
897 static int arc_debug_entry(struct target
*target
)
899 CHECK_RETVAL(arc_save_context(target
));
901 /* TODO: reset internal indicators of caches states, otherwise D$/I$
902 * will not be flushed/invalidated when required. */
903 CHECK_RETVAL(arc_examine_debug_reason(target
));
908 static int arc_poll(struct target
*target
)
910 uint32_t status
, value
;
911 struct arc_common
*arc
= target_to_arc(target
);
913 /* gdb calls continuously through this arc_poll() function */
914 CHECK_RETVAL(arc_jtag_status(&arc
->jtag_info
, &status
));
916 /* check for processor halted */
917 if (status
& ARC_JTAG_STAT_RU
) {
918 if (target
->state
!= TARGET_RUNNING
) {
919 LOG_WARNING("target is still running!");
920 target
->state
= TARGET_RUNNING
;
924 /* In some cases JTAG status register indicates that
925 * processor is in halt mode, but processor is still running.
926 * We check halt bit of AUX STATUS32 register for setting correct state. */
927 if ((target
->state
== TARGET_RUNNING
) || (target
->state
== TARGET_RESET
)) {
928 CHECK_RETVAL(arc_get_register_value(target
, "status32", &value
));
929 if (value
& AUX_STATUS32_REG_HALT_BIT
) {
930 LOG_DEBUG("ARC core in halt or reset state.");
931 /* Save context if target was not in reset state */
932 if (target
->state
== TARGET_RUNNING
)
933 CHECK_RETVAL(arc_debug_entry(target
));
934 target
->state
= TARGET_HALTED
;
935 CHECK_RETVAL(target_call_event_callbacks(target
, TARGET_EVENT_HALTED
));
937 LOG_DEBUG("Discrepancy of STATUS32[0] HALT bit and ARC_JTAG_STAT_RU, "
938 "target is still running");
941 } else if (target
->state
== TARGET_DEBUG_RUNNING
) {
943 target
->state
= TARGET_HALTED
;
944 LOG_DEBUG("ARC core is in debug running mode");
946 CHECK_RETVAL(arc_debug_entry(target
));
948 CHECK_RETVAL(target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_HALTED
));
954 static int arc_assert_reset(struct target
*target
)
956 struct arc_common
*arc
= target_to_arc(target
);
957 enum reset_types jtag_reset_config
= jtag_get_reset_config();
958 bool srst_asserted
= false;
960 LOG_DEBUG("target->state: %s", target_state_name(target
));
962 if (target_has_event_action(target
, TARGET_EVENT_RESET_ASSERT
)) {
963 /* allow scripts to override the reset event */
965 target_handle_event(target
, TARGET_EVENT_RESET_ASSERT
);
966 register_cache_invalidate(arc
->core_and_aux_cache
);
967 /* An ARC target might be in halt state after reset, so
968 * if script requested processor to resume, then it must
969 * be manually started to ensure that this request
971 if (target
->state
== TARGET_HALTED
&& !target
->reset_halt
) {
972 /* Resume the target and continue from the current
973 * PC register value. */
974 LOG_DEBUG("Starting CPU execution after reset");
975 CHECK_RETVAL(target_resume(target
, 1, 0, 0, 0));
977 target
->state
= TARGET_RESET
;
982 /* some cores support connecting while srst is asserted
983 * use that mode if it has been configured */
984 if (!(jtag_reset_config
& RESET_SRST_PULLS_TRST
) &&
985 (jtag_reset_config
& RESET_SRST_NO_GATING
)) {
986 jtag_add_reset(0, 1);
987 srst_asserted
= true;
990 if (jtag_reset_config
& RESET_HAS_SRST
) {
991 /* should issue a srst only, but we may have to assert trst as well */
992 if (jtag_reset_config
& RESET_SRST_PULLS_TRST
)
993 jtag_add_reset(1, 1);
994 else if (!srst_asserted
)
995 jtag_add_reset(0, 1);
998 target
->state
= TARGET_RESET
;
999 jtag_add_sleep(50000);
1001 register_cache_invalidate(arc
->core_and_aux_cache
);
1003 if (target
->reset_halt
)
1004 CHECK_RETVAL(target_halt(target
));
1009 static int arc_deassert_reset(struct target
*target
)
1011 LOG_DEBUG("target->state: %s", target_state_name(target
));
1013 /* deassert reset lines */
1014 jtag_add_reset(0, 0);
1019 static int arc_arch_state(struct target
*target
)
1023 if (debug_level
< LOG_LVL_DEBUG
)
1026 CHECK_RETVAL(arc_get_register_value(target
, "pc", &pc_value
));
1028 LOG_DEBUG("target state: %s; PC at: 0x%08" PRIx32
,
1029 target_state_name(target
),
1036 * See arc_save_context() for reason why we want to dump all regs at once.
1037 * This however means that if there are dependencies between registers they
1038 * will not be observable until target will be resumed.
1040 static int arc_restore_context(struct target
*target
)
1042 int retval
= ERROR_OK
;
1044 struct arc_common
*arc
= target_to_arc(target
);
1045 struct reg
*reg_list
= arc
->core_and_aux_cache
->reg_list
;
1047 LOG_DEBUG("Restoring registers values");
1050 const uint32_t core_regs_size
= arc
->num_core_regs
* sizeof(uint32_t);
1051 const uint32_t aux_regs_size
= arc
->num_aux_regs
* sizeof(uint32_t);
1052 uint32_t *core_values
= malloc(core_regs_size
);
1053 uint32_t *aux_values
= malloc(aux_regs_size
);
1054 uint32_t *core_addrs
= malloc(core_regs_size
);
1055 uint32_t *aux_addrs
= malloc(aux_regs_size
);
1056 unsigned int core_cnt
= 0;
1057 unsigned int aux_cnt
= 0;
1059 if (!core_values
|| !core_addrs
|| !aux_values
|| !aux_addrs
) {
1060 LOG_ERROR("Unable to allocate memory");
1061 retval
= ERROR_FAIL
;
1065 memset(core_values
, 0xff, core_regs_size
);
1066 memset(core_addrs
, 0xff, core_regs_size
);
1067 memset(aux_values
, 0xff, aux_regs_size
);
1068 memset(aux_addrs
, 0xff, aux_regs_size
);
1070 for (i
= 0; i
< arc
->num_core_regs
; i
++) {
1071 struct reg
*reg
= &(reg_list
[i
]);
1072 struct arc_reg_desc
*arc_reg
= reg
->arch_info
;
1073 if (reg
->valid
&& reg
->exist
&& reg
->dirty
) {
1074 LOG_DEBUG("Will write regnum=%u", i
);
1075 core_addrs
[core_cnt
] = arc_reg
->arch_num
;
1076 core_values
[core_cnt
] = target_buffer_get_u32(target
, reg
->value
);
1081 for (i
= 0; i
< arc
->num_aux_regs
; i
++) {
1082 struct reg
*reg
= &(reg_list
[arc
->num_core_regs
+ i
]);
1083 struct arc_reg_desc
*arc_reg
= reg
->arch_info
;
1084 if (reg
->valid
&& reg
->exist
&& reg
->dirty
) {
1085 LOG_DEBUG("Will write regnum=%lu", arc
->num_core_regs
+ i
);
1086 aux_addrs
[aux_cnt
] = arc_reg
->arch_num
;
1087 aux_values
[aux_cnt
] = target_buffer_get_u32(target
, reg
->value
);
1092 /* Write data to target.
1093 * Check before write, if aux and core count is greater than 0. */
1095 retval
= arc_jtag_write_core_reg(&arc
->jtag_info
, core_addrs
, core_cnt
, core_values
);
1096 if (ERROR_OK
!= retval
) {
1097 LOG_ERROR("Attempt to write to core registers failed.");
1098 retval
= ERROR_FAIL
;
1104 retval
= arc_jtag_write_aux_reg(&arc
->jtag_info
, aux_addrs
, aux_cnt
, aux_values
);
1105 if (ERROR_OK
!= retval
) {
1106 LOG_ERROR("Attempt to write to aux registers failed.");
1107 retval
= ERROR_FAIL
;
1121 static int arc_enable_interrupts(struct target
*target
, int enable
)
1125 struct arc_common
*arc
= target_to_arc(target
);
1127 CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc
->jtag_info
, AUX_STATUS32_REG
, &value
));
1130 /* enable interrupts */
1131 value
|= SET_CORE_ENABLE_INTERRUPTS
;
1132 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc
->jtag_info
, AUX_STATUS32_REG
, value
));
1133 LOG_DEBUG("interrupts enabled");
1135 /* disable interrupts */
1136 value
&= ~SET_CORE_ENABLE_INTERRUPTS
;
1137 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc
->jtag_info
, AUX_STATUS32_REG
, value
));
1138 LOG_DEBUG("interrupts disabled");
1144 static int arc_resume(struct target
*target
, int current
, target_addr_t address
,
1145 int handle_breakpoints
, int debug_execution
)
1147 struct arc_common
*arc
= target_to_arc(target
);
1148 uint32_t resume_pc
= 0;
1150 struct reg
*pc
= &arc
->core_and_aux_cache
->reg_list
[arc
->pc_index_in_cache
];
1152 LOG_DEBUG("current:%i, address:0x%08" TARGET_PRIxADDR
", handle_breakpoints(not supported yet):%i,"
1153 " debug_execution:%i", current
, address
, handle_breakpoints
, debug_execution
);
1155 if (target
->state
!= TARGET_HALTED
) {
1156 LOG_WARNING("target not halted");
1157 return ERROR_TARGET_NOT_HALTED
;
1160 /* current = 1: continue on current PC, otherwise continue at <address> */
1162 target_buffer_set_u32(target
, pc
->value
, address
);
1165 LOG_DEBUG("Changing the value of current PC to 0x%08" TARGET_PRIxADDR
, address
);
1169 resume_pc
= address
;
1171 resume_pc
= target_buffer_get_u32(target
, pc
->value
);
1173 CHECK_RETVAL(arc_restore_context(target
));
1175 LOG_DEBUG("Target resumes from PC=0x%" PRIx32
", pc.dirty=%i, pc.valid=%i",
1176 resume_pc
, pc
->dirty
, pc
->valid
);
1178 /* check if GDB tells to set our PC where to continue from */
1179 if ((pc
->valid
== 1) && (resume_pc
== target_buffer_get_u32(target
, pc
->value
))) {
1180 value
= target_buffer_get_u32(target
, pc
->value
);
1181 LOG_DEBUG("resume Core (when start-core) with PC @:0x%08" PRIx32
, value
);
1182 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc
->jtag_info
, AUX_PC_REG
, value
));
1185 /* Restore IRQ state if not in debug_execution*/
1186 if (!debug_execution
)
1187 CHECK_RETVAL(arc_enable_interrupts(target
, arc
->irq_state
));
1189 CHECK_RETVAL(arc_enable_interrupts(target
, !debug_execution
));
1191 target
->debug_reason
= DBG_REASON_NOTHALTED
;
1193 /* ready to get us going again */
1194 target
->state
= TARGET_RUNNING
;
1195 CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc
->jtag_info
, AUX_STATUS32_REG
, &value
));
1196 value
&= ~SET_CORE_HALT_BIT
; /* clear the HALT bit */
1197 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc
->jtag_info
, AUX_STATUS32_REG
, value
));
1198 LOG_DEBUG("Core started to run");
1200 /* registers are now invalid */
1201 register_cache_invalidate(arc
->core_and_aux_cache
);
1203 if (!debug_execution
) {
1204 target
->state
= TARGET_RUNNING
;
1205 CHECK_RETVAL(target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
));
1206 LOG_DEBUG("target resumed at 0x%08" PRIx32
, resume_pc
);
1208 target
->state
= TARGET_DEBUG_RUNNING
;
1209 CHECK_RETVAL(target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_RESUMED
));
1210 LOG_DEBUG("target debug resumed at 0x%08" PRIx32
, resume_pc
);
1216 static int arc_init_target(struct command_context
*cmd_ctx
, struct target
*target
)
1218 CHECK_RETVAL(arc_build_reg_cache(target
));
1219 CHECK_RETVAL(arc_build_bcr_reg_cache(target
));
1220 target
->debug_reason
= DBG_REASON_DBGRQ
;
1224 static void arc_free_reg_cache(struct reg_cache
*cache
)
1226 free(cache
->reg_list
);
1230 static void arc_deinit_target(struct target
*target
)
1232 struct arc_common
*arc
= target_to_arc(target
);
1234 LOG_DEBUG("deinitialization of target");
1235 if (arc
->core_aux_cache_built
)
1236 arc_free_reg_cache(arc
->core_and_aux_cache
);
1237 if (arc
->bcr_cache_built
)
1238 arc_free_reg_cache(arc
->bcr_cache
);
1240 struct arc_reg_data_type
*type
, *n
;
1241 struct arc_reg_desc
*desc
, *k
;
1243 /* Free arc-specific reg_data_types allocations*/
1244 list_for_each_entry_safe_reverse(type
, n
, &arc
->reg_data_types
, list
) {
1245 if (type
->data_type
.type_class
== REG_TYPE_CLASS_STRUCT
) {
1246 free(type
->reg_type_struct_field
);
1247 free(type
->bitfields
);
1249 } else if (type
->data_type
.type_class
== REG_TYPE_CLASS_FLAGS
) {
1250 free(type
->reg_type_flags_field
);
1251 free(type
->bitfields
);
1256 /* Free standard_gdb_types reg_data_types allocations */
1257 type
= list_first_entry(&arc
->reg_data_types
, struct arc_reg_data_type
, list
);
1260 list_for_each_entry_safe(desc
, k
, &arc
->aux_reg_descriptions
, list
)
1261 free_reg_desc(desc
);
1263 list_for_each_entry_safe(desc
, k
, &arc
->core_reg_descriptions
, list
)
1264 free_reg_desc(desc
);
1266 list_for_each_entry_safe(desc
, k
, &arc
->bcr_reg_descriptions
, list
)
1267 free_reg_desc(desc
);
1273 static int arc_target_create(struct target
*target
, Jim_Interp
*interp
)
1275 struct arc_common
*arc
= calloc(1, sizeof(*arc
));
1278 LOG_ERROR("Unable to allocate memory");
1282 LOG_DEBUG("Entering");
1283 CHECK_RETVAL(arc_init_arch_info(target
, arc
, target
->tap
));
1289 * Write 4-byte instruction to memory. This is like target_write_u32, however
1290 * in case of little endian ARC instructions are in middle endian format, not
1291 * little endian, so different type of conversion should be done.
1292 * Middle endinan: instruction "aabbccdd", stored as "bbaaddcc"
1294 int arc_write_instruction_u32(struct target
*target
, uint32_t address
,
1297 uint8_t value_buf
[4];
1298 if (!target_was_examined(target
)) {
1299 LOG_ERROR("Target not examined yet");
1303 LOG_DEBUG("Address: 0x%08" PRIx32
", value: 0x%08" PRIx32
, address
,
1306 if (target
->endianness
== TARGET_LITTLE_ENDIAN
)
1307 arc_h_u32_to_me(value_buf
, instr
);
1309 h_u32_to_be(value_buf
, instr
);
1311 CHECK_RETVAL(target_write_buffer(target
, address
, 4, value_buf
));
1317 * Read 32-bit instruction from memory. It is like target_read_u32, however in
1318 * case of little endian ARC instructions are in middle endian format, so
1319 * different type of conversion should be done.
1321 int arc_read_instruction_u32(struct target
*target
, uint32_t address
,
1324 uint8_t value_buf
[4];
1326 if (!target_was_examined(target
)) {
1327 LOG_ERROR("Target not examined yet");
1332 CHECK_RETVAL(target_read_buffer(target
, address
, 4, value_buf
));
1334 if (target
->endianness
== TARGET_LITTLE_ENDIAN
)
1335 *value
= arc_me_to_h_u32(value_buf
);
1337 *value
= be_to_h_u32(value_buf
);
1339 LOG_DEBUG("Address: 0x%08" PRIx32
", value: 0x%08" PRIx32
, address
,
1345 static int arc_set_breakpoint(struct target
*target
,
1346 struct breakpoint
*breakpoint
)
1349 if (breakpoint
->set
) {
1350 LOG_WARNING("breakpoint already set");
1354 if (breakpoint
->type
== BKPT_SOFT
) {
1355 LOG_DEBUG("bpid: %" PRIu32
, breakpoint
->unique_id
);
1357 if (breakpoint
->length
== 4) {
1358 uint32_t verify
= 0xffffffff;
1360 CHECK_RETVAL(target_read_buffer(target
, breakpoint
->address
, breakpoint
->length
,
1361 breakpoint
->orig_instr
));
1363 CHECK_RETVAL(arc_write_instruction_u32(target
, breakpoint
->address
,
1366 CHECK_RETVAL(arc_read_instruction_u32(target
, breakpoint
->address
, &verify
));
1368 if (verify
!= ARC_SDBBP_32
) {
1369 LOG_ERROR("Unable to set 32bit breakpoint at address @0x%" TARGET_PRIxADDR
1370 " - check that memory is read/writable", breakpoint
->address
);
1373 } else if (breakpoint
->length
== 2) {
1374 uint16_t verify
= 0xffff;
1376 CHECK_RETVAL(target_read_buffer(target
, breakpoint
->address
, breakpoint
->length
,
1377 breakpoint
->orig_instr
));
1378 CHECK_RETVAL(target_write_u16(target
, breakpoint
->address
, ARC_SDBBP_16
));
1380 CHECK_RETVAL(target_read_u16(target
, breakpoint
->address
, &verify
));
1381 if (verify
!= ARC_SDBBP_16
) {
1382 LOG_ERROR("Unable to set 16bit breakpoint at address @0x%" TARGET_PRIxADDR
1383 " - check that memory is read/writable", breakpoint
->address
);
1387 LOG_ERROR("Invalid breakpoint length: target supports only 2 or 4");
1388 return ERROR_COMMAND_ARGUMENT_INVALID
;
1391 breakpoint
->set
= 64; /* Any nice value but 0 */
1392 } else if (breakpoint
->type
== BKPT_HARD
) {
1393 LOG_DEBUG("Hardware breakpoints are not supported yet!");
1396 LOG_DEBUG("ERROR: setting unknown breakpoint type");
1399 /* core instruction cache is now invalid,
1400 * TODO: add cache invalidation function here (when implemented). */
1405 static int arc_unset_breakpoint(struct target
*target
,
1406 struct breakpoint
*breakpoint
)
1408 int retval
= ERROR_OK
;
1410 if (!breakpoint
->set
) {
1411 LOG_WARNING("breakpoint not set");
1415 if (breakpoint
->type
== BKPT_SOFT
) {
1416 /* restore original instruction (kept in target endianness) */
1417 LOG_DEBUG("bpid: %" PRIu32
, breakpoint
->unique_id
);
1418 if (breakpoint
->length
== 4) {
1419 uint32_t current_instr
;
1421 /* check that user program has not modified breakpoint instruction */
1422 CHECK_RETVAL(arc_read_instruction_u32(target
, breakpoint
->address
, ¤t_instr
));
1424 if (current_instr
== ARC_SDBBP_32
) {
1425 retval
= target_write_buffer(target
, breakpoint
->address
,
1426 breakpoint
->length
, breakpoint
->orig_instr
);
1427 if (retval
!= ERROR_OK
)
1430 LOG_WARNING("Software breakpoint @0x%" TARGET_PRIxADDR
1431 " has been overwritten outside of debugger."
1432 "Expected: @0x%" PRIx32
", got: @0x%" PRIx32
,
1433 breakpoint
->address
, ARC_SDBBP_32
, current_instr
);
1435 } else if (breakpoint
->length
== 2) {
1436 uint16_t current_instr
;
1438 /* check that user program has not modified breakpoint instruction */
1439 CHECK_RETVAL(target_read_u16(target
, breakpoint
->address
, ¤t_instr
));
1440 if (current_instr
== ARC_SDBBP_16
) {
1441 retval
= target_write_buffer(target
, breakpoint
->address
,
1442 breakpoint
->length
, breakpoint
->orig_instr
);
1443 if (retval
!= ERROR_OK
)
1446 LOG_WARNING("Software breakpoint @0x%" TARGET_PRIxADDR
1447 " has been overwritten outside of debugger. "
1448 "Expected: 0x%04x, got: 0x%04" PRIx16
,
1449 breakpoint
->address
, ARC_SDBBP_16
, current_instr
);
1452 LOG_ERROR("Invalid breakpoint length: target supports only 2 or 4");
1453 return ERROR_COMMAND_ARGUMENT_INVALID
;
1455 breakpoint
->set
= 0;
1457 } else if (breakpoint
->type
== BKPT_HARD
) {
1458 LOG_WARNING("Hardware breakpoints are not supported yet!");
1461 LOG_DEBUG("ERROR: unsetting unknown breakpoint type");
1465 /* core instruction cache is now invalid.
1466 * TODO: Add cache invalidation function */
1472 static int arc_add_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1474 if (target
->state
== TARGET_HALTED
) {
1475 return arc_set_breakpoint(target
, breakpoint
);
1478 LOG_WARNING(" > core was not halted, please try again.");
1479 return ERROR_TARGET_NOT_HALTED
;
1483 static int arc_remove_breakpoint(struct target
*target
,
1484 struct breakpoint
*breakpoint
)
1486 if (target
->state
== TARGET_HALTED
) {
1487 if (breakpoint
->set
)
1488 CHECK_RETVAL(arc_unset_breakpoint(target
, breakpoint
));
1490 LOG_WARNING("target not halted");
1491 return ERROR_TARGET_NOT_HALTED
;
1497 /* Helper function which swiches core to single_step mode by
1498 * doing aux r/w operations. */
1499 int arc_config_step(struct target
*target
, int enable_step
)
1503 struct arc_common
*arc
= target_to_arc(target
);
1505 /* enable core debug step mode */
1507 CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc
->jtag_info
, AUX_STATUS32_REG
,
1509 value
&= ~SET_CORE_AE_BIT
; /* clear the AE bit */
1510 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc
->jtag_info
, AUX_STATUS32_REG
,
1512 LOG_DEBUG(" [status32:0x%08" PRIx32
"]", value
);
1514 /* Doing read-modify-write, because DEBUG might contain manually set
1515 * bits like UB or ED, which should be preserved. */
1516 CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc
->jtag_info
,
1517 AUX_DEBUG_REG
, &value
));
1518 value
|= SET_CORE_SINGLE_INSTR_STEP
; /* set the IS bit */
1519 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc
->jtag_info
, AUX_DEBUG_REG
,
1521 LOG_DEBUG("core debug step mode enabled [debug-reg:0x%08" PRIx32
"]", value
);
1523 } else { /* disable core debug step mode */
1524 CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc
->jtag_info
, AUX_DEBUG_REG
,
1526 value
&= ~SET_CORE_SINGLE_INSTR_STEP
; /* clear the IS bit */
1527 CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc
->jtag_info
, AUX_DEBUG_REG
,
1529 LOG_DEBUG("core debug step mode disabled");
1535 int arc_step(struct target
*target
, int current
, target_addr_t address
,
1536 int handle_breakpoints
)
1538 /* get pointers to arch-specific information */
1539 struct arc_common
*arc
= target_to_arc(target
);
1540 struct breakpoint
*breakpoint
= NULL
;
1541 struct reg
*pc
= &(arc
->core_and_aux_cache
->reg_list
[arc
->pc_index_in_cache
]);
1543 if (target
->state
!= TARGET_HALTED
) {
1544 LOG_WARNING("target not halted");
1545 return ERROR_TARGET_NOT_HALTED
;
1548 /* current = 1: continue on current pc, otherwise continue at <address> */
1550 buf_set_u32(pc
->value
, 0, 32, address
);
1555 LOG_DEBUG("Target steps one instruction from PC=0x%" PRIx32
,
1556 buf_get_u32(pc
->value
, 0, 32));
1558 /* the front-end may request us not to handle breakpoints */
1559 if (handle_breakpoints
) {
1560 breakpoint
= breakpoint_find(target
, buf_get_u32(pc
->value
, 0, 32));
1562 CHECK_RETVAL(arc_unset_breakpoint(target
, breakpoint
));
1565 /* restore context */
1566 CHECK_RETVAL(arc_restore_context(target
));
1568 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
1570 CHECK_RETVAL(target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
));
1572 /* disable interrupts while stepping */
1573 CHECK_RETVAL(arc_enable_interrupts(target
, 0));
1575 /* do a single step */
1576 CHECK_RETVAL(arc_config_step(target
, 1));
1578 /* make sure we done our step */
1581 /* registers are now invalid */
1582 register_cache_invalidate(arc
->core_and_aux_cache
);
1585 CHECK_RETVAL(arc_set_breakpoint(target
, breakpoint
));
1587 LOG_DEBUG("target stepped ");
1589 target
->state
= TARGET_HALTED
;
1591 /* Saving context */
1592 CHECK_RETVAL(arc_debug_entry(target
));
1593 CHECK_RETVAL(target_call_event_callbacks(target
, TARGET_EVENT_HALTED
));
1601 struct target_type arcv2_target
= {
1606 .arch_state
= arc_arch_state
,
1608 /* TODO That seems like something similiar to metaware hostlink, so perhaps
1609 * we can exploit this in the future. */
1610 .target_request_data
= NULL
,
1613 .resume
= arc_resume
,
1616 .assert_reset
= arc_assert_reset
,
1617 .deassert_reset
= arc_deassert_reset
,
1619 /* TODO Implement soft_reset_halt */
1620 .soft_reset_halt
= NULL
,
1622 .get_gdb_reg_list
= arc_get_gdb_reg_list
,
1624 .read_memory
= arc_mem_read
,
1625 .write_memory
= arc_mem_write
,
1626 .checksum_memory
= NULL
,
1627 .blank_check_memory
= NULL
,
1629 .add_breakpoint
= arc_add_breakpoint
,
1630 .add_context_breakpoint
= NULL
,
1631 .add_hybrid_breakpoint
= NULL
,
1632 .remove_breakpoint
= arc_remove_breakpoint
,
1633 .add_watchpoint
= NULL
,
1634 .remove_watchpoint
= NULL
,
1635 .hit_watchpoint
= NULL
,
1637 .run_algorithm
= NULL
,
1638 .start_algorithm
= NULL
,
1639 .wait_algorithm
= NULL
,
1641 .commands
= arc_monitor_command_handlers
,
1643 .target_create
= arc_target_create
,
1644 .init_target
= arc_init_target
,
1645 .deinit_target
= arc_deinit_target
,
1646 .examine
= arc_examine
,
1649 .read_phys_memory
= NULL
,
1650 .write_phys_memory
= NULL
,
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