src/target/adi_v5_swd.c

   1 /***************************************************************************
   2  *
   3  *   Copyright (C) 2010 by David Brownell
   4  *
   5  *   This program is free software; you can redistribute it and/or modify
   6  *   it under the terms of the GNU General Public License as published by
   7  *   the Free Software Foundation; either version 2 of the License, or
   8  *   (at your option) any later version.
   9  *
  10  *   This program is distributed in the hope that it will be useful,
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  *   GNU General Public License for more details.
  14  *
  15  *   You should have received a copy of the GNU General Public License
  16  *   along with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  ***************************************************************************/
  18
  19 /**
  20  * @file
  21  * Utilities to support ARM "Serial Wire Debug" (SWD), a low pin-count debug
  22  * link protocol used in cases where JTAG is not wanted.  This is coupled to
  23  * recent versions of ARM's "CoreSight" debug framework.  This specific code
  24  * is a transport level interface, with "target/arm_adi_v5.[hc]" code
  25  * understanding operation semantics, shared with the JTAG transport.
  26  *
  27  * Single-DAP support only.
  28  *
  29  * for details, see "ARM IHI 0031A"
  30  * ARM Debug Interface v5 Architecture Specification
  31  * especially section 5.3 for SWD protocol
  32  *
  33  * On many chips (most current Cortex-M3 parts) SWD is a run-time alternative
  34  * to JTAG.  Boards may support one or both.  There are also SWD-only chips,
  35  * (using SW-DP not SWJ-DP).
  36  *
  37  * Even boards that also support JTAG can benefit from SWD support, because
  38  * usually there's no way to access the SWO trace view mechanism in JTAG mode.
  39  * That is, trace access may require SWD support.
  40  *
  41  */
  42
  43 #ifdef HAVE_CONFIG_H
  44 #include "config.h"
  45 #endif
  46
  47 #include "arm.h"
  48 #include "arm_adi_v5.h"
  49 #include <helper/time_support.h>
  50
  51 #include <transport/transport.h>
  52 #include <jtag/interface.h>
  53
  54 #include <jtag/swd.h>
  55
  56 /* YUK! - but this is currently a global.... */
  57 extern struct jtag_interface *jtag_interface;
  58 static bool do_sync;
  59
  60 static void swd_finish_read(struct adiv5_dap *dap)
  61 {
  62         const struct swd_driver *swd = jtag_interface->swd;
  63         if (dap->last_read != NULL) {
  64                 swd->read_reg(swd_cmd(true, false, DP_RDBUFF), dap->last_read, 0);
  65                 dap->last_read = NULL;
  66         }
  67 }
  68
  69 static int swd_queue_dp_write(struct adiv5_dap *dap, unsigned reg,
  70                 uint32_t data);
  71 static int swd_queue_dp_read(struct adiv5_dap *dap, unsigned reg,
  72                 uint32_t *data);
  73
  74 static void swd_clear_sticky_errors(struct adiv5_dap *dap)
  75 {
  76         const struct swd_driver *swd = jtag_interface->swd;
  77         assert(swd);
  78
  79         swd->write_reg(swd_cmd(false,  false, DP_ABORT),
  80                 STKCMPCLR | STKERRCLR | WDERRCLR | ORUNERRCLR, 0);
  81 }
  82
  83 static int swd_run_inner(struct adiv5_dap *dap)
  84 {
  85         const struct swd_driver *swd = jtag_interface->swd;
  86         int retval;
  87
  88         retval = swd->run();
  89
  90         if (retval != ERROR_OK) {
  91                 /* fault response */
  92                 dap->do_reconnect = true;
  93         }
  94
  95         return retval;
  96 }
  97
  98 static int swd_connect(struct adiv5_dap *dap)
  99 {
 100         uint32_t dpidr;
 101         int status;
 102
 103         /* FIXME validate transport config ... is the
 104          * configured DAP present (check IDCODE)?
 105          * Is *only* one DAP configured?
 106          *
 107          * MUST READ DPIDR
 108          */
 109
 110         /* Note, debugport_init() does setup too */
 111         jtag_interface->swd->switch_seq(JTAG_TO_SWD);
 112
 113         /* Clear link state, including the SELECT cache. */
 114         dap->do_reconnect = false;
 115         dap->select = DP_SELECT_INVALID;
 116
 117         swd_queue_dp_read(dap, DP_DPIDR, &dpidr);
 118
 119         /* force clear all sticky faults */
 120         swd_clear_sticky_errors(dap);
 121
 122         status = swd_run_inner(dap);
 123
 124         if (status == ERROR_OK) {
 125                 LOG_INFO("SWD DPIDR %#8.8" PRIx32, dpidr);
 126                 dap->do_reconnect = false;
 127         } else
 128                 dap->do_reconnect = true;
 129
 130         return status;
 131 }
 132
 133 static inline int check_sync(struct adiv5_dap *dap)
 134 {
 135         return do_sync ? swd_run_inner(dap) : ERROR_OK;
 136 }
 137
 138 static int swd_check_reconnect(struct adiv5_dap *dap)
 139 {
 140         if (dap->do_reconnect)
 141                 return swd_connect(dap);
 142
 143         return ERROR_OK;
 144 }
 145
 146 static int swd_queue_ap_abort(struct adiv5_dap *dap, uint8_t *ack)
 147 {
 148         const struct swd_driver *swd = jtag_interface->swd;
 149         assert(swd);
 150
 151         swd->write_reg(swd_cmd(false,  false, DP_ABORT),
 152                 DAPABORT | STKCMPCLR | STKERRCLR | WDERRCLR | ORUNERRCLR, 0);
 153         return check_sync(dap);
 154 }
 155
 156 /** Select the DP register bank matching bits 7:4 of reg. */
 157 static void swd_queue_dp_bankselect(struct adiv5_dap *dap, unsigned reg)
 158 {
 159         /* Only register address 4 is banked. */
 160         if ((reg & 0xf) != 4)
 161                 return;
 162
 163         uint32_t select_dp_bank = (reg & 0x000000F0) >> 4;
 164         uint32_t sel = select_dp_bank
 165                         | (dap->select & (DP_SELECT_APSEL | DP_SELECT_APBANK));
 166
 167         if (sel == dap->select)
 168                 return;
 169
 170         dap->select = sel;
 171
 172         swd_queue_dp_write(dap, DP_SELECT, sel);
 173 }
 174
 175 static int swd_queue_dp_read(struct adiv5_dap *dap, unsigned reg,
 176                 uint32_t *data)
 177 {
 178         const struct swd_driver *swd = jtag_interface->swd;
 179         assert(swd);
 180
 181         int retval = swd_check_reconnect(dap);
 182         if (retval != ERROR_OK)
 183                 return retval;
 184
 185         swd_queue_dp_bankselect(dap, reg);
 186         swd->read_reg(swd_cmd(true,  false, reg), data, 0);
 187
 188         return check_sync(dap);
 189 }
 190
 191 static int swd_queue_dp_write(struct adiv5_dap *dap, unsigned reg,
 192                 uint32_t data)
 193 {
 194         const struct swd_driver *swd = jtag_interface->swd;
 195         assert(swd);
 196
 197         int retval = swd_check_reconnect(dap);
 198         if (retval != ERROR_OK)
 199                 return retval;
 200
 201         swd_finish_read(dap);
 202         swd_queue_dp_bankselect(dap, reg);
 203         swd->write_reg(swd_cmd(false,  false, reg), data, 0);
 204
 205         return check_sync(dap);
 206 }
 207
 208 /** Select the AP register bank matching bits 7:4 of reg. */
 209 static void swd_queue_ap_bankselect(struct adiv5_ap *ap, unsigned reg)
 210 {
 211         struct adiv5_dap *dap = ap->dap;
 212         uint32_t sel = ((uint32_t)ap->ap_num << 24)
 213                         | (reg & 0x000000F0)
 214                         | (dap->select & DP_SELECT_DPBANK);
 215
 216         if (sel == dap->select)
 217                 return;
 218
 219         dap->select = sel;
 220
 221         swd_queue_dp_write(dap, DP_SELECT, sel);
 222 }
 223
 224 static int swd_queue_ap_read(struct adiv5_ap *ap, unsigned reg,
 225                 uint32_t *data)
 226 {
 227         const struct swd_driver *swd = jtag_interface->swd;
 228         assert(swd);
 229
 230         struct adiv5_dap *dap = ap->dap;
 231
 232         int retval = swd_check_reconnect(dap);
 233         if (retval != ERROR_OK)
 234                 return retval;
 235
 236         swd_queue_ap_bankselect(ap, reg);
 237         swd->read_reg(swd_cmd(true,  true, reg), dap->last_read, ap->memaccess_tck);
 238         dap->last_read = data;
 239
 240         return check_sync(dap);
 241 }
 242
 243 static int swd_queue_ap_write(struct adiv5_ap *ap, unsigned reg,
 244                 uint32_t data)
 245 {
 246         const struct swd_driver *swd = jtag_interface->swd;
 247         assert(swd);
 248
 249         struct adiv5_dap *dap = ap->dap;
 250
 251         int retval = swd_check_reconnect(dap);
 252         if (retval != ERROR_OK)
 253                 return retval;
 254
 255         swd_finish_read(dap);
 256         swd_queue_ap_bankselect(ap, reg);
 257         swd->write_reg(swd_cmd(false,  true, reg), data, ap->memaccess_tck);
 258
 259         return check_sync(dap);
 260 }
 261
 262 /** Executes all queued DAP operations. */
 263 static int swd_run(struct adiv5_dap *dap)
 264 {
 265         swd_finish_read(dap);
 266         return swd_run_inner(dap);
 267 }
 268
 269 const struct dap_ops swd_dap_ops = {
 270         .queue_dp_read = swd_queue_dp_read,
 271         .queue_dp_write = swd_queue_dp_write,
 272         .queue_ap_read = swd_queue_ap_read,
 273         .queue_ap_write = swd_queue_ap_write,
 274         .queue_ap_abort = swd_queue_ap_abort,
 275         .run = swd_run,
 276 };
 277
 278 /*
 279  * This represents the bits which must be sent out on TMS/SWDIO to
 280  * switch a DAP implemented using an SWJ-DP module into SWD mode.
 281  * These bits are stored (and transmitted) LSB-first.
 282  *
 283  * See the DAP-Lite specification, section 2.2.5 for information
 284  * about making the debug link select SWD or JTAG.  (Similar info
 285  * is in a few other ARM documents.)
 286  */
 287 static const uint8_t jtag2swd_bitseq[] = {
 288         /* More than 50 TCK/SWCLK cycles with TMS/SWDIO high,
 289          * putting both JTAG and SWD logic into reset state.
 290          */
 291         0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 292         /* Switching sequence enables SWD and disables JTAG
 293          * NOTE: bits in the DP's IDCODE may expose the need for
 294          * an old/obsolete/deprecated sequence (0xb6 0xed).
 295          */
 296         0x9e, 0xe7,
 297         /* More than 50 TCK/SWCLK cycles with TMS/SWDIO high,
 298          * putting both JTAG and SWD logic into reset state.
 299          */
 300         0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 301 };
 302
 303 /**
 304  * Put the debug link into SWD mode, if the target supports it.
 305  * The link's initial mode may be either JTAG (for example,
 306  * with SWJ-DP after reset) or SWD.
 307  *
 308  * @param target Enters SWD mode (if possible).
 309  *
 310  * Note that targets using the JTAG-DP do not support SWD, and that
 311  * some targets which could otherwise support it may have have been
 312  * configured to disable SWD signaling
 313  *
 314  * @return ERROR_OK or else a fault code.
 315  */
 316 int dap_to_swd(struct target *target)
 317 {
 318         struct arm *arm = target_to_arm(target);
 319         int retval;
 320
 321         if (!arm->dap) {
 322                 LOG_ERROR("SWD mode is not available");
 323                 return ERROR_FAIL;
 324         }
 325
 326         LOG_DEBUG("Enter SWD mode");
 327
 328         /* REVISIT it's ugly to need to make calls to a "jtag"
 329          * subsystem if the link may not be in JTAG mode...
 330          */
 331
 332         retval =  jtag_add_tms_seq(8 * sizeof(jtag2swd_bitseq),
 333                         jtag2swd_bitseq, TAP_INVALID);
 334         if (retval == ERROR_OK)
 335                 retval = jtag_execute_queue();
 336
 337         /* set up the DAP's ops vector for SWD mode. */
 338         arm->dap->ops = &swd_dap_ops;
 339
 340         return retval;
 341 }
 342
 343 static const struct command_registration swd_commands[] = {
 344         {
 345                 /*
 346                  * Set up SWD and JTAG targets identically, unless/until
 347                  * infrastructure improves ...  meanwhile, ignore all
 348                  * JTAG-specific stuff like IR length for SWD.
 349                  *
 350                  * REVISIT can we verify "just one SWD DAP" here/early?
 351                  */
 352                 .name = "newdap",
 353                 .jim_handler = jim_jtag_newtap,
 354                 .mode = COMMAND_CONFIG,
 355                 .help = "declare a new SWD DAP"
 356         },
 357         COMMAND_REGISTRATION_DONE
 358 };
 359
 360 static const struct command_registration swd_handlers[] = {
 361         {
 362                 .name = "swd",
 363                 .mode = COMMAND_ANY,
 364                 .help = "SWD command group",
 365                 .chain = swd_commands,
 366         },
 367         COMMAND_REGISTRATION_DONE
 368 };
 369
 370 static int swd_select(struct command_context *ctx)
 371 {
 372         int retval;
 373
 374         retval = register_commands(ctx, NULL, swd_handlers);
 375
 376         if (retval != ERROR_OK)
 377                 return retval;
 378
 379         const struct swd_driver *swd = jtag_interface->swd;
 380
 381          /* be sure driver is in SWD mode; start
 382           * with hardware default TRN (1), it can be changed later
 383           */
 384         if (!swd || !swd->read_reg || !swd->write_reg || !swd->init) {
 385                 LOG_DEBUG("no SWD driver?");
 386                 return ERROR_FAIL;
 387         }
 388
 389         retval = swd->init();
 390         if (retval != ERROR_OK) {
 391                 LOG_DEBUG("can't init SWD driver");
 392                 return retval;
 393         }
 394
 395         /* force DAP into SWD mode (not JTAG) */
 396         /*retval = dap_to_swd(target);*/
 397
 398         if (ctx->current_target) {
 399                 /* force DAP into SWD mode (not JTAG) */
 400                 struct target *target = get_current_target(ctx);
 401                 retval = dap_to_swd(target);
 402         }
 403
 404         return retval;
 405 }
 406
 407 static int swd_init(struct command_context *ctx)
 408 {
 409         struct target *target = get_current_target(ctx);
 410         struct arm *arm = target_to_arm(target);
 411         struct adiv5_dap *dap = arm->dap;
 412         /* Force the DAP's ops vector for SWD mode.
 413          * messy - is there a better way? */
 414         arm->dap->ops = &swd_dap_ops;
 415
 416         return swd_connect(dap);
 417 }
 418
 419 static struct transport swd_transport = {
 420         .name = "swd",
 421         .select = swd_select,
 422         .init = swd_init,
 423 };
 424
 425 static void swd_constructor(void) __attribute__((constructor));
 426 static void swd_constructor(void)
 427 {
 428         transport_register(&swd_transport);
 429 }
 430
 431 /** Returns true if the current debug session
 432  * is using SWD as its transport.
 433  */
 434 bool transport_is_swd(void)
 435 {
 436         return get_current_transport() == &swd_transport;
 437 }