src/target/adi_v5_swd.c

   1 /***************************************************************************
   2  *
   3  *   Copyright (C) 2010 by David Brownell
   4  *
   5  *   This program is free software; you can redistribute it and/or modify
   6  *   it under the terms of the GNU General Public License as published by
   7  *   the Free Software Foundation; either version 2 of the License, or
   8  *   (at your option) any later version.
   9  *
  10  *   This program is distributed in the hope that it will be useful,
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  *   GNU General Public License for more details.
  14  *
  15  *   You should have received a copy of the GNU General Public License
  16  *   along with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  ***************************************************************************/
  18
  19 /**
  20  * @file
  21  * Utilities to support ARM "Serial Wire Debug" (SWD), a low pin-count debug
  22  * link protocol used in cases where JTAG is not wanted.  This is coupled to
  23  * recent versions of ARM's "CoreSight" debug framework.  This specific code
  24  * is a transport level interface, with "target/arm_adi_v5.[hc]" code
  25  * understanding operation semantics, shared with the JTAG transport.
  26  *
  27  * Single-DAP support only.
  28  *
  29  * for details, see "ARM IHI 0031A"
  30  * ARM Debug Interface v5 Architecture Specification
  31  * especially section 5.3 for SWD protocol
  32  *
  33  * On many chips (most current Cortex-M3 parts) SWD is a run-time alternative
  34  * to JTAG.  Boards may support one or both.  There are also SWD-only chips,
  35  * (using SW-DP not SWJ-DP).
  36  *
  37  * Even boards that also support JTAG can benefit from SWD support, because
  38  * usually there's no way to access the SWO trace view mechanism in JTAG mode.
  39  * That is, trace access may require SWD support.
  40  *
  41  */
  42
  43 #ifdef HAVE_CONFIG_H
  44 #include "config.h"
  45 #endif
  46
  47 #include "arm.h"
  48 #include "arm_adi_v5.h"
  49 #include <helper/time_support.h>
  50
  51 #include <transport/transport.h>
  52 #include <jtag/interface.h>
  53
  54 #include <jtag/swd.h>
  55
  56 static bool do_sync;
  57
  58 static void swd_finish_read(struct adiv5_dap *dap)
  59 {
  60         const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
  61         if (dap->last_read != NULL) {
  62                 swd->read_reg(swd_cmd(true, false, DP_RDBUFF), dap->last_read, 0);
  63                 dap->last_read = NULL;
  64         }
  65 }
  66
  67 static int swd_queue_dp_write(struct adiv5_dap *dap, unsigned reg,
  68                 uint32_t data);
  69 static int swd_queue_dp_read(struct adiv5_dap *dap, unsigned reg,
  70                 uint32_t *data);
  71
  72 static void swd_clear_sticky_errors(struct adiv5_dap *dap)
  73 {
  74         const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
  75         assert(swd);
  76
  77         swd->write_reg(swd_cmd(false,  false, DP_ABORT),
  78                 STKCMPCLR | STKERRCLR | WDERRCLR | ORUNERRCLR, 0);
  79 }
  80
  81 static int swd_run_inner(struct adiv5_dap *dap)
  82 {
  83         const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
  84         int retval;
  85
  86         retval = swd->run();
  87
  88         if (retval != ERROR_OK) {
  89                 /* fault response */
  90                 dap->do_reconnect = true;
  91         }
  92
  93         return retval;
  94 }
  95
  96 static int swd_connect(struct adiv5_dap *dap)
  97 {
  98         const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
  99         uint32_t dpidr = 0xdeadbeef;
 100         int status;
 101
 102         /* FIXME validate transport config ... is the
 103          * configured DAP present (check IDCODE)?
 104          * Is *only* one DAP configured?
 105          *
 106          * MUST READ DPIDR
 107          */
 108
 109         /* Check if we should reset srst already when connecting, but not if reconnecting. */
 110         if (!dap->do_reconnect) {
 111                 enum reset_types jtag_reset_config = jtag_get_reset_config();
 112
 113                 if (jtag_reset_config & RESET_CNCT_UNDER_SRST) {
 114                         if (jtag_reset_config & RESET_SRST_NO_GATING)
 115                                 adapter_assert_reset();
 116                         else
 117                                 LOG_WARNING("\'srst_nogate\' reset_config option is required");
 118                 }
 119         }
 120
 121         /* Note, debugport_init() does setup too */
 122         swd->switch_seq(JTAG_TO_SWD);
 123
 124         /* Clear link state, including the SELECT cache. */
 125         dap->do_reconnect = false;
 126         dap_invalidate_cache(dap);
 127
 128         swd_queue_dp_read(dap, DP_DPIDR, &dpidr);
 129
 130         /* force clear all sticky faults */
 131         swd_clear_sticky_errors(dap);
 132
 133         status = swd_run_inner(dap);
 134
 135         if (status == ERROR_OK) {
 136                 LOG_INFO("SWD DPIDR %#8.8" PRIx32, dpidr);
 137                 dap->do_reconnect = false;
 138                 status = dap_dp_init(dap);
 139         } else
 140                 dap->do_reconnect = true;
 141
 142         return status;
 143 }
 144
 145 static int swd_send_sequence(struct adiv5_dap *dap, enum swd_special_seq seq)
 146 {
 147         const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
 148         assert(swd);
 149
 150         return swd->switch_seq(seq);
 151 }
 152
 153 static inline int check_sync(struct adiv5_dap *dap)
 154 {
 155         return do_sync ? swd_run_inner(dap) : ERROR_OK;
 156 }
 157
 158 static int swd_check_reconnect(struct adiv5_dap *dap)
 159 {
 160         if (dap->do_reconnect)
 161                 return swd_connect(dap);
 162
 163         return ERROR_OK;
 164 }
 165
 166 static int swd_queue_ap_abort(struct adiv5_dap *dap, uint8_t *ack)
 167 {
 168         const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
 169         assert(swd);
 170
 171         swd->write_reg(swd_cmd(false,  false, DP_ABORT),
 172                 DAPABORT | STKCMPCLR | STKERRCLR | WDERRCLR | ORUNERRCLR, 0);
 173         return check_sync(dap);
 174 }
 175
 176 /** Select the DP register bank matching bits 7:4 of reg. */
 177 static int swd_queue_dp_bankselect(struct adiv5_dap *dap, unsigned reg)
 178 {
 179         /* Only register address 4 is banked. */
 180         if ((reg & 0xf) != 4)
 181                 return ERROR_OK;
 182
 183         uint32_t select_dp_bank = (reg & 0x000000F0) >> 4;
 184         uint32_t sel = select_dp_bank
 185                         | (dap->select & (DP_SELECT_APSEL | DP_SELECT_APBANK));
 186
 187         if (sel == dap->select)
 188                 return ERROR_OK;
 189
 190         dap->select = sel;
 191
 192         int retval = swd_queue_dp_write(dap, DP_SELECT, sel);
 193         if (retval != ERROR_OK)
 194                 dap->select = DP_SELECT_INVALID;
 195
 196         return retval;
 197 }
 198
 199 static int swd_queue_dp_read(struct adiv5_dap *dap, unsigned reg,
 200                 uint32_t *data)
 201 {
 202         const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
 203         assert(swd);
 204
 205         int retval = swd_check_reconnect(dap);
 206         if (retval != ERROR_OK)
 207                 return retval;
 208
 209         retval = swd_queue_dp_bankselect(dap, reg);
 210         if (retval != ERROR_OK)
 211                 return retval;
 212
 213         swd->read_reg(swd_cmd(true,  false, reg), data, 0);
 214
 215         return check_sync(dap);
 216 }
 217
 218 static int swd_queue_dp_write(struct adiv5_dap *dap, unsigned reg,
 219                 uint32_t data)
 220 {
 221         const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
 222         assert(swd);
 223
 224         int retval = swd_check_reconnect(dap);
 225         if (retval != ERROR_OK)
 226                 return retval;
 227
 228         swd_finish_read(dap);
 229         if (reg == DP_SELECT) {
 230                 dap->select = data & (DP_SELECT_APSEL | DP_SELECT_APBANK | DP_SELECT_DPBANK);
 231
 232                 swd->write_reg(swd_cmd(false,  false, reg), data, 0);
 233
 234                 retval = check_sync(dap);
 235                 if (retval != ERROR_OK)
 236                         dap->select = DP_SELECT_INVALID;
 237
 238                 return retval;
 239         }
 240
 241         retval = swd_queue_dp_bankselect(dap, reg);
 242         if (retval != ERROR_OK)
 243                 return retval;
 244
 245         swd->write_reg(swd_cmd(false,  false, reg), data, 0);
 246
 247         return check_sync(dap);
 248 }
 249
 250 /** Select the AP register bank matching bits 7:4 of reg. */
 251 static int swd_queue_ap_bankselect(struct adiv5_ap *ap, unsigned reg)
 252 {
 253         struct adiv5_dap *dap = ap->dap;
 254         uint32_t sel = ((uint32_t)ap->ap_num << 24)
 255                         | (reg & 0x000000F0)
 256                         | (dap->select & DP_SELECT_DPBANK);
 257
 258         if (sel == dap->select)
 259                 return ERROR_OK;
 260
 261         dap->select = sel;
 262
 263         int retval = swd_queue_dp_write(dap, DP_SELECT, sel);
 264         if (retval != ERROR_OK)
 265                 dap->select = DP_SELECT_INVALID;
 266
 267         return retval;
 268 }
 269
 270 static int swd_queue_ap_read(struct adiv5_ap *ap, unsigned reg,
 271                 uint32_t *data)
 272 {
 273         struct adiv5_dap *dap = ap->dap;
 274         const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
 275         assert(swd);
 276
 277         int retval = swd_check_reconnect(dap);
 278         if (retval != ERROR_OK)
 279                 return retval;
 280
 281         retval = swd_queue_ap_bankselect(ap, reg);
 282         if (retval != ERROR_OK)
 283                 return retval;
 284
 285         swd->read_reg(swd_cmd(true,  true, reg), dap->last_read, ap->memaccess_tck);
 286         dap->last_read = data;
 287
 288         return check_sync(dap);
 289 }
 290
 291 static int swd_queue_ap_write(struct adiv5_ap *ap, unsigned reg,
 292                 uint32_t data)
 293 {
 294         struct adiv5_dap *dap = ap->dap;
 295         const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
 296         assert(swd);
 297
 298         int retval = swd_check_reconnect(dap);
 299         if (retval != ERROR_OK)
 300                 return retval;
 301
 302         swd_finish_read(dap);
 303         retval = swd_queue_ap_bankselect(ap, reg);
 304         if (retval != ERROR_OK)
 305                 return retval;
 306
 307         swd->write_reg(swd_cmd(false,  true, reg), data, ap->memaccess_tck);
 308
 309         return check_sync(dap);
 310 }
 311
 312 /** Executes all queued DAP operations. */
 313 static int swd_run(struct adiv5_dap *dap)
 314 {
 315         swd_finish_read(dap);
 316         return swd_run_inner(dap);
 317 }
 318
 319 /** Put the SWJ-DP back to JTAG mode */
 320 static void swd_quit(struct adiv5_dap *dap)
 321 {
 322         const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
 323
 324         swd->switch_seq(SWD_TO_JTAG);
 325         /* flush the queue before exit */
 326         swd->run();
 327 }
 328
 329 const struct dap_ops swd_dap_ops = {
 330         .connect = swd_connect,
 331         .send_sequence = swd_send_sequence,
 332         .queue_dp_read = swd_queue_dp_read,
 333         .queue_dp_write = swd_queue_dp_write,
 334         .queue_ap_read = swd_queue_ap_read,
 335         .queue_ap_write = swd_queue_ap_write,
 336         .queue_ap_abort = swd_queue_ap_abort,
 337         .run = swd_run,
 338         .quit = swd_quit,
 339 };
 340
 341 static const struct command_registration swd_commands[] = {
 342         {
 343                 /*
 344                  * Set up SWD and JTAG targets identically, unless/until
 345                  * infrastructure improves ...  meanwhile, ignore all
 346                  * JTAG-specific stuff like IR length for SWD.
 347                  *
 348                  * REVISIT can we verify "just one SWD DAP" here/early?
 349                  */
 350                 .name = "newdap",
 351                 .jim_handler = jim_jtag_newtap,
 352                 .mode = COMMAND_CONFIG,
 353                 .help = "declare a new SWD DAP"
 354         },
 355         COMMAND_REGISTRATION_DONE
 356 };
 357
 358 static const struct command_registration swd_handlers[] = {
 359         {
 360                 .name = "swd",
 361                 .mode = COMMAND_ANY,
 362                 .help = "SWD command group",
 363                 .chain = swd_commands,
 364                 .usage = "",
 365         },
 366         COMMAND_REGISTRATION_DONE
 367 };
 368
 369 static int swd_select(struct command_context *ctx)
 370 {
 371         /* FIXME: only place where global 'adapter_driver' is still needed */
 372         extern struct adapter_driver *adapter_driver;
 373         const struct swd_driver *swd = adapter_driver->swd_ops;
 374         int retval;
 375
 376         retval = register_commands(ctx, NULL, swd_handlers);
 377         if (retval != ERROR_OK)
 378                 return retval;
 379
 380          /* be sure driver is in SWD mode; start
 381           * with hardware default TRN (1), it can be changed later
 382           */
 383         if (!swd || !swd->read_reg || !swd->write_reg || !swd->init) {
 384                 LOG_DEBUG("no SWD driver?");
 385                 return ERROR_FAIL;
 386         }
 387
 388         retval = swd->init();
 389         if (retval != ERROR_OK) {
 390                 LOG_DEBUG("can't init SWD driver");
 391                 return retval;
 392         }
 393
 394         return retval;
 395 }
 396
 397 static int swd_init(struct command_context *ctx)
 398 {
 399         /* nothing done here, SWD is initialized
 400          * together with the DAP */
 401         return ERROR_OK;
 402 }
 403
 404 static struct transport swd_transport = {
 405         .name = "swd",
 406         .select = swd_select,
 407         .init = swd_init,
 408 };
 409
 410 static void swd_constructor(void) __attribute__((constructor));
 411 static void swd_constructor(void)
 412 {
 413         transport_register(&swd_transport);
 414 }
 415
 416 /** Returns true if the current debug session
 417  * is using SWD as its transport.
 418  */
 419 bool transport_is_swd(void)
 420 {
 421         return get_current_transport() == &swd_transport;
 422 }