target/adi_v5_swd: update cached value on write to DP_SELECT
[openocd.git] / src / target / adi_v5_swd.c
1 /***************************************************************************
2 *
3 * Copyright (C) 2010 by David Brownell
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 ***************************************************************************/
18
19 /**
20 * @file
21 * Utilities to support ARM "Serial Wire Debug" (SWD), a low pin-count debug
22 * link protocol used in cases where JTAG is not wanted. This is coupled to
23 * recent versions of ARM's "CoreSight" debug framework. This specific code
24 * is a transport level interface, with "target/arm_adi_v5.[hc]" code
25 * understanding operation semantics, shared with the JTAG transport.
26 *
27 * Single-DAP support only.
28 *
29 * for details, see "ARM IHI 0031A"
30 * ARM Debug Interface v5 Architecture Specification
31 * especially section 5.3 for SWD protocol
32 *
33 * On many chips (most current Cortex-M3 parts) SWD is a run-time alternative
34 * to JTAG. Boards may support one or both. There are also SWD-only chips,
35 * (using SW-DP not SWJ-DP).
36 *
37 * Even boards that also support JTAG can benefit from SWD support, because
38 * usually there's no way to access the SWO trace view mechanism in JTAG mode.
39 * That is, trace access may require SWD support.
40 *
41 */
42
43 #ifdef HAVE_CONFIG_H
44 #include "config.h"
45 #endif
46
47 #include "arm.h"
48 #include "arm_adi_v5.h"
49 #include <helper/time_support.h>
50
51 #include <transport/transport.h>
52 #include <jtag/interface.h>
53
54 #include <jtag/swd.h>
55
56 static bool do_sync;
57
58 static void swd_finish_read(struct adiv5_dap *dap)
59 {
60 const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
61 if (dap->last_read != NULL) {
62 swd->read_reg(swd_cmd(true, false, DP_RDBUFF), dap->last_read, 0);
63 dap->last_read = NULL;
64 }
65 }
66
67 static int swd_queue_dp_write(struct adiv5_dap *dap, unsigned reg,
68 uint32_t data);
69 static int swd_queue_dp_read(struct adiv5_dap *dap, unsigned reg,
70 uint32_t *data);
71
72 static void swd_clear_sticky_errors(struct adiv5_dap *dap)
73 {
74 const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
75 assert(swd);
76
77 swd->write_reg(swd_cmd(false, false, DP_ABORT),
78 STKCMPCLR | STKERRCLR | WDERRCLR | ORUNERRCLR, 0);
79 }
80
81 static int swd_run_inner(struct adiv5_dap *dap)
82 {
83 const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
84 int retval;
85
86 retval = swd->run();
87
88 if (retval != ERROR_OK) {
89 /* fault response */
90 dap->do_reconnect = true;
91 }
92
93 return retval;
94 }
95
96 static int swd_connect(struct adiv5_dap *dap)
97 {
98 const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
99 uint32_t dpidr;
100 int status;
101
102 /* FIXME validate transport config ... is the
103 * configured DAP present (check IDCODE)?
104 * Is *only* one DAP configured?
105 *
106 * MUST READ DPIDR
107 */
108
109 /* Check if we should reset srst already when connecting, but not if reconnecting. */
110 if (!dap->do_reconnect) {
111 enum reset_types jtag_reset_config = jtag_get_reset_config();
112
113 if (jtag_reset_config & RESET_CNCT_UNDER_SRST) {
114 if (jtag_reset_config & RESET_SRST_NO_GATING)
115 swd_add_reset(1);
116 else
117 LOG_WARNING("\'srst_nogate\' reset_config option is required");
118 }
119 }
120
121 /* Note, debugport_init() does setup too */
122 swd->switch_seq(JTAG_TO_SWD);
123
124 /* Clear link state, including the SELECT cache. */
125 dap->do_reconnect = false;
126 dap_invalidate_cache(dap);
127
128 swd_queue_dp_read(dap, DP_DPIDR, &dpidr);
129
130 /* force clear all sticky faults */
131 swd_clear_sticky_errors(dap);
132
133 status = swd_run_inner(dap);
134
135 if (status == ERROR_OK) {
136 LOG_INFO("SWD DPIDR %#8.8" PRIx32, dpidr);
137 dap->do_reconnect = false;
138 status = dap_dp_init(dap);
139 } else
140 dap->do_reconnect = true;
141
142 return status;
143 }
144
145 static inline int check_sync(struct adiv5_dap *dap)
146 {
147 return do_sync ? swd_run_inner(dap) : ERROR_OK;
148 }
149
150 static int swd_check_reconnect(struct adiv5_dap *dap)
151 {
152 if (dap->do_reconnect)
153 return swd_connect(dap);
154
155 return ERROR_OK;
156 }
157
158 static int swd_queue_ap_abort(struct adiv5_dap *dap, uint8_t *ack)
159 {
160 const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
161 assert(swd);
162
163 swd->write_reg(swd_cmd(false, false, DP_ABORT),
164 DAPABORT | STKCMPCLR | STKERRCLR | WDERRCLR | ORUNERRCLR, 0);
165 return check_sync(dap);
166 }
167
168 /** Select the DP register bank matching bits 7:4 of reg. */
169 static void swd_queue_dp_bankselect(struct adiv5_dap *dap, unsigned reg)
170 {
171 /* Only register address 4 is banked. */
172 if ((reg & 0xf) != 4)
173 return;
174
175 uint32_t select_dp_bank = (reg & 0x000000F0) >> 4;
176 uint32_t sel = select_dp_bank
177 | (dap->select & (DP_SELECT_APSEL | DP_SELECT_APBANK));
178
179 if (sel == dap->select)
180 return;
181
182 dap->select = sel;
183
184 swd_queue_dp_write(dap, DP_SELECT, sel);
185 }
186
187 static int swd_queue_dp_read(struct adiv5_dap *dap, unsigned reg,
188 uint32_t *data)
189 {
190 const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
191 assert(swd);
192
193 int retval = swd_check_reconnect(dap);
194 if (retval != ERROR_OK)
195 return retval;
196
197 swd_queue_dp_bankselect(dap, reg);
198 swd->read_reg(swd_cmd(true, false, reg), data, 0);
199
200 return check_sync(dap);
201 }
202
203 static int swd_queue_dp_write(struct adiv5_dap *dap, unsigned reg,
204 uint32_t data)
205 {
206 const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
207 assert(swd);
208
209 int retval = swd_check_reconnect(dap);
210 if (retval != ERROR_OK)
211 return retval;
212
213 swd_finish_read(dap);
214 if (reg == DP_SELECT)
215 dap->select = data & (DP_SELECT_APSEL | DP_SELECT_APBANK | DP_SELECT_DPBANK);
216 else
217 swd_queue_dp_bankselect(dap, reg);
218 swd->write_reg(swd_cmd(false, false, reg), data, 0);
219
220 return check_sync(dap);
221 }
222
223 /** Select the AP register bank matching bits 7:4 of reg. */
224 static void swd_queue_ap_bankselect(struct adiv5_ap *ap, unsigned reg)
225 {
226 struct adiv5_dap *dap = ap->dap;
227 uint32_t sel = ((uint32_t)ap->ap_num << 24)
228 | (reg & 0x000000F0)
229 | (dap->select & DP_SELECT_DPBANK);
230
231 if (sel == dap->select)
232 return;
233
234 dap->select = sel;
235
236 swd_queue_dp_write(dap, DP_SELECT, sel);
237 }
238
239 static int swd_queue_ap_read(struct adiv5_ap *ap, unsigned reg,
240 uint32_t *data)
241 {
242 struct adiv5_dap *dap = ap->dap;
243 const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
244 assert(swd);
245
246 int retval = swd_check_reconnect(dap);
247 if (retval != ERROR_OK)
248 return retval;
249
250 swd_queue_ap_bankselect(ap, reg);
251 swd->read_reg(swd_cmd(true, true, reg), dap->last_read, ap->memaccess_tck);
252 dap->last_read = data;
253
254 return check_sync(dap);
255 }
256
257 static int swd_queue_ap_write(struct adiv5_ap *ap, unsigned reg,
258 uint32_t data)
259 {
260 struct adiv5_dap *dap = ap->dap;
261 const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
262 assert(swd);
263
264 int retval = swd_check_reconnect(dap);
265 if (retval != ERROR_OK)
266 return retval;
267
268 swd_finish_read(dap);
269 swd_queue_ap_bankselect(ap, reg);
270 swd->write_reg(swd_cmd(false, true, reg), data, ap->memaccess_tck);
271
272 return check_sync(dap);
273 }
274
275 /** Executes all queued DAP operations. */
276 static int swd_run(struct adiv5_dap *dap)
277 {
278 swd_finish_read(dap);
279 return swd_run_inner(dap);
280 }
281
282 /** Put the SWJ-DP back to JTAG mode */
283 static void swd_quit(struct adiv5_dap *dap)
284 {
285 const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
286
287 swd->switch_seq(SWD_TO_JTAG);
288 /* flush the queue before exit */
289 swd->run();
290 }
291
292 const struct dap_ops swd_dap_ops = {
293 .connect = swd_connect,
294 .queue_dp_read = swd_queue_dp_read,
295 .queue_dp_write = swd_queue_dp_write,
296 .queue_ap_read = swd_queue_ap_read,
297 .queue_ap_write = swd_queue_ap_write,
298 .queue_ap_abort = swd_queue_ap_abort,
299 .run = swd_run,
300 .quit = swd_quit,
301 };
302
303 static const struct command_registration swd_commands[] = {
304 {
305 /*
306 * Set up SWD and JTAG targets identically, unless/until
307 * infrastructure improves ... meanwhile, ignore all
308 * JTAG-specific stuff like IR length for SWD.
309 *
310 * REVISIT can we verify "just one SWD DAP" here/early?
311 */
312 .name = "newdap",
313 .jim_handler = jim_jtag_newtap,
314 .mode = COMMAND_CONFIG,
315 .help = "declare a new SWD DAP"
316 },
317 COMMAND_REGISTRATION_DONE
318 };
319
320 static const struct command_registration swd_handlers[] = {
321 {
322 .name = "swd",
323 .mode = COMMAND_ANY,
324 .help = "SWD command group",
325 .chain = swd_commands,
326 },
327 COMMAND_REGISTRATION_DONE
328 };
329
330 static int swd_select(struct command_context *ctx)
331 {
332 /* FIXME: only place where global 'jtag_interface' is still needed */
333 extern struct jtag_interface *jtag_interface;
334 const struct swd_driver *swd = jtag_interface->swd;
335 int retval;
336
337 retval = register_commands(ctx, NULL, swd_handlers);
338 if (retval != ERROR_OK)
339 return retval;
340
341 /* be sure driver is in SWD mode; start
342 * with hardware default TRN (1), it can be changed later
343 */
344 if (!swd || !swd->read_reg || !swd->write_reg || !swd->init) {
345 LOG_DEBUG("no SWD driver?");
346 return ERROR_FAIL;
347 }
348
349 retval = swd->init();
350 if (retval != ERROR_OK) {
351 LOG_DEBUG("can't init SWD driver");
352 return retval;
353 }
354
355 return retval;
356 }
357
358 static int swd_init(struct command_context *ctx)
359 {
360 /* nothing done here, SWD is initialized
361 * together with the DAP */
362 return ERROR_OK;
363 }
364
365 static struct transport swd_transport = {
366 .name = "swd",
367 .select = swd_select,
368 .init = swd_init,
369 };
370
371 static void swd_constructor(void) __attribute__((constructor));
372 static void swd_constructor(void)
373 {
374 transport_register(&swd_transport);
375 }
376
377 /** Returns true if the current debug session
378 * is using SWD as its transport.
379 */
380 bool transport_is_swd(void)
381 {
382 return get_current_transport() == &swd_transport;
383 }