arm_adi_v5: Make the DAP API stateless
[openocd.git] / src / target / adi_v5_swd.c
1 /***************************************************************************
2 *
3 * Copyright (C) 2010 by David Brownell
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the
17 * Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 ***************************************************************************/
20
21 /**
22 * @file
23 * Utilities to support ARM "Serial Wire Debug" (SWD), a low pin-count debug
24 * link protocol used in cases where JTAG is not wanted. This is coupled to
25 * recent versions of ARM's "CoreSight" debug framework. This specific code
26 * is a transport level interface, with "target/arm_adi_v5.[hc]" code
27 * understanding operation semantics, shared with the JTAG transport.
28 *
29 * Single-DAP support only.
30 *
31 * for details, see "ARM IHI 0031A"
32 * ARM Debug Interface v5 Architecture Specification
33 * especially section 5.3 for SWD protocol
34 *
35 * On many chips (most current Cortex-M3 parts) SWD is a run-time alternative
36 * to JTAG. Boards may support one or both. There are also SWD-only chips,
37 * (using SW-DP not SWJ-DP).
38 *
39 * Even boards that also support JTAG can benefit from SWD support, because
40 * usually there's no way to access the SWO trace view mechanism in JTAG mode.
41 * That is, trace access may require SWD support.
42 *
43 */
44
45 #ifdef HAVE_CONFIG_H
46 #include "config.h"
47 #endif
48
49 #include "arm.h"
50 #include "arm_adi_v5.h"
51 #include <helper/time_support.h>
52
53 #include <transport/transport.h>
54 #include <jtag/interface.h>
55
56 #include <jtag/swd.h>
57
58 /* YUK! - but this is currently a global.... */
59 extern struct jtag_interface *jtag_interface;
60 static bool do_sync;
61
62 static void swd_finish_read(struct adiv5_dap *dap)
63 {
64 const struct swd_driver *swd = jtag_interface->swd;
65 if (dap->last_read != NULL) {
66 swd->read_reg(swd_cmd(true, false, DP_RDBUFF), dap->last_read, 0);
67 dap->last_read = NULL;
68 }
69 }
70
71 static int swd_queue_dp_write(struct adiv5_dap *dap, unsigned reg,
72 uint32_t data);
73 static int swd_queue_dp_read(struct adiv5_dap *dap, unsigned reg,
74 uint32_t *data);
75
76 static void swd_clear_sticky_errors(struct adiv5_dap *dap)
77 {
78 const struct swd_driver *swd = jtag_interface->swd;
79 assert(swd);
80
81 swd->write_reg(swd_cmd(false, false, DP_ABORT),
82 STKCMPCLR | STKERRCLR | WDERRCLR | ORUNERRCLR, 0);
83 }
84
85 static int swd_run_inner(struct adiv5_dap *dap)
86 {
87 const struct swd_driver *swd = jtag_interface->swd;
88 int retval;
89
90 retval = swd->run();
91
92 if (retval != ERROR_OK) {
93 /* fault response */
94 dap->do_reconnect = true;
95 }
96
97 return retval;
98 }
99
100 static int swd_connect(struct adiv5_dap *dap)
101 {
102 uint32_t idcode;
103 int status;
104
105 /* FIXME validate transport config ... is the
106 * configured DAP present (check IDCODE)?
107 * Is *only* one DAP configured?
108 *
109 * MUST READ IDCODE
110 */
111
112 /* Note, debugport_init() does setup too */
113 jtag_interface->swd->switch_seq(JTAG_TO_SWD);
114
115 /* Make sure we don't try to perform any other accesses before the DPIDR read. */
116 dap->do_reconnect = false;
117 dap->select = 0;
118
119 swd_queue_dp_read(dap, DP_IDCODE, &idcode);
120
121 /* force clear all sticky faults */
122 swd_clear_sticky_errors(dap);
123
124 status = swd_run_inner(dap);
125
126 if (status == ERROR_OK) {
127 LOG_INFO("SWD IDCODE %#8.8" PRIx32, idcode);
128 dap->do_reconnect = false;
129 } else
130 dap->do_reconnect = true;
131
132 return status;
133 }
134
135 static inline int check_sync(struct adiv5_dap *dap)
136 {
137 return do_sync ? swd_run_inner(dap) : ERROR_OK;
138 }
139
140 static int swd_check_reconnect(struct adiv5_dap *dap)
141 {
142 if (dap->do_reconnect)
143 return swd_connect(dap);
144
145 return ERROR_OK;
146 }
147
148 static int swd_queue_ap_abort(struct adiv5_dap *dap, uint8_t *ack)
149 {
150 const struct swd_driver *swd = jtag_interface->swd;
151 assert(swd);
152
153 swd->write_reg(swd_cmd(false, false, DP_ABORT),
154 DAPABORT | STKCMPCLR | STKERRCLR | WDERRCLR | ORUNERRCLR, 0);
155 return check_sync(dap);
156 }
157
158 /** Select the DP register bank matching bits 7:4 of reg. */
159 static void swd_queue_dp_bankselect(struct adiv5_dap *dap, unsigned reg)
160 {
161 if (reg == DP_SELECT)
162 return;
163
164 uint32_t select_dp_bank = (reg & 0x000000F0) >> 4;
165 uint32_t select = select_dp_bank
166 | (dap->select & (DP_SELECT_APSEL | DP_SELECT_APBANK));
167
168 if (select == dap->select)
169 return;
170
171 dap->select = select;
172
173 swd_queue_dp_write(dap, DP_SELECT, select);
174 }
175
176 static int swd_queue_dp_read(struct adiv5_dap *dap, unsigned reg,
177 uint32_t *data)
178 {
179 const struct swd_driver *swd = jtag_interface->swd;
180 assert(swd);
181
182 int retval = swd_check_reconnect(dap);
183 if (retval != ERROR_OK)
184 return retval;
185
186 swd_queue_dp_bankselect(dap, reg);
187 swd->read_reg(swd_cmd(true, false, reg), data, 0);
188
189 return check_sync(dap);
190 }
191
192 static int swd_queue_dp_write(struct adiv5_dap *dap, unsigned reg,
193 uint32_t data)
194 {
195 const struct swd_driver *swd = jtag_interface->swd;
196 assert(swd);
197
198 int retval = swd_check_reconnect(dap);
199 if (retval != ERROR_OK)
200 return retval;
201
202 swd_finish_read(dap);
203 swd_queue_dp_bankselect(dap, reg);
204 swd->write_reg(swd_cmd(false, false, reg), data, 0);
205
206 return check_sync(dap);
207 }
208
209 /** Select the AP register bank matching bits 7:4 of reg. */
210 static void swd_queue_ap_bankselect(struct adiv5_ap *ap, unsigned reg)
211 {
212 struct adiv5_dap *dap = ap->dap;
213 uint32_t select = ((uint32_t)ap->ap_num << 24)
214 | (reg & 0x000000F0)
215 | (dap->select & DP_SELECT_DPBANK);
216
217 if (select == dap->select)
218 return;
219
220 dap->select = select;
221
222 swd_queue_dp_write(dap, DP_SELECT, select);
223 }
224
225 static int swd_queue_ap_read(struct adiv5_ap *ap, unsigned reg,
226 uint32_t *data)
227 {
228 const struct swd_driver *swd = jtag_interface->swd;
229 assert(swd);
230
231 struct adiv5_dap *dap = ap->dap;
232
233 int retval = swd_check_reconnect(dap);
234 if (retval != ERROR_OK)
235 return retval;
236
237 swd_queue_ap_bankselect(ap, reg);
238 swd->read_reg(swd_cmd(true, true, reg), dap->last_read, ap->memaccess_tck);
239 dap->last_read = data;
240
241 return check_sync(dap);
242 }
243
244 static int swd_queue_ap_write(struct adiv5_ap *ap, unsigned reg,
245 uint32_t data)
246 {
247 const struct swd_driver *swd = jtag_interface->swd;
248 assert(swd);
249
250 struct adiv5_dap *dap = ap->dap;
251
252 int retval = swd_check_reconnect(dap);
253 if (retval != ERROR_OK)
254 return retval;
255
256 swd_finish_read(dap);
257 swd_queue_ap_bankselect(ap, reg);
258 swd->write_reg(swd_cmd(false, true, reg), data, ap->memaccess_tck);
259
260 return check_sync(dap);
261 }
262
263 /** Executes all queued DAP operations. */
264 static int swd_run(struct adiv5_dap *dap)
265 {
266 swd_finish_read(dap);
267 return swd_run_inner(dap);
268 }
269
270 const struct dap_ops swd_dap_ops = {
271 .queue_dp_read = swd_queue_dp_read,
272 .queue_dp_write = swd_queue_dp_write,
273 .queue_ap_read = swd_queue_ap_read,
274 .queue_ap_write = swd_queue_ap_write,
275 .queue_ap_abort = swd_queue_ap_abort,
276 .run = swd_run,
277 };
278
279 /*
280 * This represents the bits which must be sent out on TMS/SWDIO to
281 * switch a DAP implemented using an SWJ-DP module into SWD mode.
282 * These bits are stored (and transmitted) LSB-first.
283 *
284 * See the DAP-Lite specification, section 2.2.5 for information
285 * about making the debug link select SWD or JTAG. (Similar info
286 * is in a few other ARM documents.)
287 */
288 static const uint8_t jtag2swd_bitseq[] = {
289 /* More than 50 TCK/SWCLK cycles with TMS/SWDIO high,
290 * putting both JTAG and SWD logic into reset state.
291 */
292 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
293 /* Switching sequence enables SWD and disables JTAG
294 * NOTE: bits in the DP's IDCODE may expose the need for
295 * an old/obsolete/deprecated sequence (0xb6 0xed).
296 */
297 0x9e, 0xe7,
298 /* More than 50 TCK/SWCLK cycles with TMS/SWDIO high,
299 * putting both JTAG and SWD logic into reset state.
300 */
301 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
302 };
303
304 /**
305 * Put the debug link into SWD mode, if the target supports it.
306 * The link's initial mode may be either JTAG (for example,
307 * with SWJ-DP after reset) or SWD.
308 *
309 * @param target Enters SWD mode (if possible).
310 *
311 * Note that targets using the JTAG-DP do not support SWD, and that
312 * some targets which could otherwise support it may have have been
313 * configured to disable SWD signaling
314 *
315 * @return ERROR_OK or else a fault code.
316 */
317 int dap_to_swd(struct target *target)
318 {
319 struct arm *arm = target_to_arm(target);
320 int retval;
321
322 if (!arm->dap) {
323 LOG_ERROR("SWD mode is not available");
324 return ERROR_FAIL;
325 }
326
327 LOG_DEBUG("Enter SWD mode");
328
329 /* REVISIT it's ugly to need to make calls to a "jtag"
330 * subsystem if the link may not be in JTAG mode...
331 */
332
333 retval = jtag_add_tms_seq(8 * sizeof(jtag2swd_bitseq),
334 jtag2swd_bitseq, TAP_INVALID);
335 if (retval == ERROR_OK)
336 retval = jtag_execute_queue();
337
338 /* set up the DAP's ops vector for SWD mode. */
339 arm->dap->ops = &swd_dap_ops;
340
341 return retval;
342 }
343
344 COMMAND_HANDLER(handle_swd_wcr)
345 {
346 int retval;
347 struct target *target = get_current_target(CMD_CTX);
348 struct arm *arm = target_to_arm(target);
349 struct adiv5_dap *dap = arm->dap;
350 uint32_t wcr;
351 unsigned trn, scale = 0;
352
353 switch (CMD_ARGC) {
354 /* no-args: just dump state */
355 case 0:
356 /*retval = swd_queue_dp_read(dap, DP_WCR, &wcr); */
357 retval = dap_queue_dp_read(dap, DP_WCR, &wcr);
358 if (retval == ERROR_OK)
359 dap->ops->run(dap);
360 if (retval != ERROR_OK) {
361 LOG_ERROR("can't read WCR?");
362 return retval;
363 }
364
365 command_print(CMD_CTX,
366 "turnaround=%" PRIu32 ", prescale=%" PRIu32,
367 WCR_TO_TRN(wcr),
368 WCR_TO_PRESCALE(wcr));
369 return ERROR_OK;
370
371 case 2: /* TRN and prescale */
372 COMMAND_PARSE_NUMBER(uint, CMD_ARGV[1], scale);
373 if (scale > 7) {
374 LOG_ERROR("prescale %d is too big", scale);
375 return ERROR_FAIL;
376 }
377 /* FALL THROUGH */
378
379 case 1: /* TRN only */
380 COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], trn);
381 if (trn < 1 || trn > 4) {
382 LOG_ERROR("turnaround %d is invalid", trn);
383 return ERROR_FAIL;
384 }
385
386 wcr = ((trn - 1) << 8) | scale;
387 /* FIXME
388 * write WCR ...
389 * then, re-init adapter with new TRN
390 */
391 LOG_ERROR("can't yet modify WCR");
392 return ERROR_FAIL;
393
394 default: /* too many arguments */
395 return ERROR_COMMAND_SYNTAX_ERROR;
396 }
397 }
398
399 static const struct command_registration swd_commands[] = {
400 {
401 /*
402 * Set up SWD and JTAG targets identically, unless/until
403 * infrastructure improves ... meanwhile, ignore all
404 * JTAG-specific stuff like IR length for SWD.
405 *
406 * REVISIT can we verify "just one SWD DAP" here/early?
407 */
408 .name = "newdap",
409 .jim_handler = jim_jtag_newtap,
410 .mode = COMMAND_CONFIG,
411 .help = "declare a new SWD DAP"
412 },
413 {
414 .name = "wcr",
415 .handler = handle_swd_wcr,
416 .mode = COMMAND_ANY,
417 .help = "display or update DAP's WCR register",
418 .usage = "turnaround (1..4), prescale (0..7)",
419 },
420
421 /* REVISIT -- add a command for SWV trace on/off */
422 COMMAND_REGISTRATION_DONE
423 };
424
425 static const struct command_registration swd_handlers[] = {
426 {
427 .name = "swd",
428 .mode = COMMAND_ANY,
429 .help = "SWD command group",
430 .chain = swd_commands,
431 },
432 COMMAND_REGISTRATION_DONE
433 };
434
435 static int swd_select(struct command_context *ctx)
436 {
437 int retval;
438
439 retval = register_commands(ctx, NULL, swd_handlers);
440
441 if (retval != ERROR_OK)
442 return retval;
443
444 const struct swd_driver *swd = jtag_interface->swd;
445
446 /* be sure driver is in SWD mode; start
447 * with hardware default TRN (1), it can be changed later
448 */
449 if (!swd || !swd->read_reg || !swd->write_reg || !swd->init) {
450 LOG_DEBUG("no SWD driver?");
451 return ERROR_FAIL;
452 }
453
454 retval = swd->init();
455 if (retval != ERROR_OK) {
456 LOG_DEBUG("can't init SWD driver");
457 return retval;
458 }
459
460 /* force DAP into SWD mode (not JTAG) */
461 /*retval = dap_to_swd(target);*/
462
463 if (ctx->current_target) {
464 /* force DAP into SWD mode (not JTAG) */
465 struct target *target = get_current_target(ctx);
466 retval = dap_to_swd(target);
467 }
468
469 return retval;
470 }
471
472 static int swd_init(struct command_context *ctx)
473 {
474 struct target *target = get_current_target(ctx);
475 struct arm *arm = target_to_arm(target);
476 struct adiv5_dap *dap = arm->dap;
477 /* Force the DAP's ops vector for SWD mode.
478 * messy - is there a better way? */
479 arm->dap->ops = &swd_dap_ops;
480
481 return swd_connect(dap);
482 }
483
484 static struct transport swd_transport = {
485 .name = "swd",
486 .select = swd_select,
487 .init = swd_init,
488 };
489
490 static void swd_constructor(void) __attribute__((constructor));
491 static void swd_constructor(void)
492 {
493 transport_register(&swd_transport);
494 }
495
496 /** Returns true if the current debug session
497 * is using SWD as its transport.
498 */
499 bool transport_is_swd(void)
500 {
501 return get_current_transport() == &swd_transport;
502 }