arm_adi_v5: Split ahbap_debugport_init
[openocd.git] / src / target / adi_v5_swd.c
1 /***************************************************************************
2 *
3 * Copyright (C) 2010 by David Brownell
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the
17 * Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 ***************************************************************************/
20
21 /**
22 * @file
23 * Utilities to support ARM "Serial Wire Debug" (SWD), a low pin-count debug
24 * link protocol used in cases where JTAG is not wanted. This is coupled to
25 * recent versions of ARM's "CoreSight" debug framework. This specific code
26 * is a transport level interface, with "target/arm_adi_v5.[hc]" code
27 * understanding operation semantics, shared with the JTAG transport.
28 *
29 * Single-DAP support only.
30 *
31 * for details, see "ARM IHI 0031A"
32 * ARM Debug Interface v5 Architecture Specification
33 * especially section 5.3 for SWD protocol
34 *
35 * On many chips (most current Cortex-M3 parts) SWD is a run-time alternative
36 * to JTAG. Boards may support one or both. There are also SWD-only chips,
37 * (using SW-DP not SWJ-DP).
38 *
39 * Even boards that also support JTAG can benefit from SWD support, because
40 * usually there's no way to access the SWO trace view mechanism in JTAG mode.
41 * That is, trace access may require SWD support.
42 *
43 */
44
45 #ifdef HAVE_CONFIG_H
46 #include "config.h"
47 #endif
48
49 #include "arm.h"
50 #include "arm_adi_v5.h"
51 #include <helper/time_support.h>
52
53 #include <transport/transport.h>
54 #include <jtag/interface.h>
55
56 #include <jtag/swd.h>
57
58 /* YUK! - but this is currently a global.... */
59 extern struct jtag_interface *jtag_interface;
60 static bool do_sync;
61
62 static void swd_finish_read(struct adiv5_dap *dap)
63 {
64 const struct swd_driver *swd = jtag_interface->swd;
65 if (dap->last_read != NULL) {
66 swd->read_reg(swd_cmd(true, false, DP_RDBUFF), dap->last_read, 0);
67 dap->last_read = NULL;
68 }
69 }
70
71 static int swd_queue_dp_write(struct adiv5_dap *dap, unsigned reg,
72 uint32_t data);
73 static int swd_queue_dp_read(struct adiv5_dap *dap, unsigned reg,
74 uint32_t *data);
75
76 static void swd_clear_sticky_errors(struct adiv5_dap *dap)
77 {
78 const struct swd_driver *swd = jtag_interface->swd;
79 assert(swd);
80
81 swd->write_reg(swd_cmd(false, false, DP_ABORT),
82 STKCMPCLR | STKERRCLR | WDERRCLR | ORUNERRCLR, 0);
83 }
84
85 static int swd_run_inner(struct adiv5_dap *dap)
86 {
87 const struct swd_driver *swd = jtag_interface->swd;
88 int retval;
89
90 retval = swd->run();
91
92 if (retval != ERROR_OK) {
93 /* fault response */
94 dap->do_reconnect = true;
95 }
96
97 return retval;
98 }
99
100 static int swd_connect(struct adiv5_dap *dap)
101 {
102 uint32_t idcode;
103 int status;
104
105 /* FIXME validate transport config ... is the
106 * configured DAP present (check IDCODE)?
107 * Is *only* one DAP configured?
108 *
109 * MUST READ IDCODE
110 */
111
112 /* Note, debugport_init() does setup too */
113 jtag_interface->swd->switch_seq(JTAG_TO_SWD);
114
115 /* Make sure we don't try to perform any other accesses before the DPIDR read. */
116 dap->do_reconnect = false;
117 dap->dp_bank_value = 0;
118
119 swd_queue_dp_read(dap, DP_IDCODE, &idcode);
120
121 /* force clear all sticky faults */
122 swd_clear_sticky_errors(dap);
123
124 status = swd_run_inner(dap);
125
126 if (status == ERROR_OK) {
127 LOG_INFO("SWD IDCODE %#8.8" PRIx32, idcode);
128 dap->do_reconnect = false;
129 } else
130 dap->do_reconnect = true;
131
132 return status;
133 }
134
135 static inline int check_sync(struct adiv5_dap *dap)
136 {
137 return do_sync ? swd_run_inner(dap) : ERROR_OK;
138 }
139
140 static int swd_check_reconnect(struct adiv5_dap *dap)
141 {
142 if (dap->do_reconnect)
143 return swd_connect(dap);
144
145 return ERROR_OK;
146 }
147
148 static int swd_queue_ap_abort(struct adiv5_dap *dap, uint8_t *ack)
149 {
150 const struct swd_driver *swd = jtag_interface->swd;
151 assert(swd);
152
153 swd->write_reg(swd_cmd(false, false, DP_ABORT),
154 DAPABORT | STKCMPCLR | STKERRCLR | WDERRCLR | ORUNERRCLR, 0);
155 return check_sync(dap);
156 }
157
158 /** Select the DP register bank matching bits 7:4 of reg. */
159 static void swd_queue_dp_bankselect(struct adiv5_dap *dap, unsigned reg)
160 {
161 uint32_t select_dp_bank = (reg & 0x000000F0) >> 4;
162
163 if (reg == DP_SELECT)
164 return;
165
166 if (select_dp_bank == dap->dp_bank_value)
167 return;
168
169 dap->dp_bank_value = select_dp_bank;
170 select_dp_bank |= dap->ap_current | dap->ap_bank_value;
171
172 swd_queue_dp_write(dap, DP_SELECT, select_dp_bank);
173 }
174
175 static int swd_queue_dp_read(struct adiv5_dap *dap, unsigned reg,
176 uint32_t *data)
177 {
178 const struct swd_driver *swd = jtag_interface->swd;
179 assert(swd);
180
181 int retval = swd_check_reconnect(dap);
182 if (retval != ERROR_OK)
183 return retval;
184
185 swd_queue_dp_bankselect(dap, reg);
186 swd->read_reg(swd_cmd(true, false, reg), data, 0);
187
188 return check_sync(dap);
189 }
190
191 static int swd_queue_dp_write(struct adiv5_dap *dap, unsigned reg,
192 uint32_t data)
193 {
194 const struct swd_driver *swd = jtag_interface->swd;
195 assert(swd);
196
197 int retval = swd_check_reconnect(dap);
198 if (retval != ERROR_OK)
199 return retval;
200
201 swd_finish_read(dap);
202 swd_queue_dp_bankselect(dap, reg);
203 swd->write_reg(swd_cmd(false, false, reg), data, 0);
204
205 return check_sync(dap);
206 }
207
208 /** Select the AP register bank matching bits 7:4 of reg. */
209 static void swd_queue_ap_bankselect(struct adiv5_dap *dap, unsigned reg)
210 {
211 uint32_t select_ap_bank = reg & 0x000000F0;
212
213 if (select_ap_bank == dap->ap_bank_value)
214 return;
215
216 dap->ap_bank_value = select_ap_bank;
217 select_ap_bank |= dap->ap_current | dap->dp_bank_value;
218
219 swd_queue_dp_write(dap, DP_SELECT, select_ap_bank);
220 }
221
222 static int swd_queue_ap_read(struct adiv5_dap *dap, unsigned reg,
223 uint32_t *data)
224 {
225 const struct swd_driver *swd = jtag_interface->swd;
226 assert(swd);
227
228 int retval = swd_check_reconnect(dap);
229 if (retval != ERROR_OK)
230 return retval;
231
232 swd_queue_ap_bankselect(dap, reg);
233 swd->read_reg(swd_cmd(true, true, reg), dap->last_read, dap->ap[dap_ap_get_select(dap)].memaccess_tck);
234 dap->last_read = data;
235
236 return check_sync(dap);
237 }
238
239 static int swd_queue_ap_write(struct adiv5_dap *dap, unsigned reg,
240 uint32_t data)
241 {
242 const struct swd_driver *swd = jtag_interface->swd;
243 assert(swd);
244
245 int retval = swd_check_reconnect(dap);
246 if (retval != ERROR_OK)
247 return retval;
248
249 swd_finish_read(dap);
250 swd_queue_ap_bankselect(dap, reg);
251 swd->write_reg(swd_cmd(false, true, reg), data, dap->ap[dap_ap_get_select(dap)].memaccess_tck);
252
253 return check_sync(dap);
254 }
255
256 /** Executes all queued DAP operations. */
257 static int swd_run(struct adiv5_dap *dap)
258 {
259 swd_finish_read(dap);
260 return swd_run_inner(dap);
261 }
262
263 const struct dap_ops swd_dap_ops = {
264 .queue_dp_read = swd_queue_dp_read,
265 .queue_dp_write = swd_queue_dp_write,
266 .queue_ap_read = swd_queue_ap_read,
267 .queue_ap_write = swd_queue_ap_write,
268 .queue_ap_abort = swd_queue_ap_abort,
269 .run = swd_run,
270 };
271
272 /*
273 * This represents the bits which must be sent out on TMS/SWDIO to
274 * switch a DAP implemented using an SWJ-DP module into SWD mode.
275 * These bits are stored (and transmitted) LSB-first.
276 *
277 * See the DAP-Lite specification, section 2.2.5 for information
278 * about making the debug link select SWD or JTAG. (Similar info
279 * is in a few other ARM documents.)
280 */
281 static const uint8_t jtag2swd_bitseq[] = {
282 /* More than 50 TCK/SWCLK cycles with TMS/SWDIO high,
283 * putting both JTAG and SWD logic into reset state.
284 */
285 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
286 /* Switching sequence enables SWD and disables JTAG
287 * NOTE: bits in the DP's IDCODE may expose the need for
288 * an old/obsolete/deprecated sequence (0xb6 0xed).
289 */
290 0x9e, 0xe7,
291 /* More than 50 TCK/SWCLK cycles with TMS/SWDIO high,
292 * putting both JTAG and SWD logic into reset state.
293 */
294 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
295 };
296
297 /**
298 * Put the debug link into SWD mode, if the target supports it.
299 * The link's initial mode may be either JTAG (for example,
300 * with SWJ-DP after reset) or SWD.
301 *
302 * @param target Enters SWD mode (if possible).
303 *
304 * Note that targets using the JTAG-DP do not support SWD, and that
305 * some targets which could otherwise support it may have have been
306 * configured to disable SWD signaling
307 *
308 * @return ERROR_OK or else a fault code.
309 */
310 int dap_to_swd(struct target *target)
311 {
312 struct arm *arm = target_to_arm(target);
313 int retval;
314
315 if (!arm->dap) {
316 LOG_ERROR("SWD mode is not available");
317 return ERROR_FAIL;
318 }
319
320 LOG_DEBUG("Enter SWD mode");
321
322 /* REVISIT it's ugly to need to make calls to a "jtag"
323 * subsystem if the link may not be in JTAG mode...
324 */
325
326 retval = jtag_add_tms_seq(8 * sizeof(jtag2swd_bitseq),
327 jtag2swd_bitseq, TAP_INVALID);
328 if (retval == ERROR_OK)
329 retval = jtag_execute_queue();
330
331 /* set up the DAP's ops vector for SWD mode. */
332 arm->dap->ops = &swd_dap_ops;
333
334 return retval;
335 }
336
337 COMMAND_HANDLER(handle_swd_wcr)
338 {
339 int retval;
340 struct target *target = get_current_target(CMD_CTX);
341 struct arm *arm = target_to_arm(target);
342 struct adiv5_dap *dap = arm->dap;
343 uint32_t wcr;
344 unsigned trn, scale = 0;
345
346 switch (CMD_ARGC) {
347 /* no-args: just dump state */
348 case 0:
349 /*retval = swd_queue_dp_read(dap, DP_WCR, &wcr); */
350 retval = dap_queue_dp_read(dap, DP_WCR, &wcr);
351 if (retval == ERROR_OK)
352 dap->ops->run(dap);
353 if (retval != ERROR_OK) {
354 LOG_ERROR("can't read WCR?");
355 return retval;
356 }
357
358 command_print(CMD_CTX,
359 "turnaround=%" PRIu32 ", prescale=%" PRIu32,
360 WCR_TO_TRN(wcr),
361 WCR_TO_PRESCALE(wcr));
362 return ERROR_OK;
363
364 case 2: /* TRN and prescale */
365 COMMAND_PARSE_NUMBER(uint, CMD_ARGV[1], scale);
366 if (scale > 7) {
367 LOG_ERROR("prescale %d is too big", scale);
368 return ERROR_FAIL;
369 }
370 /* FALL THROUGH */
371
372 case 1: /* TRN only */
373 COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], trn);
374 if (trn < 1 || trn > 4) {
375 LOG_ERROR("turnaround %d is invalid", trn);
376 return ERROR_FAIL;
377 }
378
379 wcr = ((trn - 1) << 8) | scale;
380 /* FIXME
381 * write WCR ...
382 * then, re-init adapter with new TRN
383 */
384 LOG_ERROR("can't yet modify WCR");
385 return ERROR_FAIL;
386
387 default: /* too many arguments */
388 return ERROR_COMMAND_SYNTAX_ERROR;
389 }
390 }
391
392 static const struct command_registration swd_commands[] = {
393 {
394 /*
395 * Set up SWD and JTAG targets identically, unless/until
396 * infrastructure improves ... meanwhile, ignore all
397 * JTAG-specific stuff like IR length for SWD.
398 *
399 * REVISIT can we verify "just one SWD DAP" here/early?
400 */
401 .name = "newdap",
402 .jim_handler = jim_jtag_newtap,
403 .mode = COMMAND_CONFIG,
404 .help = "declare a new SWD DAP"
405 },
406 {
407 .name = "wcr",
408 .handler = handle_swd_wcr,
409 .mode = COMMAND_ANY,
410 .help = "display or update DAP's WCR register",
411 .usage = "turnaround (1..4), prescale (0..7)",
412 },
413
414 /* REVISIT -- add a command for SWV trace on/off */
415 COMMAND_REGISTRATION_DONE
416 };
417
418 static const struct command_registration swd_handlers[] = {
419 {
420 .name = "swd",
421 .mode = COMMAND_ANY,
422 .help = "SWD command group",
423 .chain = swd_commands,
424 },
425 COMMAND_REGISTRATION_DONE
426 };
427
428 static int swd_select(struct command_context *ctx)
429 {
430 int retval;
431
432 retval = register_commands(ctx, NULL, swd_handlers);
433
434 if (retval != ERROR_OK)
435 return retval;
436
437 const struct swd_driver *swd = jtag_interface->swd;
438
439 /* be sure driver is in SWD mode; start
440 * with hardware default TRN (1), it can be changed later
441 */
442 if (!swd || !swd->read_reg || !swd->write_reg || !swd->init) {
443 LOG_DEBUG("no SWD driver?");
444 return ERROR_FAIL;
445 }
446
447 retval = swd->init();
448 if (retval != ERROR_OK) {
449 LOG_DEBUG("can't init SWD driver");
450 return retval;
451 }
452
453 /* force DAP into SWD mode (not JTAG) */
454 /*retval = dap_to_swd(target);*/
455
456 if (ctx->current_target) {
457 /* force DAP into SWD mode (not JTAG) */
458 struct target *target = get_current_target(ctx);
459 retval = dap_to_swd(target);
460 }
461
462 return retval;
463 }
464
465 static int swd_init(struct command_context *ctx)
466 {
467 struct target *target = get_current_target(ctx);
468 struct arm *arm = target_to_arm(target);
469 struct adiv5_dap *dap = arm->dap;
470 /* Force the DAP's ops vector for SWD mode.
471 * messy - is there a better way? */
472 arm->dap->ops = &swd_dap_ops;
473
474 return swd_connect(dap);
475 }
476
477 static struct transport swd_transport = {
478 .name = "swd",
479 .select = swd_select,
480 .init = swd_init,
481 };
482
483 static void swd_constructor(void) __attribute__((constructor));
484 static void swd_constructor(void)
485 {
486 transport_register(&swd_transport);
487 }
488
489 /** Returns true if the current debug session
490 * is using SWD as its transport.
491 */
492 bool transport_is_swd(void)
493 {
494 return get_current_transport() == &swd_transport;
495 }