adi_v5_swd: Avoid special handling the SELECT cache during connect
[openocd.git] / src / target / adi_v5_swd.c
1 /***************************************************************************
2 *
3 * Copyright (C) 2010 by David Brownell
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the
17 * Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 ***************************************************************************/
20
21 /**
22 * @file
23 * Utilities to support ARM "Serial Wire Debug" (SWD), a low pin-count debug
24 * link protocol used in cases where JTAG is not wanted. This is coupled to
25 * recent versions of ARM's "CoreSight" debug framework. This specific code
26 * is a transport level interface, with "target/arm_adi_v5.[hc]" code
27 * understanding operation semantics, shared with the JTAG transport.
28 *
29 * Single-DAP support only.
30 *
31 * for details, see "ARM IHI 0031A"
32 * ARM Debug Interface v5 Architecture Specification
33 * especially section 5.3 for SWD protocol
34 *
35 * On many chips (most current Cortex-M3 parts) SWD is a run-time alternative
36 * to JTAG. Boards may support one or both. There are also SWD-only chips,
37 * (using SW-DP not SWJ-DP).
38 *
39 * Even boards that also support JTAG can benefit from SWD support, because
40 * usually there's no way to access the SWO trace view mechanism in JTAG mode.
41 * That is, trace access may require SWD support.
42 *
43 */
44
45 #ifdef HAVE_CONFIG_H
46 #include "config.h"
47 #endif
48
49 #include "arm.h"
50 #include "arm_adi_v5.h"
51 #include <helper/time_support.h>
52
53 #include <transport/transport.h>
54 #include <jtag/interface.h>
55
56 #include <jtag/swd.h>
57
58 /* YUK! - but this is currently a global.... */
59 extern struct jtag_interface *jtag_interface;
60 static bool do_sync;
61
62 static void swd_finish_read(struct adiv5_dap *dap)
63 {
64 const struct swd_driver *swd = jtag_interface->swd;
65 if (dap->last_read != NULL) {
66 swd->read_reg(swd_cmd(true, false, DP_RDBUFF), dap->last_read, 0);
67 dap->last_read = NULL;
68 }
69 }
70
71 static int swd_queue_dp_write(struct adiv5_dap *dap, unsigned reg,
72 uint32_t data);
73 static int swd_queue_dp_read(struct adiv5_dap *dap, unsigned reg,
74 uint32_t *data);
75
76 static void swd_clear_sticky_errors(struct adiv5_dap *dap)
77 {
78 const struct swd_driver *swd = jtag_interface->swd;
79 assert(swd);
80
81 swd->write_reg(swd_cmd(false, false, DP_ABORT),
82 STKCMPCLR | STKERRCLR | WDERRCLR | ORUNERRCLR, 0);
83 }
84
85 static int swd_run_inner(struct adiv5_dap *dap)
86 {
87 const struct swd_driver *swd = jtag_interface->swd;
88 int retval;
89
90 retval = swd->run();
91
92 if (retval != ERROR_OK) {
93 /* fault response */
94 dap->do_reconnect = true;
95 }
96
97 return retval;
98 }
99
100 static int swd_connect(struct adiv5_dap *dap)
101 {
102 uint32_t idcode;
103 int status;
104
105 /* FIXME validate transport config ... is the
106 * configured DAP present (check IDCODE)?
107 * Is *only* one DAP configured?
108 *
109 * MUST READ IDCODE
110 */
111
112 /* Note, debugport_init() does setup too */
113 jtag_interface->swd->switch_seq(JTAG_TO_SWD);
114
115 /* Clear link state, including the SELECT cache. */
116 dap->do_reconnect = false;
117 dap->select = DP_SELECT_INVALID;
118
119 swd_queue_dp_read(dap, DP_IDCODE, &idcode);
120
121 /* force clear all sticky faults */
122 swd_clear_sticky_errors(dap);
123
124 status = swd_run_inner(dap);
125
126 if (status == ERROR_OK) {
127 LOG_INFO("SWD IDCODE %#8.8" PRIx32, idcode);
128 dap->do_reconnect = false;
129 } else
130 dap->do_reconnect = true;
131
132 return status;
133 }
134
135 static inline int check_sync(struct adiv5_dap *dap)
136 {
137 return do_sync ? swd_run_inner(dap) : ERROR_OK;
138 }
139
140 static int swd_check_reconnect(struct adiv5_dap *dap)
141 {
142 if (dap->do_reconnect)
143 return swd_connect(dap);
144
145 return ERROR_OK;
146 }
147
148 static int swd_queue_ap_abort(struct adiv5_dap *dap, uint8_t *ack)
149 {
150 const struct swd_driver *swd = jtag_interface->swd;
151 assert(swd);
152
153 swd->write_reg(swd_cmd(false, false, DP_ABORT),
154 DAPABORT | STKCMPCLR | STKERRCLR | WDERRCLR | ORUNERRCLR, 0);
155 return check_sync(dap);
156 }
157
158 /** Select the DP register bank matching bits 7:4 of reg. */
159 static void swd_queue_dp_bankselect(struct adiv5_dap *dap, unsigned reg)
160 {
161 /* Only register address 4 is banked. */
162 if ((reg & 0xf) != 4)
163 return;
164
165 uint32_t select_dp_bank = (reg & 0x000000F0) >> 4;
166 uint32_t sel = select_dp_bank
167 | (dap->select & (DP_SELECT_APSEL | DP_SELECT_APBANK));
168
169 if (sel == dap->select)
170 return;
171
172 dap->select = sel;
173
174 swd_queue_dp_write(dap, DP_SELECT, sel);
175 }
176
177 static int swd_queue_dp_read(struct adiv5_dap *dap, unsigned reg,
178 uint32_t *data)
179 {
180 const struct swd_driver *swd = jtag_interface->swd;
181 assert(swd);
182
183 int retval = swd_check_reconnect(dap);
184 if (retval != ERROR_OK)
185 return retval;
186
187 swd_queue_dp_bankselect(dap, reg);
188 swd->read_reg(swd_cmd(true, false, reg), data, 0);
189
190 return check_sync(dap);
191 }
192
193 static int swd_queue_dp_write(struct adiv5_dap *dap, unsigned reg,
194 uint32_t data)
195 {
196 const struct swd_driver *swd = jtag_interface->swd;
197 assert(swd);
198
199 int retval = swd_check_reconnect(dap);
200 if (retval != ERROR_OK)
201 return retval;
202
203 swd_finish_read(dap);
204 swd_queue_dp_bankselect(dap, reg);
205 swd->write_reg(swd_cmd(false, false, reg), data, 0);
206
207 return check_sync(dap);
208 }
209
210 /** Select the AP register bank matching bits 7:4 of reg. */
211 static void swd_queue_ap_bankselect(struct adiv5_ap *ap, unsigned reg)
212 {
213 struct adiv5_dap *dap = ap->dap;
214 uint32_t sel = ((uint32_t)ap->ap_num << 24)
215 | (reg & 0x000000F0)
216 | (dap->select & DP_SELECT_DPBANK);
217
218 if (sel == dap->select)
219 return;
220
221 dap->select = sel;
222
223 swd_queue_dp_write(dap, DP_SELECT, sel);
224 }
225
226 static int swd_queue_ap_read(struct adiv5_ap *ap, unsigned reg,
227 uint32_t *data)
228 {
229 const struct swd_driver *swd = jtag_interface->swd;
230 assert(swd);
231
232 struct adiv5_dap *dap = ap->dap;
233
234 int retval = swd_check_reconnect(dap);
235 if (retval != ERROR_OK)
236 return retval;
237
238 swd_queue_ap_bankselect(ap, reg);
239 swd->read_reg(swd_cmd(true, true, reg), dap->last_read, ap->memaccess_tck);
240 dap->last_read = data;
241
242 return check_sync(dap);
243 }
244
245 static int swd_queue_ap_write(struct adiv5_ap *ap, unsigned reg,
246 uint32_t data)
247 {
248 const struct swd_driver *swd = jtag_interface->swd;
249 assert(swd);
250
251 struct adiv5_dap *dap = ap->dap;
252
253 int retval = swd_check_reconnect(dap);
254 if (retval != ERROR_OK)
255 return retval;
256
257 swd_finish_read(dap);
258 swd_queue_ap_bankselect(ap, reg);
259 swd->write_reg(swd_cmd(false, true, reg), data, ap->memaccess_tck);
260
261 return check_sync(dap);
262 }
263
264 /** Executes all queued DAP operations. */
265 static int swd_run(struct adiv5_dap *dap)
266 {
267 swd_finish_read(dap);
268 return swd_run_inner(dap);
269 }
270
271 const struct dap_ops swd_dap_ops = {
272 .queue_dp_read = swd_queue_dp_read,
273 .queue_dp_write = swd_queue_dp_write,
274 .queue_ap_read = swd_queue_ap_read,
275 .queue_ap_write = swd_queue_ap_write,
276 .queue_ap_abort = swd_queue_ap_abort,
277 .run = swd_run,
278 };
279
280 /*
281 * This represents the bits which must be sent out on TMS/SWDIO to
282 * switch a DAP implemented using an SWJ-DP module into SWD mode.
283 * These bits are stored (and transmitted) LSB-first.
284 *
285 * See the DAP-Lite specification, section 2.2.5 for information
286 * about making the debug link select SWD or JTAG. (Similar info
287 * is in a few other ARM documents.)
288 */
289 static const uint8_t jtag2swd_bitseq[] = {
290 /* More than 50 TCK/SWCLK cycles with TMS/SWDIO high,
291 * putting both JTAG and SWD logic into reset state.
292 */
293 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
294 /* Switching sequence enables SWD and disables JTAG
295 * NOTE: bits in the DP's IDCODE may expose the need for
296 * an old/obsolete/deprecated sequence (0xb6 0xed).
297 */
298 0x9e, 0xe7,
299 /* More than 50 TCK/SWCLK cycles with TMS/SWDIO high,
300 * putting both JTAG and SWD logic into reset state.
301 */
302 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
303 };
304
305 /**
306 * Put the debug link into SWD mode, if the target supports it.
307 * The link's initial mode may be either JTAG (for example,
308 * with SWJ-DP after reset) or SWD.
309 *
310 * @param target Enters SWD mode (if possible).
311 *
312 * Note that targets using the JTAG-DP do not support SWD, and that
313 * some targets which could otherwise support it may have have been
314 * configured to disable SWD signaling
315 *
316 * @return ERROR_OK or else a fault code.
317 */
318 int dap_to_swd(struct target *target)
319 {
320 struct arm *arm = target_to_arm(target);
321 int retval;
322
323 if (!arm->dap) {
324 LOG_ERROR("SWD mode is not available");
325 return ERROR_FAIL;
326 }
327
328 LOG_DEBUG("Enter SWD mode");
329
330 /* REVISIT it's ugly to need to make calls to a "jtag"
331 * subsystem if the link may not be in JTAG mode...
332 */
333
334 retval = jtag_add_tms_seq(8 * sizeof(jtag2swd_bitseq),
335 jtag2swd_bitseq, TAP_INVALID);
336 if (retval == ERROR_OK)
337 retval = jtag_execute_queue();
338
339 /* set up the DAP's ops vector for SWD mode. */
340 arm->dap->ops = &swd_dap_ops;
341
342 return retval;
343 }
344
345 COMMAND_HANDLER(handle_swd_wcr)
346 {
347 int retval;
348 struct target *target = get_current_target(CMD_CTX);
349 struct arm *arm = target_to_arm(target);
350 struct adiv5_dap *dap = arm->dap;
351 uint32_t wcr;
352 unsigned trn, scale = 0;
353
354 switch (CMD_ARGC) {
355 /* no-args: just dump state */
356 case 0:
357 /*retval = swd_queue_dp_read(dap, DP_WCR, &wcr); */
358 retval = dap_queue_dp_read(dap, DP_WCR, &wcr);
359 if (retval == ERROR_OK)
360 dap->ops->run(dap);
361 if (retval != ERROR_OK) {
362 LOG_ERROR("can't read WCR?");
363 return retval;
364 }
365
366 command_print(CMD_CTX,
367 "turnaround=%" PRIu32 ", prescale=%" PRIu32,
368 WCR_TO_TRN(wcr),
369 WCR_TO_PRESCALE(wcr));
370 return ERROR_OK;
371
372 case 2: /* TRN and prescale */
373 COMMAND_PARSE_NUMBER(uint, CMD_ARGV[1], scale);
374 if (scale > 7) {
375 LOG_ERROR("prescale %d is too big", scale);
376 return ERROR_FAIL;
377 }
378 /* FALL THROUGH */
379
380 case 1: /* TRN only */
381 COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], trn);
382 if (trn < 1 || trn > 4) {
383 LOG_ERROR("turnaround %d is invalid", trn);
384 return ERROR_FAIL;
385 }
386
387 wcr = ((trn - 1) << 8) | scale;
388 /* FIXME
389 * write WCR ...
390 * then, re-init adapter with new TRN
391 */
392 LOG_ERROR("can't yet modify WCR");
393 return ERROR_FAIL;
394
395 default: /* too many arguments */
396 return ERROR_COMMAND_SYNTAX_ERROR;
397 }
398 }
399
400 static const struct command_registration swd_commands[] = {
401 {
402 /*
403 * Set up SWD and JTAG targets identically, unless/until
404 * infrastructure improves ... meanwhile, ignore all
405 * JTAG-specific stuff like IR length for SWD.
406 *
407 * REVISIT can we verify "just one SWD DAP" here/early?
408 */
409 .name = "newdap",
410 .jim_handler = jim_jtag_newtap,
411 .mode = COMMAND_CONFIG,
412 .help = "declare a new SWD DAP"
413 },
414 {
415 .name = "wcr",
416 .handler = handle_swd_wcr,
417 .mode = COMMAND_ANY,
418 .help = "display or update DAP's WCR register",
419 .usage = "turnaround (1..4), prescale (0..7)",
420 },
421
422 /* REVISIT -- add a command for SWV trace on/off */
423 COMMAND_REGISTRATION_DONE
424 };
425
426 static const struct command_registration swd_handlers[] = {
427 {
428 .name = "swd",
429 .mode = COMMAND_ANY,
430 .help = "SWD command group",
431 .chain = swd_commands,
432 },
433 COMMAND_REGISTRATION_DONE
434 };
435
436 static int swd_select(struct command_context *ctx)
437 {
438 int retval;
439
440 retval = register_commands(ctx, NULL, swd_handlers);
441
442 if (retval != ERROR_OK)
443 return retval;
444
445 const struct swd_driver *swd = jtag_interface->swd;
446
447 /* be sure driver is in SWD mode; start
448 * with hardware default TRN (1), it can be changed later
449 */
450 if (!swd || !swd->read_reg || !swd->write_reg || !swd->init) {
451 LOG_DEBUG("no SWD driver?");
452 return ERROR_FAIL;
453 }
454
455 retval = swd->init();
456 if (retval != ERROR_OK) {
457 LOG_DEBUG("can't init SWD driver");
458 return retval;
459 }
460
461 /* force DAP into SWD mode (not JTAG) */
462 /*retval = dap_to_swd(target);*/
463
464 if (ctx->current_target) {
465 /* force DAP into SWD mode (not JTAG) */
466 struct target *target = get_current_target(ctx);
467 retval = dap_to_swd(target);
468 }
469
470 return retval;
471 }
472
473 static int swd_init(struct command_context *ctx)
474 {
475 struct target *target = get_current_target(ctx);
476 struct arm *arm = target_to_arm(target);
477 struct adiv5_dap *dap = arm->dap;
478 /* Force the DAP's ops vector for SWD mode.
479 * messy - is there a better way? */
480 arm->dap->ops = &swd_dap_ops;
481
482 return swd_connect(dap);
483 }
484
485 static struct transport swd_transport = {
486 .name = "swd",
487 .select = swd_select,
488 .init = swd_init,
489 };
490
491 static void swd_constructor(void) __attribute__((constructor));
492 static void swd_constructor(void)
493 {
494 transport_register(&swd_transport);
495 }
496
497 /** Returns true if the current debug session
498 * is using SWD as its transport.
499 */
500 bool transport_is_swd(void)
501 {
502 return get_current_transport() == &swd_transport;
503 }