src/target/adi_v5_swd.c

   1 /***************************************************************************
   2  *
   3  *   Copyright (C) 2010 by David Brownell
   4  *
   5  *   This program is free software; you can redistribute it and/or modify
   6  *   it under the terms of the GNU General Public License as published by
   7  *   the Free Software Foundation; either version 2 of the License, or
   8  *   (at your option) any later version.
   9  *
  10  *   This program is distributed in the hope that it will be useful,
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  *   GNU General Public License for more details.
  14  *
  15  *   You should have received a copy of the GNU General Public License
  16  *   along with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  ***************************************************************************/
  18
  19 /**
  20  * @file
  21  * Utilities to support ARM "Serial Wire Debug" (SWD), a low pin-count debug
  22  * link protocol used in cases where JTAG is not wanted.  This is coupled to
  23  * recent versions of ARM's "CoreSight" debug framework.  This specific code
  24  * is a transport level interface, with "target/arm_adi_v5.[hc]" code
  25  * understanding operation semantics, shared with the JTAG transport.
  26  *
  27  * Single-DAP support only.
  28  *
  29  * for details, see "ARM IHI 0031A"
  30  * ARM Debug Interface v5 Architecture Specification
  31  * especially section 5.3 for SWD protocol
  32  *
  33  * On many chips (most current Cortex-M3 parts) SWD is a run-time alternative
  34  * to JTAG.  Boards may support one or both.  There are also SWD-only chips,
  35  * (using SW-DP not SWJ-DP).
  36  *
  37  * Even boards that also support JTAG can benefit from SWD support, because
  38  * usually there's no way to access the SWO trace view mechanism in JTAG mode.
  39  * That is, trace access may require SWD support.
  40  *
  41  */
  42
  43 #ifdef HAVE_CONFIG_H
  44 #include "config.h"
  45 #endif
  46
  47 #include "arm.h"
  48 #include "arm_adi_v5.h"
  49 #include <helper/time_support.h>
  50
  51 #include <transport/transport.h>
  52 #include <jtag/interface.h>
  53
  54 #include <jtag/swd.h>
  55
  56 static bool do_sync;
  57
  58 static void swd_finish_read(struct adiv5_dap *dap)
  59 {
  60         const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
  61         if (dap->last_read != NULL) {
  62                 swd->read_reg(swd_cmd(true, false, DP_RDBUFF), dap->last_read, 0);
  63                 dap->last_read = NULL;
  64         }
  65 }
  66
  67 static int swd_queue_dp_write(struct adiv5_dap *dap, unsigned reg,
  68                 uint32_t data);
  69 static int swd_queue_dp_read(struct adiv5_dap *dap, unsigned reg,
  70                 uint32_t *data);
  71
  72 static void swd_clear_sticky_errors(struct adiv5_dap *dap)
  73 {
  74         const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
  75         assert(swd);
  76
  77         swd->write_reg(swd_cmd(false,  false, DP_ABORT),
  78                 STKCMPCLR | STKERRCLR | WDERRCLR | ORUNERRCLR, 0);
  79 }
  80
  81 static int swd_run_inner(struct adiv5_dap *dap)
  82 {
  83         const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
  84         int retval;
  85
  86         retval = swd->run();
  87
  88         if (retval != ERROR_OK) {
  89                 /* fault response */
  90                 dap->do_reconnect = true;
  91         }
  92
  93         return retval;
  94 }
  95
  96 static int swd_connect(struct adiv5_dap *dap)
  97 {
  98         const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
  99         uint32_t dpidr;
 100         int status;
 101
 102         /* FIXME validate transport config ... is the
 103          * configured DAP present (check IDCODE)?
 104          * Is *only* one DAP configured?
 105          *
 106          * MUST READ DPIDR
 107          */
 108
 109         /* Check if we should reset srst already when connecting, but not if reconnecting. */
 110         if (!dap->do_reconnect) {
 111                 enum reset_types jtag_reset_config = jtag_get_reset_config();
 112
 113                 if (jtag_reset_config & RESET_CNCT_UNDER_SRST) {
 114                         if (jtag_reset_config & RESET_SRST_NO_GATING)
 115                                 swd_add_reset(1);
 116                         else
 117                                 LOG_WARNING("\'srst_nogate\' reset_config option is required");
 118                 }
 119         }
 120
 121         /* Note, debugport_init() does setup too */
 122         swd->switch_seq(JTAG_TO_SWD);
 123
 124         /* Clear link state, including the SELECT cache. */
 125         dap->do_reconnect = false;
 126         dap_invalidate_cache(dap);
 127
 128         swd_queue_dp_read(dap, DP_DPIDR, &dpidr);
 129
 130         /* force clear all sticky faults */
 131         swd_clear_sticky_errors(dap);
 132
 133         status = swd_run_inner(dap);
 134
 135         if (status == ERROR_OK) {
 136                 LOG_INFO("SWD DPIDR %#8.8" PRIx32, dpidr);
 137                 dap->do_reconnect = false;
 138                 status = dap_dp_init(dap);
 139         } else
 140                 dap->do_reconnect = true;
 141
 142         return status;
 143 }
 144
 145 static inline int check_sync(struct adiv5_dap *dap)
 146 {
 147         return do_sync ? swd_run_inner(dap) : ERROR_OK;
 148 }
 149
 150 static int swd_check_reconnect(struct adiv5_dap *dap)
 151 {
 152         if (dap->do_reconnect)
 153                 return swd_connect(dap);
 154
 155         return ERROR_OK;
 156 }
 157
 158 static int swd_queue_ap_abort(struct adiv5_dap *dap, uint8_t *ack)
 159 {
 160         const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
 161         assert(swd);
 162
 163         swd->write_reg(swd_cmd(false,  false, DP_ABORT),
 164                 DAPABORT | STKCMPCLR | STKERRCLR | WDERRCLR | ORUNERRCLR, 0);
 165         return check_sync(dap);
 166 }
 167
 168 /** Select the DP register bank matching bits 7:4 of reg. */
 169 static int swd_queue_dp_bankselect(struct adiv5_dap *dap, unsigned reg)
 170 {
 171         /* Only register address 4 is banked. */
 172         if ((reg & 0xf) != 4)
 173                 return ERROR_OK;
 174
 175         uint32_t select_dp_bank = (reg & 0x000000F0) >> 4;
 176         uint32_t sel = select_dp_bank
 177                         | (dap->select & (DP_SELECT_APSEL | DP_SELECT_APBANK));
 178
 179         if (sel == dap->select)
 180                 return ERROR_OK;
 181
 182         dap->select = sel;
 183
 184         int retval = swd_queue_dp_write(dap, DP_SELECT, sel);
 185         if (retval != ERROR_OK)
 186                 dap->select = DP_SELECT_INVALID;
 187
 188         return retval;
 189 }
 190
 191 static int swd_queue_dp_read(struct adiv5_dap *dap, unsigned reg,
 192                 uint32_t *data)
 193 {
 194         const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
 195         assert(swd);
 196
 197         int retval = swd_check_reconnect(dap);
 198         if (retval != ERROR_OK)
 199                 return retval;
 200
 201         retval = swd_queue_dp_bankselect(dap, reg);
 202         if (retval != ERROR_OK)
 203                 return retval;
 204
 205         swd->read_reg(swd_cmd(true,  false, reg), data, 0);
 206
 207         return check_sync(dap);
 208 }
 209
 210 static int swd_queue_dp_write(struct adiv5_dap *dap, unsigned reg,
 211                 uint32_t data)
 212 {
 213         const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
 214         assert(swd);
 215
 216         int retval = swd_check_reconnect(dap);
 217         if (retval != ERROR_OK)
 218                 return retval;
 219
 220         swd_finish_read(dap);
 221         if (reg == DP_SELECT) {
 222                 dap->select = data & (DP_SELECT_APSEL | DP_SELECT_APBANK | DP_SELECT_DPBANK);
 223
 224                 swd->write_reg(swd_cmd(false,  false, reg), data, 0);
 225
 226                 retval = check_sync(dap);
 227                 if (retval != ERROR_OK)
 228                         dap->select = DP_SELECT_INVALID;
 229
 230                 return retval;
 231         }
 232
 233         retval = swd_queue_dp_bankselect(dap, reg);
 234         if (retval != ERROR_OK)
 235                 return retval;
 236
 237         swd->write_reg(swd_cmd(false,  false, reg), data, 0);
 238
 239         return check_sync(dap);
 240 }
 241
 242 /** Select the AP register bank matching bits 7:4 of reg. */
 243 static int swd_queue_ap_bankselect(struct adiv5_ap *ap, unsigned reg)
 244 {
 245         struct adiv5_dap *dap = ap->dap;
 246         uint32_t sel = ((uint32_t)ap->ap_num << 24)
 247                         | (reg & 0x000000F0)
 248                         | (dap->select & DP_SELECT_DPBANK);
 249
 250         if (sel == dap->select)
 251                 return ERROR_OK;
 252
 253         dap->select = sel;
 254
 255         int retval = swd_queue_dp_write(dap, DP_SELECT, sel);
 256         if (retval != ERROR_OK)
 257                 dap->select = DP_SELECT_INVALID;
 258
 259         return retval;
 260 }
 261
 262 static int swd_queue_ap_read(struct adiv5_ap *ap, unsigned reg,
 263                 uint32_t *data)
 264 {
 265         struct adiv5_dap *dap = ap->dap;
 266         const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
 267         assert(swd);
 268
 269         int retval = swd_check_reconnect(dap);
 270         if (retval != ERROR_OK)
 271                 return retval;
 272
 273         retval = swd_queue_ap_bankselect(ap, reg);
 274         if (retval != ERROR_OK)
 275                 return retval;
 276
 277         swd->read_reg(swd_cmd(true,  true, reg), dap->last_read, ap->memaccess_tck);
 278         dap->last_read = data;
 279
 280         return check_sync(dap);
 281 }
 282
 283 static int swd_queue_ap_write(struct adiv5_ap *ap, unsigned reg,
 284                 uint32_t data)
 285 {
 286         struct adiv5_dap *dap = ap->dap;
 287         const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
 288         assert(swd);
 289
 290         int retval = swd_check_reconnect(dap);
 291         if (retval != ERROR_OK)
 292                 return retval;
 293
 294         swd_finish_read(dap);
 295         retval = swd_queue_ap_bankselect(ap, reg);
 296         if (retval != ERROR_OK)
 297                 return retval;
 298
 299         swd->write_reg(swd_cmd(false,  true, reg), data, ap->memaccess_tck);
 300
 301         return check_sync(dap);
 302 }
 303
 304 /** Executes all queued DAP operations. */
 305 static int swd_run(struct adiv5_dap *dap)
 306 {
 307         swd_finish_read(dap);
 308         return swd_run_inner(dap);
 309 }
 310
 311 /** Put the SWJ-DP back to JTAG mode */
 312 static void swd_quit(struct adiv5_dap *dap)
 313 {
 314         const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
 315
 316         swd->switch_seq(SWD_TO_JTAG);
 317         /* flush the queue before exit */
 318         swd->run();
 319 }
 320
 321 const struct dap_ops swd_dap_ops = {
 322         .connect = swd_connect,
 323         .queue_dp_read = swd_queue_dp_read,
 324         .queue_dp_write = swd_queue_dp_write,
 325         .queue_ap_read = swd_queue_ap_read,
 326         .queue_ap_write = swd_queue_ap_write,
 327         .queue_ap_abort = swd_queue_ap_abort,
 328         .run = swd_run,
 329         .quit = swd_quit,
 330 };
 331
 332 static const struct command_registration swd_commands[] = {
 333         {
 334                 /*
 335                  * Set up SWD and JTAG targets identically, unless/until
 336                  * infrastructure improves ...  meanwhile, ignore all
 337                  * JTAG-specific stuff like IR length for SWD.
 338                  *
 339                  * REVISIT can we verify "just one SWD DAP" here/early?
 340                  */
 341                 .name = "newdap",
 342                 .jim_handler = jim_jtag_newtap,
 343                 .mode = COMMAND_CONFIG,
 344                 .help = "declare a new SWD DAP"
 345         },
 346         COMMAND_REGISTRATION_DONE
 347 };
 348
 349 static const struct command_registration swd_handlers[] = {
 350         {
 351                 .name = "swd",
 352                 .mode = COMMAND_ANY,
 353                 .help = "SWD command group",
 354                 .chain = swd_commands,
 355                 .usage = "",
 356         },
 357         COMMAND_REGISTRATION_DONE
 358 };
 359
 360 static int swd_select(struct command_context *ctx)
 361 {
 362         /* FIXME: only place where global 'jtag_interface' is still needed */
 363         extern struct jtag_interface *jtag_interface;
 364         const struct swd_driver *swd = jtag_interface->swd;
 365         int retval;
 366
 367         retval = register_commands(ctx, NULL, swd_handlers);
 368         if (retval != ERROR_OK)
 369                 return retval;
 370
 371          /* be sure driver is in SWD mode; start
 372           * with hardware default TRN (1), it can be changed later
 373           */
 374         if (!swd || !swd->read_reg || !swd->write_reg || !swd->init) {
 375                 LOG_DEBUG("no SWD driver?");
 376                 return ERROR_FAIL;
 377         }
 378
 379         retval = swd->init();
 380         if (retval != ERROR_OK) {
 381                 LOG_DEBUG("can't init SWD driver");
 382                 return retval;
 383         }
 384
 385         return retval;
 386 }
 387
 388 static int swd_init(struct command_context *ctx)
 389 {
 390         /* nothing done here, SWD is initialized
 391          * together with the DAP */
 392         return ERROR_OK;
 393 }
 394
 395 static struct transport swd_transport = {
 396         .name = "swd",
 397         .select = swd_select,
 398         .init = swd_init,
 399 };
 400
 401 static void swd_constructor(void) __attribute__((constructor));
 402 static void swd_constructor(void)
 403 {
 404         transport_register(&swd_transport);
 405 }
 406
 407 /** Returns true if the current debug session
 408  * is using SWD as its transport.
 409  */
 410 bool transport_is_swd(void)
 411 {
 412         return get_current_transport() == &swd_transport;
 413 }