src/target/adi_v5_jtag.c

   1 /***************************************************************************
   2  *   Copyright (C) 2006 by Magnus Lundin
   3  *   lundin@mlu.mine.nu
   4  *
   5  *   Copyright (C) 2008 by Spencer Oliver
   6  *   spen@spen-soft.co.uk
   7  *
   8  *   Copyright (C) 2009 by Oyvind Harboe
   9  *   oyvind.harboe@zylin.com
  10  *
  11  *   Copyright (C) 2009-2010 by David Brownell
  12  *
  13  *   This program is free software; you can redistribute it and/or modify
  14  *   it under the terms of the GNU General Public License as published by
  15  *   the Free Software Foundation; either version 2 of the License, or
  16  *   (at your option) any later version.
  17  *
  18  *   This program is distributed in the hope that it will be useful,
  19  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  *   GNU General Public License for more details.
  22  *
  23  *   You should have received a copy of the GNU General Public License
  24  *   along with this program; if not, write to the
  25  *   Free Software Foundation, Inc.,
  26  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  27  ***************************************************************************/
  28
  29 /**
  30  * @file
  31  * This file implements JTAG transport support for cores implementing
  32  the ARM Debug Interface version 5 (ADIv5).
  33  */
  34
  35 #ifdef HAVE_CONFIG_H
  36 #include "config.h"
  37 #endif
  38
  39 #include "arm.h"
  40 #include "arm_adi_v5.h"
  41 #include <helper/time_support.h>
  42
  43
  44 /* JTAG instructions/registers for JTAG-DP and SWJ-DP */
  45 #define JTAG_DP_ABORT           0x8
  46 #define JTAG_DP_DPACC           0xA
  47 #define JTAG_DP_APACC           0xB
  48 #define JTAG_DP_IDCODE          0xE
  49
  50 /* three-bit ACK values for DPACC and APACC reads */
  51 #define JTAG_ACK_OK_FAULT       0x2
  52 #define JTAG_ACK_WAIT           0x1
  53
  54 /***************************************************************************
  55  *
  56  * DPACC and APACC scanchain access through JTAG-DP (or SWJ-DP)
  57  *
  58 ***************************************************************************/
  59
  60 /**
  61  * Scan DPACC or APACC using target ordered uint8_t buffers.  No endianness
  62  * conversions are performed.  See section 4.4.3 of the ADIv5 spec, which
  63  * discusses operations which access these registers.
  64  *
  65  * Note that only one scan is performed.  If RnW is set, a separate scan
  66  * will be needed to collect the data which was read; the "invalue" collects
  67  * the posted result of a preceding operation, not the current one.
  68  *
  69  * @param swjdp the DAP
  70  * @param instr JTAG_DP_APACC (AP access) or JTAG_DP_DPACC (DP access)
  71  * @param reg_addr two significant bits; A[3:2]; for APACC access, the
  72  *      SELECT register has more addressing bits.
  73  * @param RnW false iff outvalue will be written to the DP or AP
  74  * @param outvalue points to a 32-bit (little-endian) integer
  75  * @param invalue NULL, or points to a 32-bit (little-endian) integer
  76  * @param ack points to where the three bit JTAG_ACK_* code will be stored
  77  */
  78
  79 /* FIXME don't export ... this is a temporary workaround for the
  80  * mem_ap_read_buf_u32() mess, until it's no longer JTAG-specific.
  81  */
  82 int adi_jtag_dp_scan(struct adiv5_dap *swjdp,
  83                 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
  84                 uint8_t *outvalue, uint8_t *invalue, uint8_t *ack)
  85 {
  86         struct arm_jtag *jtag_info = swjdp->jtag_info;
  87         struct scan_field fields[2];
  88         uint8_t out_addr_buf;
  89
  90         jtag_set_end_state(TAP_IDLE);
  91         arm_jtag_set_instr(jtag_info, instr, NULL, TAP_IDLE);
  92
  93         /* Scan out a read or write operation using some DP or AP register.
  94          * For APACC access with any sticky error flag set, this is discarded.
  95          */
  96         fields[0].num_bits = 3;
  97         buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr >> 1) & 0x6) | (RnW & 0x1));
  98         fields[0].out_value = &out_addr_buf;
  99         fields[0].in_value = ack;
 100
 101         /* NOTE: if we receive JTAG_ACK_WAIT, the previous operation did not
 102          * complete; data we write is discarded, data we read is unpredictable.
 103          * When overrun detect is active, STICKYORUN is set.
 104          */
 105
 106         fields[1].num_bits = 32;
 107         fields[1].out_value = outvalue;
 108         fields[1].in_value = invalue;
 109
 110         jtag_add_dr_scan(jtag_info->tap, 2, fields, TAP_IDLE);
 111
 112         /* Add specified number of tck clocks after starting memory bus
 113          * access, giving the hardware time to complete the access.
 114          * They provide more time for the (MEM) AP to complete the read ...
 115          * See "Minimum Response Time" for JTAG-DP, in the ADIv5 spec.
 116          */
 117         if ((instr == JTAG_DP_APACC)
 118                         && ((reg_addr == AP_REG_DRW)
 119                                 || ((reg_addr & 0xF0) == AP_REG_BD0))
 120                         && (swjdp->memaccess_tck != 0))
 121                 jtag_add_runtest(swjdp->memaccess_tck,
 122                                 TAP_IDLE);
 123
 124         return jtag_get_error();
 125 }
 126
 127 /**
 128  * Scan DPACC or APACC out and in from host ordered uint32_t buffers.
 129  * This is exactly like adi_jtag_dp_scan(), except that endianness
 130  * conversions are performed (so the types of invalue and outvalue
 131  * must be different).
 132  */
 133 static int adi_jtag_dp_scan_u32(struct adiv5_dap *swjdp,
 134                 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
 135                 uint32_t outvalue, uint32_t *invalue, uint8_t *ack)
 136 {
 137         uint8_t out_value_buf[4];
 138         int retval;
 139
 140         buf_set_u32(out_value_buf, 0, 32, outvalue);
 141
 142         retval = adi_jtag_dp_scan(swjdp, instr, reg_addr, RnW,
 143                         out_value_buf, (uint8_t *)invalue, ack);
 144         if (retval != ERROR_OK)
 145                 return retval;
 146
 147         if (invalue)
 148                 jtag_add_callback(arm_le_to_h_u32,
 149                                 (jtag_callback_data_t) invalue);
 150
 151         return retval;
 152 }
 153
 154 /**
 155  * Utility to write AP registers.
 156  */
 157 static inline int adi_jtag_ap_write_check(struct adiv5_dap *dap,
 158                 uint8_t reg_addr, uint8_t *outvalue)
 159 {
 160         return adi_jtag_dp_scan(dap, JTAG_DP_APACC, reg_addr, DPAP_WRITE,
 161                         outvalue, NULL, NULL);
 162 }
 163
 164 static int adi_jtag_scan_inout_check_u32(struct adiv5_dap *swjdp,
 165                 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
 166                 uint32_t outvalue, uint32_t *invalue)
 167 {
 168         int retval;
 169
 170         /* Issue the read or write */
 171         retval = adi_jtag_dp_scan_u32(swjdp, instr, reg_addr,
 172                         RnW, outvalue, NULL, NULL);
 173         if (retval != ERROR_OK)
 174                 return retval;
 175
 176         /* For reads,  collect posted value; RDBUFF has no other effect.
 177          * Assumes read gets acked with OK/FAULT, and CTRL_STAT says "OK".
 178          */
 179         if ((RnW == DPAP_READ) && (invalue != NULL))
 180                 retval = adi_jtag_dp_scan_u32(swjdp, JTAG_DP_DPACC,
 181                                 DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack);
 182         return retval;
 183 }
 184
 185 static int jtagdp_transaction_endcheck(struct adiv5_dap *swjdp)
 186 {
 187         int retval;
 188         uint32_t ctrlstat;
 189
 190         /* too expensive to call keep_alive() here */
 191
 192 #if 0
 193         /* Danger!!!! BROKEN!!!! */
 194         adi_jtag_scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
 195                         DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
 196         /* Danger!!!! BROKEN!!!! Why will jtag_execute_queue() fail here????
 197         R956 introduced the check on return value here and now Michael Schwingen reports
 198         that this code no longer works....
 199
 200         https://lists.berlios.de/pipermail/openocd-development/2008-September/003107.html
 201         */
 202         if ((retval = jtag_execute_queue()) != ERROR_OK)
 203         {
 204                 LOG_ERROR("BUG: Why does this fail the first time????");
 205         }
 206         /* Why??? second time it works??? */
 207 #endif
 208
 209         /* Post CTRL/STAT read; discard any previous posted read value
 210          * but collect its ACK status.
 211          */
 212         adi_jtag_scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
 213                         DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
 214         if ((retval = jtag_execute_queue()) != ERROR_OK)
 215                 return retval;
 216
 217         swjdp->ack = swjdp->ack & 0x7;
 218
 219         /* common code path avoids calling timeval_ms() */
 220         if (swjdp->ack != JTAG_ACK_OK_FAULT)
 221         {
 222                 long long then = timeval_ms();
 223
 224                 while (swjdp->ack != JTAG_ACK_OK_FAULT)
 225                 {
 226                         if (swjdp->ack == JTAG_ACK_WAIT)
 227                         {
 228                                 if ((timeval_ms()-then) > 1000)
 229                                 {
 230                                         /* NOTE:  this would be a good spot
 231                                          * to use JTAG_DP_ABORT.
 232                                          */
 233                                         LOG_WARNING("Timeout (1000ms) waiting "
 234                                                 "for ACK=OK/FAULT "
 235                                                 "in JTAG-DP transaction");
 236                                         return ERROR_JTAG_DEVICE_ERROR;
 237                                 }
 238                         }
 239                         else
 240                         {
 241                                 LOG_WARNING("Invalid ACK %#x "
 242                                                 "in JTAG-DP transaction",
 243                                                 swjdp->ack);
 244                                 return ERROR_JTAG_DEVICE_ERROR;
 245                         }
 246
 247                         adi_jtag_scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
 248                                         DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
 249                         if ((retval = dap_run(swjdp)) != ERROR_OK)
 250                                 return retval;
 251                         swjdp->ack = swjdp->ack & 0x7;
 252                 }
 253         }
 254
 255         /* REVISIT also STICKYCMP, for pushed comparisons (nyet used) */
 256
 257         /* Check for STICKYERR and STICKYORUN */
 258         if (ctrlstat & (SSTICKYORUN | SSTICKYERR))
 259         {
 260                 LOG_DEBUG("jtag-dp: CTRL/STAT error, 0x%" PRIx32, ctrlstat);
 261                 /* Check power to debug regions */
 262                 if ((ctrlstat & 0xf0000000) != 0xf0000000)
 263                          ahbap_debugport_init(swjdp);
 264                 else
 265                 {
 266                         uint32_t mem_ap_csw, mem_ap_tar;
 267
 268                         /* Maybe print information about last intended
 269                          * MEM-AP access; but not if autoincrementing.
 270                          * *Real* CSW and TAR values are always shown.
 271                          */
 272                         if (swjdp->ap_tar_value != (uint32_t) -1)
 273                                 LOG_DEBUG("MEM-AP Cached values: "
 274                                         "ap_bank 0x%" PRIx32
 275                                         ", ap_csw 0x%" PRIx32
 276                                         ", ap_tar 0x%" PRIx32,
 277                                         swjdp->ap_bank_value,
 278                                         swjdp->ap_csw_value,
 279                                         swjdp->ap_tar_value);
 280
 281                         if (ctrlstat & SSTICKYORUN)
 282                                 LOG_ERROR("JTAG-DP OVERRUN - check clock, "
 283                                         "memaccess, or reduce jtag speed");
 284
 285                         if (ctrlstat & SSTICKYERR)
 286                                 LOG_ERROR("JTAG-DP STICKY ERROR");
 287
 288                         /* Clear Sticky Error Bits */
 289                         adi_jtag_scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
 290                                         DP_CTRL_STAT, DPAP_WRITE,
 291                                         swjdp->dp_ctrl_stat | SSTICKYORUN
 292                                                 | SSTICKYERR, NULL);
 293                         adi_jtag_scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
 294                                         DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
 295                         if ((retval = dap_run(swjdp)) != ERROR_OK)
 296                                 return retval;
 297
 298                         LOG_DEBUG("jtag-dp: CTRL/STAT 0x%" PRIx32, ctrlstat);
 299
 300                         retval = dap_queue_ap_read(swjdp,
 301                                         AP_REG_CSW, &mem_ap_csw);
 302                         if (retval != ERROR_OK)
 303                                 return retval;
 304
 305                         retval = dap_queue_ap_read(swjdp,
 306                                         AP_REG_TAR, &mem_ap_tar);
 307                         if (retval != ERROR_OK)
 308                                 return retval;
 309
 310                         if ((retval = dap_run(swjdp)) != ERROR_OK)
 311                                 return retval;
 312                         LOG_ERROR("MEM_AP_CSW 0x%" PRIx32 ", MEM_AP_TAR 0x%"
 313                                         PRIx32, mem_ap_csw, mem_ap_tar);
 314
 315                 }
 316                 if ((retval = dap_run(swjdp)) != ERROR_OK)
 317                         return retval;
 318                 return ERROR_JTAG_DEVICE_ERROR;
 319         }
 320
 321         return ERROR_OK;
 322 }
 323
 324 /*--------------------------------------------------------------------------*/
 325
 326 static int jtag_idcode_q_read(struct adiv5_dap *dap,
 327                 uint8_t *ack, uint32_t *data)
 328 {
 329         struct arm_jtag *jtag_info = dap->jtag_info;
 330         int retval;
 331         struct scan_field fields[1];
 332
 333         /* This is a standard JTAG operation -- no DAP tweakage */
 334         jtag_set_end_state(TAP_IDLE);
 335         retval = arm_jtag_set_instr(jtag_info, JTAG_DP_IDCODE, NULL, TAP_IDLE);
 336         if (retval != ERROR_OK)
 337                 return retval;
 338
 339         fields[0].num_bits = 32;
 340         fields[0].out_value = NULL;
 341         fields[0].in_value = (void *) data;
 342
 343         jtag_add_dr_scan(jtag_info->tap, 1, fields, TAP_IDLE);
 344         retval = jtag_get_error();
 345         if (retval != ERROR_OK)
 346                 return retval;
 347
 348         jtag_add_callback(arm_le_to_h_u32,
 349                         (jtag_callback_data_t) data);
 350
 351         return retval;
 352 }
 353
 354 static int jtag_dp_q_read(struct adiv5_dap *dap, unsigned reg,
 355                 uint32_t *data)
 356 {
 357         return adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
 358                         reg, DPAP_READ, 0, data);
 359 }
 360
 361 static int jtag_dp_q_write(struct adiv5_dap *dap, unsigned reg,
 362                 uint32_t data)
 363 {
 364         return adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
 365                         reg, DPAP_WRITE, data, NULL);
 366 }
 367
 368 /** Select the AP register bank matching bits 7:4 of reg. */
 369 static int jtag_ap_q_bankselect(struct adiv5_dap *dap, unsigned reg)
 370 {
 371         uint32_t select = reg & 0x000000F0;
 372
 373         if (select == dap->ap_bank_value)
 374                 return ERROR_OK;
 375         dap->ap_bank_value = select;
 376
 377         select |= dap->apsel;
 378
 379         return jtag_dp_q_write(dap, DP_SELECT, select);
 380 }
 381
 382 static int jtag_ap_q_read(struct adiv5_dap *dap, unsigned reg,
 383                 uint32_t *data)
 384 {
 385         int retval = jtag_ap_q_bankselect(dap, reg);
 386
 387         if (retval != ERROR_OK)
 388                 return retval;
 389
 390         return adi_jtag_scan_inout_check_u32(dap, JTAG_DP_APACC, reg,
 391                         DPAP_READ, 0, data);
 392 }
 393
 394 static int jtag_ap_q_write(struct adiv5_dap *dap, unsigned reg,
 395                 uint32_t data)
 396 {
 397         uint8_t out_value_buf[4];
 398
 399         int retval = jtag_ap_q_bankselect(dap, reg);
 400         if (retval != ERROR_OK)
 401                 return retval;
 402
 403         buf_set_u32(out_value_buf, 0, 32, data);
 404
 405         return adi_jtag_ap_write_check(dap, reg, out_value_buf);
 406 }
 407
 408 static int jtag_ap_q_abort(struct adiv5_dap *dap, uint8_t *ack)
 409 {
 410         /* for JTAG, this is the only valid ABORT register operation */
 411         return adi_jtag_dp_scan_u32(dap, JTAG_DP_ABORT,
 412                         0, DPAP_WRITE, 1, NULL, ack);
 413 }
 414
 415 static int jtag_dp_run(struct adiv5_dap *dap)
 416 {
 417         return jtagdp_transaction_endcheck(dap);
 418 }
 419
 420 /* FIXME don't export ... just initialize as
 421  * part of DAP setup
 422 */
 423 const struct dap_ops jtag_dp_ops = {
 424         .queue_idcode_read =    jtag_idcode_q_read,
 425         .queue_dp_read =        jtag_dp_q_read,
 426         .queue_dp_write =       jtag_dp_q_write,
 427         .queue_ap_read =        jtag_ap_q_read,
 428         .queue_ap_write =       jtag_ap_q_write,
 429         .queue_ap_abort =       jtag_ap_q_abort,
 430         .run =                  jtag_dp_run,
 431 };
 432
 433
 434 const uint8_t swd2jtag_bitseq[] = {
 435         /* More than 50 TCK/SWCLK cycles with TMS/SWDIO high,
 436          * putting both JTAG and SWD logic into reset state.
 437          */
 438         0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 439         /* Switching equence disables SWD and enables JTAG
 440          * NOTE: bits in the DP's IDCODE can expose the need for
 441          * the old/deprecated sequence (0xae 0xde).
 442          */
 443         0x3c, 0xe7,
 444         /* At least 50 TCK/SWCLK cycles with TMS/SWDIO high,
 445          * putting both JTAG and SWD logic into reset state.
 446          * NOTE:  some docs say "at least 5".
 447          */
 448         0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 449 };
 450
 451 /** Put the debug link into JTAG mode, if the target supports it.
 452  * The link's initial mode may be either SWD or JTAG.
 453  *
 454  * @param target Enters JTAG mode (if possible).
 455  *
 456  * Note that targets implemented with SW-DP do not support JTAG, and
 457  * that some targets which could otherwise support it may have been
 458  * configured to disable JTAG signaling
 459  *
 460  * @return ERROR_OK or else a fault code.
 461  */
 462 int dap_to_jtag(struct target *target)
 463 {
 464         int retval;
 465
 466         LOG_DEBUG("Enter JTAG mode");
 467
 468         /* REVISIT it's nasty to need to make calls to a "jtag"
 469          * subsystem if the link isn't in JTAG mode...
 470          */
 471
 472         retval = jtag_add_tms_seq(8 * sizeof(swd2jtag_bitseq),
 473                         swd2jtag_bitseq, TAP_RESET);
 474         if (retval == ERROR_OK)
 475                 retval = jtag_execute_queue();
 476
 477         /* REVISIT set up the DAP's ops vector for JTAG mode. */
 478
 479         return retval;
 480 }