build: cleanup src/target directory
[openocd.git] / src / target / adi_v5_jtag.c
1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin
3 * lundin@mlu.mine.nu
4 *
5 * Copyright (C) 2008 by Spencer Oliver
6 * spen@spen-soft.co.uk
7 *
8 * Copyright (C) 2009 by Oyvind Harboe
9 * oyvind.harboe@zylin.com
10 *
11 * Copyright (C) 2009-2010 by David Brownell
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the
25 * Free Software Foundation, Inc.,
26 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
27 ***************************************************************************/
28
29 /**
30 * @file
31 * This file implements JTAG transport support for cores implementing
32 the ARM Debug Interface version 5 (ADIv5).
33 */
34
35 #ifdef HAVE_CONFIG_H
36 #include "config.h"
37 #endif
38
39 #include "arm.h"
40 #include "arm_adi_v5.h"
41 #include <helper/time_support.h>
42
43 /* JTAG instructions/registers for JTAG-DP and SWJ-DP */
44 #define JTAG_DP_ABORT 0x8
45 #define JTAG_DP_DPACC 0xA
46 #define JTAG_DP_APACC 0xB
47 #define JTAG_DP_IDCODE 0xE
48
49 /* three-bit ACK values for DPACC and APACC reads */
50 #define JTAG_ACK_OK_FAULT 0x2
51 #define JTAG_ACK_WAIT 0x1
52
53 /***************************************************************************
54 *
55 * DPACC and APACC scanchain access through JTAG-DP (or SWJ-DP)
56 *
57 ***************************************************************************/
58
59 /**
60 * Scan DPACC or APACC using target ordered uint8_t buffers. No endianness
61 * conversions are performed. See section 4.4.3 of the ADIv5 spec, which
62 * discusses operations which access these registers.
63 *
64 * Note that only one scan is performed. If RnW is set, a separate scan
65 * will be needed to collect the data which was read; the "invalue" collects
66 * the posted result of a preceding operation, not the current one.
67 *
68 * @param dap the DAP
69 * @param instr JTAG_DP_APACC (AP access) or JTAG_DP_DPACC (DP access)
70 * @param reg_addr two significant bits; A[3:2]; for APACC access, the
71 * SELECT register has more addressing bits.
72 * @param RnW false iff outvalue will be written to the DP or AP
73 * @param outvalue points to a 32-bit (little-endian) integer
74 * @param invalue NULL, or points to a 32-bit (little-endian) integer
75 * @param ack points to where the three bit JTAG_ACK_* code will be stored
76 */
77
78 /* FIXME don't export ... this is a temporary workaround for the
79 * mem_ap_read_buf_u32() mess, until it's no longer JTAG-specific.
80 */
81 int adi_jtag_dp_scan(struct adiv5_dap *dap,
82 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
83 uint8_t *outvalue, uint8_t *invalue, uint8_t *ack)
84 {
85 struct arm_jtag *jtag_info = dap->jtag_info;
86 struct scan_field fields[2];
87 uint8_t out_addr_buf;
88 int retval;
89
90 retval = arm_jtag_set_instr(jtag_info, instr, NULL, TAP_IDLE);
91 if (retval != ERROR_OK)
92 return retval;
93
94 /* Scan out a read or write operation using some DP or AP register.
95 * For APACC access with any sticky error flag set, this is discarded.
96 */
97 fields[0].num_bits = 3;
98 buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr >> 1) & 0x6) | (RnW & 0x1));
99 fields[0].out_value = &out_addr_buf;
100 fields[0].in_value = ack;
101
102 /* NOTE: if we receive JTAG_ACK_WAIT, the previous operation did not
103 * complete; data we write is discarded, data we read is unpredictable.
104 * When overrun detect is active, STICKYORUN is set.
105 */
106
107 fields[1].num_bits = 32;
108 fields[1].out_value = outvalue;
109 fields[1].in_value = invalue;
110
111 jtag_add_dr_scan(jtag_info->tap, 2, fields, TAP_IDLE);
112
113 /* Add specified number of tck clocks after starting memory bus
114 * access, giving the hardware time to complete the access.
115 * They provide more time for the (MEM) AP to complete the read ...
116 * See "Minimum Response Time" for JTAG-DP, in the ADIv5 spec.
117 */
118 if ((instr == JTAG_DP_APACC)
119 && ((reg_addr == AP_REG_DRW)
120 || ((reg_addr & 0xF0) == AP_REG_BD0))
121 && (dap->memaccess_tck != 0))
122 jtag_add_runtest(dap->memaccess_tck,
123 TAP_IDLE);
124
125 return ERROR_OK;
126 }
127
128 /**
129 * Scan DPACC or APACC out and in from host ordered uint32_t buffers.
130 * This is exactly like adi_jtag_dp_scan(), except that endianness
131 * conversions are performed (so the types of invalue and outvalue
132 * must be different).
133 */
134 static int adi_jtag_dp_scan_u32(struct adiv5_dap *dap,
135 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
136 uint32_t outvalue, uint32_t *invalue, uint8_t *ack)
137 {
138 uint8_t out_value_buf[4];
139 int retval;
140
141 buf_set_u32(out_value_buf, 0, 32, outvalue);
142
143 retval = adi_jtag_dp_scan(dap, instr, reg_addr, RnW,
144 out_value_buf, (uint8_t *)invalue, ack);
145 if (retval != ERROR_OK)
146 return retval;
147
148 if (invalue)
149 jtag_add_callback(arm_le_to_h_u32,
150 (jtag_callback_data_t) invalue);
151
152 return retval;
153 }
154
155 /**
156 * Utility to write AP registers.
157 */
158 static inline int adi_jtag_ap_write_check(struct adiv5_dap *dap,
159 uint8_t reg_addr, uint8_t *outvalue)
160 {
161 return adi_jtag_dp_scan(dap, JTAG_DP_APACC, reg_addr, DPAP_WRITE,
162 outvalue, NULL, NULL);
163 }
164
165 static int adi_jtag_scan_inout_check_u32(struct adiv5_dap *dap,
166 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
167 uint32_t outvalue, uint32_t *invalue)
168 {
169 int retval;
170
171 /* Issue the read or write */
172 retval = adi_jtag_dp_scan_u32(dap, instr, reg_addr,
173 RnW, outvalue, NULL, NULL);
174 if (retval != ERROR_OK)
175 return retval;
176
177 /* For reads, collect posted value; RDBUFF has no other effect.
178 * Assumes read gets acked with OK/FAULT, and CTRL_STAT says "OK".
179 */
180 if ((RnW == DPAP_READ) && (invalue != NULL))
181 retval = adi_jtag_dp_scan_u32(dap, JTAG_DP_DPACC,
182 DP_RDBUFF, DPAP_READ, 0, invalue, &dap->ack);
183 return retval;
184 }
185
186 static int jtagdp_transaction_endcheck(struct adiv5_dap *dap)
187 {
188 int retval;
189 uint32_t ctrlstat;
190
191 /* too expensive to call keep_alive() here */
192
193 /* Here be dragons!
194 *
195 * It is easy to be in a JTAG clock range where the target
196 * is not operating in a stable fashion. This happens
197 * for a few reasons:
198 *
199 * - the user may construct a simple test case to try to see
200 * if a higher JTAG clock works to eke out more performance.
201 * This simple case may pass, but more complex situations can
202 * fail.
203 *
204 * - The mostly works JTAG clock rate and the complete failure
205 * JTAG clock rate may be as much as 2-4x apart. This seems
206 * to be especially true on RC oscillator driven parts.
207 *
208 * So: even if calling adi_jtag_scan_inout_check_u32() multiple
209 * times here seems to "make things better here", it is just
210 * hiding problems with too high a JTAG clock.
211 *
212 * Note that even if some parts have RCLK/RTCK, that doesn't
213 * mean that RCLK/RTCK is the *correct* rate to run the JTAG
214 * interface at, i.e. RCLK/RTCK rates can be "too high", especially
215 * before the RC oscillator phase is not yet complete.
216 */
217
218 /* Post CTRL/STAT read; discard any previous posted read value
219 * but collect its ACK status.
220 */
221 retval = adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
222 DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
223 if (retval != ERROR_OK)
224 return retval;
225 retval = jtag_execute_queue();
226 if (retval != ERROR_OK)
227 return retval;
228
229 dap->ack = dap->ack & 0x7;
230
231 /* common code path avoids calling timeval_ms() */
232 if (dap->ack != JTAG_ACK_OK_FAULT) {
233 long long then = timeval_ms();
234
235 while (dap->ack != JTAG_ACK_OK_FAULT) {
236 if (dap->ack == JTAG_ACK_WAIT) {
237 if ((timeval_ms()-then) > 1000) {
238 /* NOTE: this would be a good spot
239 * to use JTAG_DP_ABORT.
240 */
241 LOG_WARNING("Timeout (1000ms) waiting "
242 "for ACK=OK/FAULT "
243 "in JTAG-DP transaction");
244 return ERROR_JTAG_DEVICE_ERROR;
245 }
246 } else {
247 LOG_WARNING("Invalid ACK %#x "
248 "in JTAG-DP transaction",
249 dap->ack);
250 return ERROR_JTAG_DEVICE_ERROR;
251 }
252
253 retval = adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
254 DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
255 if (retval != ERROR_OK)
256 return retval;
257 retval = dap_run(dap);
258 if (retval != ERROR_OK)
259 return retval;
260 dap->ack = dap->ack & 0x7;
261 }
262 }
263
264 /* REVISIT also STICKYCMP, for pushed comparisons (nyet used) */
265
266 /* Check for STICKYERR and STICKYORUN */
267 if (ctrlstat & (SSTICKYORUN | SSTICKYERR)) {
268 LOG_DEBUG("jtag-dp: CTRL/STAT error, 0x%" PRIx32, ctrlstat);
269 /* Check power to debug regions */
270 if ((ctrlstat & 0xf0000000) != 0xf0000000) {
271 retval = ahbap_debugport_init(dap);
272 if (retval != ERROR_OK)
273 return retval;
274 } else {
275 uint32_t mem_ap_csw, mem_ap_tar;
276
277 /* Maybe print information about last intended
278 * MEM-AP access; but not if autoincrementing.
279 * *Real* CSW and TAR values are always shown.
280 */
281 if (dap->ap_tar_value != (uint32_t) -1)
282 LOG_DEBUG("MEM-AP Cached values: "
283 "ap_bank 0x%" PRIx32
284 ", ap_csw 0x%" PRIx32
285 ", ap_tar 0x%" PRIx32,
286 dap->ap_bank_value,
287 dap->ap_csw_value,
288 dap->ap_tar_value);
289
290 if (ctrlstat & SSTICKYORUN)
291 LOG_ERROR("JTAG-DP OVERRUN - check clock, "
292 "memaccess, or reduce jtag speed");
293
294 if (ctrlstat & SSTICKYERR)
295 LOG_ERROR("JTAG-DP STICKY ERROR");
296
297 /* Clear Sticky Error Bits */
298 retval = adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
299 DP_CTRL_STAT, DPAP_WRITE,
300 dap->dp_ctrl_stat | SSTICKYORUN
301 | SSTICKYERR, NULL);
302 if (retval != ERROR_OK)
303 return retval;
304 retval = adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
305 DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
306 if (retval != ERROR_OK)
307 return retval;
308 retval = dap_run(dap);
309 if (retval != ERROR_OK)
310 return retval;
311
312 LOG_DEBUG("jtag-dp: CTRL/STAT 0x%" PRIx32, ctrlstat);
313
314 retval = dap_queue_ap_read(dap,
315 AP_REG_CSW, &mem_ap_csw);
316 if (retval != ERROR_OK)
317 return retval;
318
319 retval = dap_queue_ap_read(dap,
320 AP_REG_TAR, &mem_ap_tar);
321 if (retval != ERROR_OK)
322 return retval;
323
324 retval = dap_run(dap);
325 if (retval != ERROR_OK)
326 return retval;
327 LOG_ERROR("MEM_AP_CSW 0x%" PRIx32 ", MEM_AP_TAR 0x%"
328 PRIx32, mem_ap_csw, mem_ap_tar);
329
330 }
331 retval = dap_run(dap);
332 if (retval != ERROR_OK)
333 return retval;
334 return ERROR_JTAG_DEVICE_ERROR;
335 }
336
337 return ERROR_OK;
338 }
339
340 /*--------------------------------------------------------------------------*/
341
342 static int jtag_idcode_q_read(struct adiv5_dap *dap,
343 uint8_t *ack, uint32_t *data)
344 {
345 struct arm_jtag *jtag_info = dap->jtag_info;
346 int retval;
347 struct scan_field fields[1];
348
349 /* This is a standard JTAG operation -- no DAP tweakage */
350 retval = arm_jtag_set_instr(jtag_info, JTAG_DP_IDCODE, NULL, TAP_IDLE);
351 if (retval != ERROR_OK)
352 return retval;
353
354 fields[0].num_bits = 32;
355 fields[0].out_value = NULL;
356 fields[0].in_value = (void *) data;
357
358 jtag_add_dr_scan(jtag_info->tap, 1, fields, TAP_IDLE);
359
360 jtag_add_callback(arm_le_to_h_u32,
361 (jtag_callback_data_t) data);
362
363 return ERROR_OK;
364 }
365
366 static int jtag_dp_q_read(struct adiv5_dap *dap, unsigned reg,
367 uint32_t *data)
368 {
369 return adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
370 reg, DPAP_READ, 0, data);
371 }
372
373 static int jtag_dp_q_write(struct adiv5_dap *dap, unsigned reg,
374 uint32_t data)
375 {
376 return adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
377 reg, DPAP_WRITE, data, NULL);
378 }
379
380 /** Select the AP register bank matching bits 7:4 of reg. */
381 static int jtag_ap_q_bankselect(struct adiv5_dap *dap, unsigned reg)
382 {
383 uint32_t select_ap_bank = reg & 0x000000F0;
384
385 if (select_ap_bank == dap->ap_bank_value)
386 return ERROR_OK;
387 dap->ap_bank_value = select_ap_bank;
388
389 select_ap_bank |= dap->ap_current;
390
391 return jtag_dp_q_write(dap, DP_SELECT, select_ap_bank);
392 }
393
394 static int jtag_ap_q_read(struct adiv5_dap *dap, unsigned reg,
395 uint32_t *data)
396 {
397 int retval = jtag_ap_q_bankselect(dap, reg);
398
399 if (retval != ERROR_OK)
400 return retval;
401
402 return adi_jtag_scan_inout_check_u32(dap, JTAG_DP_APACC, reg,
403 DPAP_READ, 0, data);
404 }
405
406 static int jtag_ap_q_write(struct adiv5_dap *dap, unsigned reg,
407 uint32_t data)
408 {
409 uint8_t out_value_buf[4];
410
411 int retval = jtag_ap_q_bankselect(dap, reg);
412 if (retval != ERROR_OK)
413 return retval;
414
415 buf_set_u32(out_value_buf, 0, 32, data);
416
417 return adi_jtag_ap_write_check(dap, reg, out_value_buf);
418 }
419
420 static int jtag_ap_q_abort(struct adiv5_dap *dap, uint8_t *ack)
421 {
422 /* for JTAG, this is the only valid ABORT register operation */
423 return adi_jtag_dp_scan_u32(dap, JTAG_DP_ABORT,
424 0, DPAP_WRITE, 1, NULL, ack);
425 }
426
427 static int jtag_dp_run(struct adiv5_dap *dap)
428 {
429 return jtagdp_transaction_endcheck(dap);
430 }
431
432 /* FIXME don't export ... just initialize as
433 * part of DAP setup
434 */
435 const struct dap_ops jtag_dp_ops = {
436 .queue_idcode_read = jtag_idcode_q_read,
437 .queue_dp_read = jtag_dp_q_read,
438 .queue_dp_write = jtag_dp_q_write,
439 .queue_ap_read = jtag_ap_q_read,
440 .queue_ap_write = jtag_ap_q_write,
441 .queue_ap_abort = jtag_ap_q_abort,
442 .run = jtag_dp_run,
443 };
444
445
446 static const uint8_t swd2jtag_bitseq[] = {
447 /* More than 50 TCK/SWCLK cycles with TMS/SWDIO high,
448 * putting both JTAG and SWD logic into reset state.
449 */
450 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
451 /* Switching equence disables SWD and enables JTAG
452 * NOTE: bits in the DP's IDCODE can expose the need for
453 * the old/deprecated sequence (0xae 0xde).
454 */
455 0x3c, 0xe7,
456 /* At least 50 TCK/SWCLK cycles with TMS/SWDIO high,
457 * putting both JTAG and SWD logic into reset state.
458 * NOTE: some docs say "at least 5".
459 */
460 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
461 };
462
463 /** Put the debug link into JTAG mode, if the target supports it.
464 * The link's initial mode may be either SWD or JTAG.
465 *
466 * @param target Enters JTAG mode (if possible).
467 *
468 * Note that targets implemented with SW-DP do not support JTAG, and
469 * that some targets which could otherwise support it may have been
470 * configured to disable JTAG signaling
471 *
472 * @return ERROR_OK or else a fault code.
473 */
474 int dap_to_jtag(struct target *target)
475 {
476 int retval;
477
478 LOG_DEBUG("Enter JTAG mode");
479
480 /* REVISIT it's nasty to need to make calls to a "jtag"
481 * subsystem if the link isn't in JTAG mode...
482 */
483
484 retval = jtag_add_tms_seq(8 * sizeof(swd2jtag_bitseq),
485 swd2jtag_bitseq, TAP_RESET);
486 if (retval == ERROR_OK)
487 retval = jtag_execute_queue();
488
489 /* REVISIT set up the DAP's ops vector for JTAG mode. */
490
491 return retval;
492 }