62eb7d12ffed0155d9db3cc3d7762159fad913db
[openocd.git] / src / target / adi_v5_jtag.c
1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin
3 * lundin@mlu.mine.nu
4 *
5 * Copyright (C) 2008 by Spencer Oliver
6 * spen@spen-soft.co.uk
7 *
8 * Copyright (C) 2009 by Oyvind Harboe
9 * oyvind.harboe@zylin.com
10 *
11 * Copyright (C) 2009-2010 by David Brownell
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the
25 * Free Software Foundation, Inc.,
26 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
27 ***************************************************************************/
28
29 /**
30 * @file
31 * This file implements JTAG transport support for cores implementing
32 the ARM Debug Interface version 5 (ADIv5).
33 */
34
35 #ifdef HAVE_CONFIG_H
36 #include "config.h"
37 #endif
38
39 #include "arm.h"
40 #include "arm_adi_v5.h"
41 #include <helper/time_support.h>
42
43 /* JTAG instructions/registers for JTAG-DP and SWJ-DP */
44 #define JTAG_DP_ABORT 0x8
45 #define JTAG_DP_DPACC 0xA
46 #define JTAG_DP_APACC 0xB
47 #define JTAG_DP_IDCODE 0xE
48
49 /* three-bit ACK values for DPACC and APACC reads */
50 #define JTAG_ACK_OK_FAULT 0x2
51 #define JTAG_ACK_WAIT 0x1
52
53 static int jtag_ap_q_abort(struct adiv5_dap *dap, uint8_t *ack);
54
55 /***************************************************************************
56 *
57 * DPACC and APACC scanchain access through JTAG-DP (or SWJ-DP)
58 *
59 ***************************************************************************/
60
61 /**
62 * Scan DPACC or APACC using target ordered uint8_t buffers. No endianness
63 * conversions are performed. See section 4.4.3 of the ADIv5 spec, which
64 * discusses operations which access these registers.
65 *
66 * Note that only one scan is performed. If RnW is set, a separate scan
67 * will be needed to collect the data which was read; the "invalue" collects
68 * the posted result of a preceding operation, not the current one.
69 *
70 * @param dap the DAP
71 * @param instr JTAG_DP_APACC (AP access) or JTAG_DP_DPACC (DP access)
72 * @param reg_addr two significant bits; A[3:2]; for APACC access, the
73 * SELECT register has more addressing bits.
74 * @param RnW false iff outvalue will be written to the DP or AP
75 * @param outvalue points to a 32-bit (little-endian) integer
76 * @param invalue NULL, or points to a 32-bit (little-endian) integer
77 * @param ack points to where the three bit JTAG_ACK_* code will be stored
78 */
79
80 static int adi_jtag_dp_scan(struct adiv5_dap *dap,
81 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
82 uint8_t *outvalue, uint8_t *invalue, uint8_t *ack)
83 {
84 struct arm_jtag *jtag_info = dap->jtag_info;
85 struct scan_field fields[2];
86 uint8_t out_addr_buf;
87 int retval;
88
89 retval = arm_jtag_set_instr(jtag_info, instr, NULL, TAP_IDLE);
90 if (retval != ERROR_OK)
91 return retval;
92
93 /* Scan out a read or write operation using some DP or AP register.
94 * For APACC access with any sticky error flag set, this is discarded.
95 */
96 fields[0].num_bits = 3;
97 buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr >> 1) & 0x6) | (RnW & 0x1));
98 fields[0].out_value = &out_addr_buf;
99 fields[0].in_value = ack;
100
101 /* NOTE: if we receive JTAG_ACK_WAIT, the previous operation did not
102 * complete; data we write is discarded, data we read is unpredictable.
103 * When overrun detect is active, STICKYORUN is set.
104 */
105
106 fields[1].num_bits = 32;
107 fields[1].out_value = outvalue;
108 fields[1].in_value = invalue;
109
110 jtag_add_dr_scan(jtag_info->tap, 2, fields, TAP_IDLE);
111
112 /* Add specified number of tck clocks after starting memory bus
113 * access, giving the hardware time to complete the access.
114 * They provide more time for the (MEM) AP to complete the read ...
115 * See "Minimum Response Time" for JTAG-DP, in the ADIv5 spec.
116 */
117 if ((instr == JTAG_DP_APACC)
118 && ((reg_addr == AP_REG_DRW)
119 || ((reg_addr & 0xF0) == AP_REG_BD0))
120 && (dap->memaccess_tck != 0))
121 jtag_add_runtest(dap->memaccess_tck,
122 TAP_IDLE);
123
124 return ERROR_OK;
125 }
126
127 /**
128 * Scan DPACC or APACC out and in from host ordered uint32_t buffers.
129 * This is exactly like adi_jtag_dp_scan(), except that endianness
130 * conversions are performed (so the types of invalue and outvalue
131 * must be different).
132 */
133 static int adi_jtag_dp_scan_u32(struct adiv5_dap *dap,
134 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
135 uint32_t outvalue, uint32_t *invalue, uint8_t *ack)
136 {
137 uint8_t out_value_buf[4];
138 int retval;
139
140 buf_set_u32(out_value_buf, 0, 32, outvalue);
141
142 retval = adi_jtag_dp_scan(dap, instr, reg_addr, RnW,
143 out_value_buf, (uint8_t *)invalue, ack);
144 if (retval != ERROR_OK)
145 return retval;
146
147 if (invalue)
148 jtag_add_callback(arm_le_to_h_u32,
149 (jtag_callback_data_t) invalue);
150
151 return retval;
152 }
153
154 /**
155 * Utility to write AP registers.
156 */
157 static inline int adi_jtag_ap_write_check(struct adiv5_dap *dap,
158 uint8_t reg_addr, uint8_t *outvalue)
159 {
160 return adi_jtag_dp_scan(dap, JTAG_DP_APACC, reg_addr, DPAP_WRITE,
161 outvalue, NULL, NULL);
162 }
163
164 static int adi_jtag_scan_inout_check_u32(struct adiv5_dap *dap,
165 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
166 uint32_t outvalue, uint32_t *invalue)
167 {
168 int retval;
169
170 /* Issue the read or write */
171 retval = adi_jtag_dp_scan_u32(dap, instr, reg_addr,
172 RnW, outvalue, NULL, NULL);
173 if (retval != ERROR_OK)
174 return retval;
175
176 /* For reads, collect posted value; RDBUFF has no other effect.
177 * Assumes read gets acked with OK/FAULT, and CTRL_STAT says "OK".
178 */
179 if ((RnW == DPAP_READ) && (invalue != NULL))
180 retval = adi_jtag_dp_scan_u32(dap, JTAG_DP_DPACC,
181 DP_RDBUFF, DPAP_READ, 0, invalue, &dap->ack);
182 return retval;
183 }
184
185 static int jtagdp_transaction_endcheck(struct adiv5_dap *dap)
186 {
187 int retval;
188 uint32_t ctrlstat;
189
190 /* too expensive to call keep_alive() here */
191
192 /* Here be dragons!
193 *
194 * It is easy to be in a JTAG clock range where the target
195 * is not operating in a stable fashion. This happens
196 * for a few reasons:
197 *
198 * - the user may construct a simple test case to try to see
199 * if a higher JTAG clock works to eke out more performance.
200 * This simple case may pass, but more complex situations can
201 * fail.
202 *
203 * - The mostly works JTAG clock rate and the complete failure
204 * JTAG clock rate may be as much as 2-4x apart. This seems
205 * to be especially true on RC oscillator driven parts.
206 *
207 * So: even if calling adi_jtag_scan_inout_check_u32() multiple
208 * times here seems to "make things better here", it is just
209 * hiding problems with too high a JTAG clock.
210 *
211 * Note that even if some parts have RCLK/RTCK, that doesn't
212 * mean that RCLK/RTCK is the *correct* rate to run the JTAG
213 * interface at, i.e. RCLK/RTCK rates can be "too high", especially
214 * before the RC oscillator phase is not yet complete.
215 */
216
217 /* Post CTRL/STAT read; discard any previous posted read value
218 * but collect its ACK status.
219 */
220 retval = adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
221 DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
222 if (retval != ERROR_OK)
223 return retval;
224 retval = jtag_execute_queue();
225 if (retval != ERROR_OK)
226 return retval;
227
228 dap->ack = dap->ack & 0x7;
229
230 /* common code path avoids calling timeval_ms() */
231 if (dap->ack != JTAG_ACK_OK_FAULT) {
232 long long then = timeval_ms();
233
234 while (dap->ack != JTAG_ACK_OK_FAULT) {
235 if (dap->ack == JTAG_ACK_WAIT) {
236 if ((timeval_ms()-then) > 1000) {
237 LOG_WARNING("Timeout (1000ms) waiting "
238 "for ACK=OK/FAULT "
239 "in JTAG-DP transaction - aborting");
240
241 uint8_t ack;
242 int abort_ret = jtag_ap_q_abort(dap, &ack);
243
244 if (abort_ret != 0)
245 LOG_WARNING("Abort failed : return=%d ack=%d", abort_ret, ack);
246
247 return ERROR_JTAG_DEVICE_ERROR;
248 }
249 } else {
250 LOG_WARNING("Invalid ACK %#x "
251 "in JTAG-DP transaction",
252 dap->ack);
253 return ERROR_JTAG_DEVICE_ERROR;
254 }
255
256 retval = adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
257 DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
258 if (retval != ERROR_OK)
259 return retval;
260 retval = jtag_execute_queue();
261 if (retval != ERROR_OK)
262 return retval;
263 dap->ack = dap->ack & 0x7;
264 }
265 }
266
267 /* REVISIT also STICKYCMP, for pushed comparisons (nyet used) */
268
269 /* Check for STICKYERR and STICKYORUN */
270 if (ctrlstat & (SSTICKYORUN | SSTICKYERR)) {
271 LOG_DEBUG("jtag-dp: CTRL/STAT error, 0x%" PRIx32, ctrlstat);
272 /* Check power to debug regions */
273 if ((ctrlstat & 0xf0000000) != 0xf0000000) {
274 retval = ahbap_debugport_init(dap);
275 if (retval != ERROR_OK)
276 return retval;
277 } else {
278 uint32_t mem_ap_csw, mem_ap_tar;
279
280 /* Maybe print information about last intended
281 * MEM-AP access; but not if autoincrementing.
282 * *Real* CSW and TAR values are always shown.
283 */
284 if (dap->ap_tar_value != (uint32_t) -1)
285 LOG_DEBUG("MEM-AP Cached values: "
286 "ap_bank 0x%" PRIx32
287 ", ap_csw 0x%" PRIx32
288 ", ap_tar 0x%" PRIx32,
289 dap->ap_bank_value,
290 dap->ap_csw_value,
291 dap->ap_tar_value);
292
293 if (ctrlstat & SSTICKYORUN)
294 LOG_ERROR("JTAG-DP OVERRUN - check clock, "
295 "memaccess, or reduce jtag speed");
296
297 if (ctrlstat & SSTICKYERR)
298 LOG_ERROR("JTAG-DP STICKY ERROR");
299
300 /* Clear Sticky Error Bits */
301 retval = adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
302 DP_CTRL_STAT, DPAP_WRITE,
303 dap->dp_ctrl_stat | SSTICKYORUN
304 | SSTICKYERR, NULL);
305 if (retval != ERROR_OK)
306 return retval;
307 retval = adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
308 DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
309 if (retval != ERROR_OK)
310 return retval;
311 retval = jtag_execute_queue();
312 if (retval != ERROR_OK)
313 return retval;
314
315 LOG_DEBUG("jtag-dp: CTRL/STAT 0x%" PRIx32, ctrlstat);
316
317 retval = dap_queue_ap_read(dap,
318 AP_REG_CSW, &mem_ap_csw);
319 if (retval != ERROR_OK)
320 return retval;
321
322 retval = dap_queue_ap_read(dap,
323 AP_REG_TAR, &mem_ap_tar);
324 if (retval != ERROR_OK)
325 return retval;
326
327 retval = jtag_execute_queue();
328 if (retval != ERROR_OK)
329 return retval;
330 LOG_ERROR("MEM_AP_CSW 0x%" PRIx32 ", MEM_AP_TAR 0x%"
331 PRIx32, mem_ap_csw, mem_ap_tar);
332
333 }
334 retval = jtag_execute_queue();
335 if (retval != ERROR_OK)
336 return retval;
337 return ERROR_JTAG_DEVICE_ERROR;
338 }
339
340 return ERROR_OK;
341 }
342
343 /*--------------------------------------------------------------------------*/
344
345 static int jtag_idcode_q_read(struct adiv5_dap *dap,
346 uint8_t *ack, uint32_t *data)
347 {
348 struct arm_jtag *jtag_info = dap->jtag_info;
349 int retval;
350 struct scan_field fields[1];
351
352 /* This is a standard JTAG operation -- no DAP tweakage */
353 retval = arm_jtag_set_instr(jtag_info, JTAG_DP_IDCODE, NULL, TAP_IDLE);
354 if (retval != ERROR_OK)
355 return retval;
356
357 fields[0].num_bits = 32;
358 fields[0].out_value = NULL;
359 fields[0].in_value = (void *) data;
360
361 jtag_add_dr_scan(jtag_info->tap, 1, fields, TAP_IDLE);
362
363 jtag_add_callback(arm_le_to_h_u32,
364 (jtag_callback_data_t) data);
365
366 return ERROR_OK;
367 }
368
369 static int jtag_dp_q_read(struct adiv5_dap *dap, unsigned reg,
370 uint32_t *data)
371 {
372 return adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
373 reg, DPAP_READ, 0, data);
374 }
375
376 static int jtag_dp_q_write(struct adiv5_dap *dap, unsigned reg,
377 uint32_t data)
378 {
379 return adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
380 reg, DPAP_WRITE, data, NULL);
381 }
382
383 /** Select the AP register bank matching bits 7:4 of reg. */
384 static int jtag_ap_q_bankselect(struct adiv5_dap *dap, unsigned reg)
385 {
386 uint32_t select_ap_bank = reg & 0x000000F0;
387
388 if (select_ap_bank == dap->ap_bank_value)
389 return ERROR_OK;
390 dap->ap_bank_value = select_ap_bank;
391
392 select_ap_bank |= dap->ap_current;
393
394 return jtag_dp_q_write(dap, DP_SELECT, select_ap_bank);
395 }
396
397 static int jtag_ap_q_read(struct adiv5_dap *dap, unsigned reg,
398 uint32_t *data)
399 {
400 int retval = jtag_ap_q_bankselect(dap, reg);
401
402 if (retval != ERROR_OK)
403 return retval;
404
405 return adi_jtag_scan_inout_check_u32(dap, JTAG_DP_APACC, reg,
406 DPAP_READ, 0, data);
407 }
408
409 static int jtag_ap_q_write(struct adiv5_dap *dap, unsigned reg,
410 uint32_t data)
411 {
412 uint8_t out_value_buf[4];
413
414 int retval = jtag_ap_q_bankselect(dap, reg);
415 if (retval != ERROR_OK)
416 return retval;
417
418 buf_set_u32(out_value_buf, 0, 32, data);
419
420 return adi_jtag_ap_write_check(dap, reg, out_value_buf);
421 }
422
423 static int jtag_ap_q_read_block(struct adiv5_dap *dap, unsigned reg,
424 uint32_t blocksize, uint8_t *buffer)
425 {
426 uint32_t readcount;
427 int retval = ERROR_OK;
428
429 /* Scan out first read */
430 retval = adi_jtag_dp_scan(dap, JTAG_DP_APACC, reg,
431 DPAP_READ, 0, NULL, NULL);
432 if (retval != ERROR_OK)
433 return retval;
434
435 for (readcount = 0; readcount < blocksize - 1; readcount++) {
436 /* Scan out next read; scan in posted value for the
437 * previous one. Assumes read is acked "OK/FAULT",
438 * and CTRL_STAT says that meant "OK".
439 */
440 retval = adi_jtag_dp_scan(dap, JTAG_DP_APACC, reg,
441 DPAP_READ, 0, buffer + 4 * readcount,
442 &dap->ack);
443 if (retval != ERROR_OK)
444 return retval;
445 }
446
447 /* Scan in last posted value; RDBUFF has no other effect,
448 * assuming ack is OK/FAULT and CTRL_STAT says "OK".
449 */
450 retval = adi_jtag_dp_scan(dap, JTAG_DP_DPACC, DP_RDBUFF,
451 DPAP_READ, 0, buffer + 4 * readcount,
452 &dap->ack);
453
454 return retval;
455 }
456
457 static int jtag_ap_q_abort(struct adiv5_dap *dap, uint8_t *ack)
458 {
459 /* for JTAG, this is the only valid ABORT register operation */
460 return adi_jtag_dp_scan_u32(dap, JTAG_DP_ABORT,
461 0, DPAP_WRITE, 1, NULL, ack);
462 }
463
464 static int jtag_dp_run(struct adiv5_dap *dap)
465 {
466 return jtagdp_transaction_endcheck(dap);
467 }
468
469 /* FIXME don't export ... just initialize as
470 * part of DAP setup
471 */
472 const struct dap_ops jtag_dp_ops = {
473 .queue_idcode_read = jtag_idcode_q_read,
474 .queue_dp_read = jtag_dp_q_read,
475 .queue_dp_write = jtag_dp_q_write,
476 .queue_ap_read = jtag_ap_q_read,
477 .queue_ap_write = jtag_ap_q_write,
478 .queue_ap_read_block = jtag_ap_q_read_block,
479 .queue_ap_abort = jtag_ap_q_abort,
480 .run = jtag_dp_run,
481 };
482
483
484 static const uint8_t swd2jtag_bitseq[] = {
485 /* More than 50 TCK/SWCLK cycles with TMS/SWDIO high,
486 * putting both JTAG and SWD logic into reset state.
487 */
488 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
489 /* Switching equence disables SWD and enables JTAG
490 * NOTE: bits in the DP's IDCODE can expose the need for
491 * the old/deprecated sequence (0xae 0xde).
492 */
493 0x3c, 0xe7,
494 /* At least 50 TCK/SWCLK cycles with TMS/SWDIO high,
495 * putting both JTAG and SWD logic into reset state.
496 * NOTE: some docs say "at least 5".
497 */
498 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
499 };
500
501 /** Put the debug link into JTAG mode, if the target supports it.
502 * The link's initial mode may be either SWD or JTAG.
503 *
504 * @param target Enters JTAG mode (if possible).
505 *
506 * Note that targets implemented with SW-DP do not support JTAG, and
507 * that some targets which could otherwise support it may have been
508 * configured to disable JTAG signaling
509 *
510 * @return ERROR_OK or else a fault code.
511 */
512 int dap_to_jtag(struct target *target)
513 {
514 int retval;
515
516 LOG_DEBUG("Enter JTAG mode");
517
518 /* REVISIT it's nasty to need to make calls to a "jtag"
519 * subsystem if the link isn't in JTAG mode...
520 */
521
522 retval = jtag_add_tms_seq(8 * sizeof(swd2jtag_bitseq),
523 swd2jtag_bitseq, TAP_RESET);
524 if (retval == ERROR_OK)
525 retval = jtag_execute_queue();
526
527 /* REVISIT set up the DAP's ops vector for JTAG mode. */
528
529 return retval;
530 }