2753713c36f05f16a054bfd5b93aacd6940df5ee
[openocd.git] / src / target / adi_v5_jtag.c
1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin
3 * lundin@mlu.mine.nu
4 *
5 * Copyright (C) 2008 by Spencer Oliver
6 * spen@spen-soft.co.uk
7 *
8 * Copyright (C) 2009 by Oyvind Harboe
9 * oyvind.harboe@zylin.com
10 *
11 * Copyright (C) 2009-2010 by David Brownell
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the
25 * Free Software Foundation, Inc.,
26 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
27 ***************************************************************************/
28
29 /**
30 * @file
31 * This file implements JTAG transport support for cores implementing
32 the ARM Debug Interface version 5 (ADIv5).
33 */
34
35 #ifdef HAVE_CONFIG_H
36 #include "config.h"
37 #endif
38
39 #include "arm.h"
40 #include "arm_adi_v5.h"
41 #include <helper/time_support.h>
42
43 /* JTAG instructions/registers for JTAG-DP and SWJ-DP */
44 #define JTAG_DP_ABORT 0x8
45 #define JTAG_DP_DPACC 0xA
46 #define JTAG_DP_APACC 0xB
47 #define JTAG_DP_IDCODE 0xE
48
49 /* three-bit ACK values for DPACC and APACC reads */
50 #define JTAG_ACK_OK_FAULT 0x2
51 #define JTAG_ACK_WAIT 0x1
52
53 static int jtag_ap_q_abort(struct adiv5_dap *dap, uint8_t *ack);
54
55 /***************************************************************************
56 *
57 * DPACC and APACC scanchain access through JTAG-DP (or SWJ-DP)
58 *
59 ***************************************************************************/
60
61 /**
62 * Scan DPACC or APACC using target ordered uint8_t buffers. No endianness
63 * conversions are performed. See section 4.4.3 of the ADIv5 spec, which
64 * discusses operations which access these registers.
65 *
66 * Note that only one scan is performed. If RnW is set, a separate scan
67 * will be needed to collect the data which was read; the "invalue" collects
68 * the posted result of a preceding operation, not the current one.
69 *
70 * @param dap the DAP
71 * @param instr JTAG_DP_APACC (AP access) or JTAG_DP_DPACC (DP access)
72 * @param reg_addr two significant bits; A[3:2]; for APACC access, the
73 * SELECT register has more addressing bits.
74 * @param RnW false iff outvalue will be written to the DP or AP
75 * @param outvalue points to a 32-bit (little-endian) integer
76 * @param invalue NULL, or points to a 32-bit (little-endian) integer
77 * @param ack points to where the three bit JTAG_ACK_* code will be stored
78 */
79
80 static int adi_jtag_dp_scan(struct adiv5_dap *dap,
81 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
82 uint8_t *outvalue, uint8_t *invalue, uint8_t *ack)
83 {
84 struct jtag_tap *tap = dap->tap;
85 struct scan_field fields[2];
86 uint8_t out_addr_buf;
87 int retval;
88
89 retval = arm_jtag_set_instr(tap, instr, NULL, TAP_IDLE);
90 if (retval != ERROR_OK)
91 return retval;
92
93 /* Scan out a read or write operation using some DP or AP register.
94 * For APACC access with any sticky error flag set, this is discarded.
95 */
96 fields[0].num_bits = 3;
97 buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr >> 1) & 0x6) | (RnW & 0x1));
98 fields[0].out_value = &out_addr_buf;
99 fields[0].in_value = ack;
100
101 /* NOTE: if we receive JTAG_ACK_WAIT, the previous operation did not
102 * complete; data we write is discarded, data we read is unpredictable.
103 * When overrun detect is active, STICKYORUN is set.
104 */
105
106 fields[1].num_bits = 32;
107 fields[1].out_value = outvalue;
108 fields[1].in_value = invalue;
109
110 jtag_add_dr_scan(tap, 2, fields, TAP_IDLE);
111
112 /* Add specified number of tck clocks after starting memory bus
113 * access, giving the hardware time to complete the access.
114 * They provide more time for the (MEM) AP to complete the read ...
115 * See "Minimum Response Time" for JTAG-DP, in the ADIv5 spec.
116 */
117 if ((instr == JTAG_DP_APACC)
118 && ((reg_addr == MEM_AP_REG_DRW)
119 || ((reg_addr & 0xF0) == MEM_AP_REG_BD0))
120 && (dap->ap[dap_ap_get_select(dap)].memaccess_tck != 0))
121 jtag_add_runtest(dap->ap[dap_ap_get_select(dap)].memaccess_tck,
122 TAP_IDLE);
123
124 return ERROR_OK;
125 }
126
127 /**
128 * Scan DPACC or APACC out and in from host ordered uint32_t buffers.
129 * This is exactly like adi_jtag_dp_scan(), except that endianness
130 * conversions are performed (so the types of invalue and outvalue
131 * must be different).
132 */
133 static int adi_jtag_dp_scan_u32(struct adiv5_dap *dap,
134 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
135 uint32_t outvalue, uint32_t *invalue, uint8_t *ack)
136 {
137 uint8_t out_value_buf[4];
138 int retval;
139
140 buf_set_u32(out_value_buf, 0, 32, outvalue);
141
142 retval = adi_jtag_dp_scan(dap, instr, reg_addr, RnW,
143 out_value_buf, (uint8_t *)invalue, ack);
144 if (retval != ERROR_OK)
145 return retval;
146
147 if (invalue)
148 jtag_add_callback(arm_le_to_h_u32,
149 (jtag_callback_data_t) invalue);
150
151 return retval;
152 }
153
154 /**
155 * Utility to write AP registers.
156 */
157 static inline int adi_jtag_ap_write_check(struct adiv5_dap *dap,
158 uint8_t reg_addr, uint8_t *outvalue)
159 {
160 return adi_jtag_dp_scan(dap, JTAG_DP_APACC, reg_addr, DPAP_WRITE,
161 outvalue, NULL, NULL);
162 }
163
164 static int adi_jtag_scan_inout_check_u32(struct adiv5_dap *dap,
165 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
166 uint32_t outvalue, uint32_t *invalue)
167 {
168 int retval;
169
170 /* Issue the read or write */
171 retval = adi_jtag_dp_scan_u32(dap, instr, reg_addr,
172 RnW, outvalue, NULL, NULL);
173 if (retval != ERROR_OK)
174 return retval;
175
176 /* For reads, collect posted value; RDBUFF has no other effect.
177 * Assumes read gets acked with OK/FAULT, and CTRL_STAT says "OK".
178 */
179 if ((RnW == DPAP_READ) && (invalue != NULL))
180 retval = adi_jtag_dp_scan_u32(dap, JTAG_DP_DPACC,
181 DP_RDBUFF, DPAP_READ, 0, invalue, &dap->ack);
182 return retval;
183 }
184
185 static int jtagdp_transaction_endcheck(struct adiv5_dap *dap)
186 {
187 int retval;
188 uint32_t ctrlstat;
189
190 /* too expensive to call keep_alive() here */
191
192 /* Here be dragons!
193 *
194 * It is easy to be in a JTAG clock range where the target
195 * is not operating in a stable fashion. This happens
196 * for a few reasons:
197 *
198 * - the user may construct a simple test case to try to see
199 * if a higher JTAG clock works to eke out more performance.
200 * This simple case may pass, but more complex situations can
201 * fail.
202 *
203 * - The mostly works JTAG clock rate and the complete failure
204 * JTAG clock rate may be as much as 2-4x apart. This seems
205 * to be especially true on RC oscillator driven parts.
206 *
207 * So: even if calling adi_jtag_scan_inout_check_u32() multiple
208 * times here seems to "make things better here", it is just
209 * hiding problems with too high a JTAG clock.
210 *
211 * Note that even if some parts have RCLK/RTCK, that doesn't
212 * mean that RCLK/RTCK is the *correct* rate to run the JTAG
213 * interface at, i.e. RCLK/RTCK rates can be "too high", especially
214 * before the RC oscillator phase is not yet complete.
215 */
216
217 /* Post CTRL/STAT read; discard any previous posted read value
218 * but collect its ACK status.
219 */
220 retval = adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
221 DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
222 if (retval != ERROR_OK)
223 return retval;
224 retval = jtag_execute_queue();
225 if (retval != ERROR_OK)
226 return retval;
227
228 dap->ack = dap->ack & 0x7;
229
230 /* common code path avoids calling timeval_ms() */
231 if (dap->ack != JTAG_ACK_OK_FAULT) {
232 long long then = timeval_ms();
233
234 while (dap->ack != JTAG_ACK_OK_FAULT) {
235 if (dap->ack == JTAG_ACK_WAIT) {
236 if ((timeval_ms()-then) > 1000) {
237 LOG_WARNING("Timeout (1000ms) waiting "
238 "for ACK=OK/FAULT "
239 "in JTAG-DP transaction - aborting");
240
241 uint8_t ack;
242 int abort_ret = jtag_ap_q_abort(dap, &ack);
243
244 if (abort_ret != 0)
245 LOG_WARNING("Abort failed : return=%d ack=%d", abort_ret, ack);
246
247 return ERROR_JTAG_DEVICE_ERROR;
248 }
249 } else {
250 LOG_WARNING("Invalid ACK %#x "
251 "in JTAG-DP transaction",
252 dap->ack);
253 return ERROR_JTAG_DEVICE_ERROR;
254 }
255
256 retval = adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
257 DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
258 if (retval != ERROR_OK)
259 return retval;
260 retval = jtag_execute_queue();
261 if (retval != ERROR_OK)
262 return retval;
263 dap->ack = dap->ack & 0x7;
264 }
265 }
266
267 /* REVISIT also STICKYCMP, for pushed comparisons (nyet used) */
268
269 /* Check for STICKYERR and STICKYORUN */
270 if (ctrlstat & (SSTICKYORUN | SSTICKYERR)) {
271 LOG_DEBUG("jtag-dp: CTRL/STAT error, 0x%" PRIx32, ctrlstat);
272 /* Check power to debug regions */
273 if ((ctrlstat & 0xf0000000) != 0xf0000000) {
274 LOG_ERROR("Debug regions are unpowered, an unexpected reset might have happened");
275 return ERROR_JTAG_DEVICE_ERROR;
276 } else {
277 if (ctrlstat & SSTICKYORUN)
278 LOG_ERROR("JTAG-DP OVERRUN - check clock, "
279 "memaccess, or reduce jtag speed");
280
281 if (ctrlstat & SSTICKYERR)
282 LOG_ERROR("JTAG-DP STICKY ERROR");
283
284 /* Clear Sticky Error Bits */
285 retval = adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
286 DP_CTRL_STAT, DPAP_WRITE,
287 dap->dp_ctrl_stat | SSTICKYORUN
288 | SSTICKYERR, NULL);
289 if (retval != ERROR_OK)
290 return retval;
291 retval = adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
292 DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
293 if (retval != ERROR_OK)
294 return retval;
295 retval = jtag_execute_queue();
296 if (retval != ERROR_OK)
297 return retval;
298
299 LOG_DEBUG("jtag-dp: CTRL/STAT 0x%" PRIx32, ctrlstat);
300 }
301 retval = jtag_execute_queue();
302 if (retval != ERROR_OK)
303 return retval;
304 return ERROR_JTAG_DEVICE_ERROR;
305 }
306
307 return ERROR_OK;
308 }
309
310 /*--------------------------------------------------------------------------*/
311
312 static int jtag_dp_q_read(struct adiv5_dap *dap, unsigned reg,
313 uint32_t *data)
314 {
315 return adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
316 reg, DPAP_READ, 0, data);
317 }
318
319 static int jtag_dp_q_write(struct adiv5_dap *dap, unsigned reg,
320 uint32_t data)
321 {
322 return adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
323 reg, DPAP_WRITE, data, NULL);
324 }
325
326 /** Select the AP register bank matching bits 7:4 of reg. */
327 static int jtag_ap_q_bankselect(struct adiv5_dap *dap, unsigned reg)
328 {
329 uint32_t select_ap_bank = reg & 0x000000F0;
330
331 if (select_ap_bank == dap->ap_bank_value)
332 return ERROR_OK;
333 dap->ap_bank_value = select_ap_bank;
334
335 select_ap_bank |= dap->ap_current;
336
337 return jtag_dp_q_write(dap, DP_SELECT, select_ap_bank);
338 }
339
340 static int jtag_ap_q_read(struct adiv5_dap *dap, unsigned reg,
341 uint32_t *data)
342 {
343 int retval = jtag_ap_q_bankselect(dap, reg);
344
345 if (retval != ERROR_OK)
346 return retval;
347
348 return adi_jtag_scan_inout_check_u32(dap, JTAG_DP_APACC, reg,
349 DPAP_READ, 0, data);
350 }
351
352 static int jtag_ap_q_write(struct adiv5_dap *dap, unsigned reg,
353 uint32_t data)
354 {
355 uint8_t out_value_buf[4];
356
357 int retval = jtag_ap_q_bankselect(dap, reg);
358 if (retval != ERROR_OK)
359 return retval;
360
361 buf_set_u32(out_value_buf, 0, 32, data);
362
363 return adi_jtag_ap_write_check(dap, reg, out_value_buf);
364 }
365
366 static int jtag_ap_q_abort(struct adiv5_dap *dap, uint8_t *ack)
367 {
368 /* for JTAG, this is the only valid ABORT register operation */
369 return adi_jtag_dp_scan_u32(dap, JTAG_DP_ABORT,
370 0, DPAP_WRITE, 1, NULL, ack);
371 }
372
373 static int jtag_dp_run(struct adiv5_dap *dap)
374 {
375 return jtagdp_transaction_endcheck(dap);
376 }
377
378 /* FIXME don't export ... just initialize as
379 * part of DAP setup
380 */
381 const struct dap_ops jtag_dp_ops = {
382 .queue_dp_read = jtag_dp_q_read,
383 .queue_dp_write = jtag_dp_q_write,
384 .queue_ap_read = jtag_ap_q_read,
385 .queue_ap_write = jtag_ap_q_write,
386 .queue_ap_abort = jtag_ap_q_abort,
387 .run = jtag_dp_run,
388 };
389
390
391 static const uint8_t swd2jtag_bitseq[] = {
392 /* More than 50 TCK/SWCLK cycles with TMS/SWDIO high,
393 * putting both JTAG and SWD logic into reset state.
394 */
395 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
396 /* Switching equence disables SWD and enables JTAG
397 * NOTE: bits in the DP's IDCODE can expose the need for
398 * the old/deprecated sequence (0xae 0xde).
399 */
400 0x3c, 0xe7,
401 /* At least 50 TCK/SWCLK cycles with TMS/SWDIO high,
402 * putting both JTAG and SWD logic into reset state.
403 * NOTE: some docs say "at least 5".
404 */
405 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
406 };
407
408 /** Put the debug link into JTAG mode, if the target supports it.
409 * The link's initial mode may be either SWD or JTAG.
410 *
411 * @param target Enters JTAG mode (if possible).
412 *
413 * Note that targets implemented with SW-DP do not support JTAG, and
414 * that some targets which could otherwise support it may have been
415 * configured to disable JTAG signaling
416 *
417 * @return ERROR_OK or else a fault code.
418 */
419 int dap_to_jtag(struct target *target)
420 {
421 int retval;
422
423 LOG_DEBUG("Enter JTAG mode");
424
425 /* REVISIT it's nasty to need to make calls to a "jtag"
426 * subsystem if the link isn't in JTAG mode...
427 */
428
429 retval = jtag_add_tms_seq(8 * sizeof(swd2jtag_bitseq),
430 swd2jtag_bitseq, TAP_RESET);
431 if (retval == ERROR_OK)
432 retval = jtag_execute_queue();
433
434 /* REVISIT set up the DAP's ops vector for JTAG mode. */
435
436 return retval;
437 }