xscale: Move debug handler to contrib/loaders
[openocd.git] / src / target / Makefile.am
1 include $(top_srcdir)/common.mk
2
3 if OOCD_TRACE
4 OOCD_TRACE_FILES = oocd_trace.c
5 else
6 OOCD_TRACE_FILES =
7 endif
8
9 SUBDIRS = openrisc
10 libtarget_la_LIBADD = $(top_builddir)/src/target/openrisc/libopenrisc.la
11
12
13 METASOURCES = AUTO
14 noinst_LTLIBRARIES = libtarget.la
15 libtarget_la_SOURCES = \
16 $(TARGET_CORE_SRC) \
17 $(ARM_DEBUG_SRC) \
18 $(ARMV4_5_SRC) \
19 $(ARMV6_SRC) \
20 $(ARMV7_SRC) \
21 $(ARM_MISC_SRC) \
22 $(AVR32_SRC) \
23 $(MIPS32_SRC) \
24 $(NDS32_SRC) \
25 $(INTEL_IA32_SRC) \
26 avrt.c \
27 dsp563xx.c \
28 dsp563xx_once.c \
29 dsp5680xx.c \
30 hla_target.c
31
32 TARGET_CORE_SRC = \
33 algorithm.c \
34 register.c \
35 image.c \
36 breakpoints.c \
37 target.c \
38 target_request.c \
39 testee.c \
40 smp.c
41
42 ARMV4_5_SRC = \
43 armv4_5.c \
44 armv4_5_mmu.c \
45 armv4_5_cache.c \
46 $(ARM7_9_SRC)
47
48 ARM7_9_SRC = \
49 arm7_9_common.c \
50 arm7tdmi.c \
51 arm720t.c \
52 arm9tdmi.c \
53 arm920t.c \
54 arm966e.c \
55 arm946e.c \
56 arm926ejs.c \
57 feroceon.c
58
59 ARM_MISC_SRC = \
60 fa526.c \
61 xscale.c
62
63 ARMV6_SRC = \
64 arm11.c \
65 arm11_dbgtap.c
66
67 ARMV7_SRC = \
68 armv7m.c \
69 armv7m_trace.c \
70 cortex_m.c \
71 armv7a.c \
72 cortex_a.c \
73 ls1_sap.c
74
75 ARM_DEBUG_SRC = \
76 arm_dpm.c \
77 arm_jtag.c \
78 arm_disassembler.c \
79 arm_simulator.c \
80 arm_semihosting.c \
81 arm_adi_v5.c \
82 armv7a_cache.c \
83 armv7a_cache_l2x.c \
84 adi_v5_jtag.c \
85 adi_v5_swd.c \
86 embeddedice.c \
87 trace.c \
88 etb.c \
89 etm.c \
90 $(OOCD_TRACE_FILES) \
91 etm_dummy.c
92
93 AVR32_SRC = \
94 avr32_ap7k.c \
95 avr32_jtag.c \
96 avr32_mem.c \
97 avr32_regs.c
98
99 MIPS32_SRC = \
100 mips32.c \
101 mips_m4k.c \
102 mips32_pracc.c \
103 mips32_dmaacc.c \
104 mips_ejtag.c
105
106 NDS32_SRC = \
107 nds32.c \
108 nds32_reg.c \
109 nds32_cmd.c \
110 nds32_disassembler.c \
111 nds32_tlb.c \
112 nds32_v2.c \
113 nds32_v3_common.c \
114 nds32_v3.c \
115 nds32_v3m.c \
116 nds32_aice.c
117
118 INTEL_IA32_SRC = \
119 quark_x10xx.c \
120 quark_d20xx.c \
121 lakemont.c \
122 x86_32_common.c
123
124 noinst_HEADERS = \
125 algorithm.h \
126 arm.h \
127 arm_dpm.h \
128 arm_jtag.h \
129 arm_adi_v5.h \
130 armv7a_cache.h \
131 armv7a_cache_l2x.h \
132 arm_disassembler.h \
133 arm_opcodes.h \
134 arm_simulator.h \
135 arm_semihosting.h \
136 arm7_9_common.h \
137 arm7tdmi.h \
138 arm720t.h \
139 arm9tdmi.h \
140 arm920t.h \
141 arm926ejs.h \
142 arm966e.h \
143 arm946e.h \
144 arm11.h \
145 arm11_dbgtap.h \
146 armv4_5.h \
147 armv4_5_mmu.h \
148 armv4_5_cache.h \
149 armv7a.h \
150 armv7m.h \
151 armv7m_trace.h \
152 avrt.h \
153 dsp563xx.h \
154 dsp563xx_once.h \
155 dsp5680xx.h \
156 breakpoints.h \
157 cortex_m.h \
158 cortex_a.h \
159 embeddedice.h \
160 etb.h \
161 etm.h \
162 etm_dummy.h \
163 image.h \
164 mips32.h \
165 mips_m4k.h \
166 mips_ejtag.h \
167 mips32_pracc.h \
168 mips32_dmaacc.h \
169 oocd_trace.h \
170 register.h \
171 target.h \
172 target_type.h \
173 trace.h \
174 target_request.h \
175 trace.h \
176 xscale.h \
177 smp.h \
178 avr32_ap7k.h \
179 avr32_jtag.h \
180 avr32_mem.h \
181 avr32_regs.h \
182 nds32.h \
183 nds32_cmd.h \
184 nds32_disassembler.h \
185 nds32_edm.h \
186 nds32_insn.h \
187 nds32_reg.h \
188 nds32_tlb.h \
189 nds32_v2.h \
190 nds32_v3_common.h \
191 nds32_v3.h \
192 nds32_v3m.h \
193 nds32_aice.h \
194 lakemont.h \
195 x86_32_common.h
196
197 ocddatadir = $(pkglibdir)
198 nobase_dist_ocddata_DATA =
199
200 MAINTAINERCLEANFILES = $(srcdir)/Makefile.in

Linking to existing account procedure

If you already have an account and want to add another login method you MUST first sign in with your existing account and then change URL to read https://review.openocd.org/login/?link to get to this page again but this time it'll work for linking. Thank you.

SSH host keys fingerprints

1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=..              |
|+o..   .         |
|*.o   . .        |
|+B . . .         |
|Bo. = o S        |
|Oo.+ + =         |
|oB=.* = . o      |
| =+=.+   + E     |
|. .=o   . o      |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)