Add new target type: OpenRISC
[openocd.git] / src / target / Makefile.am
1 include $(top_srcdir)/common.mk
2
3 if OOCD_TRACE
4 OOCD_TRACE_FILES = oocd_trace.c
5 else
6 OOCD_TRACE_FILES =
7 endif
8
9 SUBDIRS = openrisc
10 libtarget_la_LIBADD = $(top_builddir)/src/target/openrisc/libopenrisc.la
11
12 BIN2C = $(top_builddir)/src/helper/bin2char$(EXEEXT_FOR_BUILD)
13
14 DEBUG_HANDLER = $(srcdir)/xscale/debug_handler.bin
15 EXTRA_DIST = \
16 startup.tcl \
17 $(DEBUG_HANDLER)
18
19 DEBUG_HEADER = xscale_debug.h
20 BUILT_SOURCES = $(DEBUG_HEADER)
21 CLEANFILES = $(DEBUG_HEADER)
22
23 $(DEBUG_HEADER): $(BIN2C) $(DEBUG_HANDLER)
24 $(BIN2C) < $(DEBUG_HANDLER) xscale_debug_handler > xscale_debug.h
25
26 METASOURCES = AUTO
27 noinst_LTLIBRARIES = libtarget.la
28 libtarget_la_SOURCES = \
29 $(TARGET_CORE_SRC) \
30 $(ARM_DEBUG_SRC) \
31 $(ARMV4_5_SRC) \
32 $(ARMV6_SRC) \
33 $(ARMV7_SRC) \
34 $(ARM_MISC_SRC) \
35 $(AVR32_SRC) \
36 $(MIPS32_SRC) \
37 $(NDS32_SRC) \
38 avrt.c \
39 dsp563xx.c \
40 dsp563xx_once.c \
41 dsp5680xx.c \
42 hla_target.c
43
44 TARGET_CORE_SRC = \
45 algorithm.c \
46 register.c \
47 image.c \
48 breakpoints.c \
49 target.c \
50 target_request.c \
51 testee.c \
52 smp.c
53
54 ARMV4_5_SRC = \
55 armv4_5.c \
56 armv4_5_mmu.c \
57 armv4_5_cache.c \
58 $(ARM7_9_SRC)
59
60 ARM7_9_SRC = \
61 arm7_9_common.c \
62 arm7tdmi.c \
63 arm720t.c \
64 arm9tdmi.c \
65 arm920t.c \
66 arm966e.c \
67 arm946e.c \
68 arm926ejs.c \
69 feroceon.c
70
71 ARM_MISC_SRC = \
72 fa526.c \
73 xscale.c
74
75 ARMV6_SRC = \
76 arm11.c \
77 arm11_dbgtap.c
78
79 ARMV7_SRC = \
80 armv7m.c \
81 cortex_m.c \
82 armv7a.c \
83 cortex_a.c
84
85 ARM_DEBUG_SRC = \
86 arm_dpm.c \
87 arm_jtag.c \
88 arm_disassembler.c \
89 arm_simulator.c \
90 arm_semihosting.c \
91 arm_adi_v5.c \
92 adi_v5_jtag.c \
93 adi_v5_swd.c \
94 embeddedice.c \
95 trace.c \
96 etb.c \
97 etm.c \
98 $(OOCD_TRACE_FILES) \
99 etm_dummy.c
100
101 AVR32_SRC = \
102 avr32_ap7k.c \
103 avr32_jtag.c \
104 avr32_mem.c \
105 avr32_regs.c
106
107 MIPS32_SRC = \
108 mips32.c \
109 mips_m4k.c \
110 mips32_pracc.c \
111 mips32_dmaacc.c \
112 mips_ejtag.c
113
114 NDS32_SRC = \
115 nds32.c \
116 nds32_reg.c \
117 nds32_cmd.c \
118 nds32_disassembler.c \
119 nds32_tlb.c \
120 nds32_v2.c \
121 nds32_v3_common.c \
122 nds32_v3.c \
123 nds32_v3m.c \
124 nds32_aice.c
125
126
127 noinst_HEADERS = \
128 algorithm.h \
129 arm.h \
130 arm_dpm.h \
131 arm_jtag.h \
132 arm_adi_v5.h \
133 arm_disassembler.h \
134 arm_opcodes.h \
135 arm_simulator.h \
136 arm_semihosting.h \
137 arm7_9_common.h \
138 arm7tdmi.h \
139 arm720t.h \
140 arm9tdmi.h \
141 arm920t.h \
142 arm926ejs.h \
143 arm966e.h \
144 arm946e.h \
145 arm11.h \
146 arm11_dbgtap.h \
147 armv4_5.h \
148 armv4_5_mmu.h \
149 armv4_5_cache.h \
150 armv7a.h \
151 armv7m.h \
152 avrt.h \
153 dsp563xx.h \
154 dsp563xx_once.h \
155 dsp5680xx.h \
156 breakpoints.h \
157 cortex_m.h \
158 cortex_a.h \
159 embeddedice.h \
160 etb.h \
161 etm.h \
162 etm_dummy.h \
163 image.h \
164 mips32.h \
165 mips_m4k.h \
166 mips_ejtag.h \
167 mips32_pracc.h \
168 mips32_dmaacc.h \
169 oocd_trace.h \
170 register.h \
171 target.h \
172 target_type.h \
173 trace.h \
174 target_request.h \
175 trace.h \
176 xscale.h \
177 smp.h \
178 avr32_ap7k.h \
179 avr32_jtag.h \
180 avr32_mem.h \
181 avr32_regs.h \
182 nds32.h \
183 nds32_cmd.h \
184 nds32_disassembler.h \
185 nds32_edm.h \
186 nds32_insn.h \
187 nds32_reg.h \
188 nds32_tlb.h \
189 nds32_v2.h \
190 nds32_v3_common.h \
191 nds32_v3.h \
192 nds32_v3m.h \
193 nds32_aice.h
194
195 ocddatadir = $(pkglibdir)
196 nobase_dist_ocddata_DATA =
197
198 MAINTAINERCLEANFILES = $(srcdir)/Makefile.in

Linking to existing account procedure

If you already have an account and want to add another login method you MUST first sign in with your existing account and then change URL to read https://review.openocd.org/login/?link to get to this page again but this time it'll work for linking. Thank you.

SSH host keys fingerprints

1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=..              |
|+o..   .         |
|*.o   . .        |
|+B . . .         |
|Bo. = o S        |
|Oo.+ + =         |
|oB=.* = . o      |
| =+=.+   + E     |
|. .=o   . o      |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)